WM8959 ultra-low power hi-fi designed multimedia handsets. powerful sp
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Mobile Multimedia with Dual-Mode Class AB/D Speaker Driver
WM8959 ultra-low power hi-fi designed multimedia handsets. powerful speaker driver operate class modes, providing total flexibility system designer. leakage, high PSRR pop/click suppression enable direct battery connection speaker supply. flexible input configuration supports microphone inputs (single-ended differential), stereo line input, mono differential line input. Four headphone drivers support fully differential headset drive, providing excellent crosstalk performance bass response, maximising stereo effects, allowing removal large expensive headphone capacitors. headphone outputs also configured drive speaker. fully differential path these outputs direct from input pins available maximise signal quality minimise power consumption. Stereo 24-bit sigma-delta DACs provide hi-fi quality audio playback, with flexible digital audio interface supporting most commonly-used clocking schemes. integrated power provides additional flexibility. WM8959 supplied very small thin 42-ball WCSP package, ideal portable systems.
WM8959
FEATURES
99dB (`A' weighted), -84dB 48kHz, 3.3V Stereo microphone interface Speaker driver into speaker <0.1% 80dB PSRR 217Hz <1uA leakage with direct battery connection Software-selectable class mode Filterless connection supported Headphone speaker drivers 40mW output power into 3.3V Fully differential capless modes supported noise, lower power received voice path Stereo Mono differential line output Pop/Click suppression Powerful GPIO functions Ultra-low power consumption 8.3mW analogue voice call 13.7mW playback headphones On-chip provides flexible clocking scheme Sample rates: 11.025, 22.05, 44.1, 48kHz 42-ball WCSP package (3.226x3.44x0.7mm, 0.5mm pitch)
APPLICATIONS
Multimedia phones
WOLFSON MICROELECTRONICS
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Pre-Production, 2008,
Copyright ©2008 Wolfson Microelectronics
WM8959 TABLE CONTENTS
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DESCRIPTION FEATURES APPLICATIONS TABLE CONTENTS BLOCK DIAGRAM CONFIGURATION. ORDERING INFORMATION DESCRIPTION ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS THERMAL PERFORMANCE. SPEAKER POWER DE-RATING CURVE ELECTRICAL CHARACTERISTICS. TERMINOLOGY TYPICAL POWER CONSUMPTION. SPEAKER DRIVER PERFORMANCE. HEADPHONE DRIVER PERFORMANCE PSRR PERFORMANCE AUDIO SIGNAL PATHS SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING AUDIO INTERFACE TIMING MASTER MODE AUDIO INTERFACE TIMING SLAVE MODE CONTROL INTERFACE TIMING 2-WIRE MODE CONTROL INTERFACE TIMING 3-WIRE MODE CONTROL INTERFACE TIMING 4-WIRE MODE
INTERNAL POWER RESET CIRCUIT DEVICE DESCRIPTION
INTRODUCTION ANALOGUE INPUT PATH DIGITAL INPUT PATH DIGITAL ANALOGUE CONVERTER (DAC) OUTPUT SIGNAL PATH ANALOGUE OUTPUTS.67 THERMAL SHUTDOWN GENERAL PURPOSE INPUT/OUTPUT DIGITAL AUDIO INTERFACE DIGITAL AUDIO INTERFACE CONTROL .100 CLOCKING SAMPLE RATES.104 CONTROL INTERFACE.112 POWER MANAGEMENT .116 SUPPRESSION CONTROL.119 POWER DOMAINS .124
REGISTER MAP.
REGISTER BITS ADDRESS .127
DIGITAL FILTER CHARACTERISTICS.
FILTER RESPONSES .149 DE-EMPHASIS FILTER RESPONSES .150
APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS. PACKAGE DIMENSIONS. IMPORTANT NOTICE
ADDRESS.155
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LONMIX
Mixer Mixer
Line
0dB, -6dB
Line
INPUT PGAs
Mixer
INPUT MIXERS
LOPMIX
Left Line Input Speaker Voice Left Line Input Left Output Mixer Left AINLMUX output Mixer
-12dB +6dB
-12dB +6dB MONO
RXVOICE AINLMUX
-73dB +6dB, steps
DIFFINL
-12dB +6dB
-12dB +6dB
RXVOICE DIFFINR
-16.5dB +30dB, 0.75dB steps 0dB, +30dB 0dB, +30dB
MICBIAS Current Detect
MICBIAS AVDD DCVDD
A-law u-law support Support Alternative Interface Button Control Accessory Detect Clock Output
RIN1 RIN2
-12dB 0dB, steps AINRMUX output Right Right Line Input Right Output Mixer Voice Right Line Input Speaker
RIN3/GPI8 RIN4/RXP
LIN3 RIN3
RIN34
-12dB +6dB
-16.5dB +30dB, 0.75dB steps
RIN12
VREF Inverted Mixer Mixer
250k
250k
LIN3/GPI7 LIN4/RXN
0dB, +30dB 0dB, +30dB Bypass Bypass AINLMUX -71.625dB 0dB, 0.375dB steps
LIN1 LIN2
BLOCK DIAGRAM
WM8959
Inverted
OUTPUT MIXERS
-16.5dB +30dB, 0.75dB steps
OUT3MIX
0dB, -6dB
OUT3
LIN12
-12dB +6dB RIN3
INMIXL
LIN3
-16.5dB +30dB, 0.75dB steps
DIGITAL CORE
-73dB +6dB, steps
LOPGA
LIN2 Mixer
LOUT
LIN34
-12dB 0dB, steps
SPKMIX SPKPGA
-73dB +6dB, steps
LOMIX
1.27x, 1.4x, 1.52x, 1.67x 1.8x Mixer
Bypass Bypass
RIN2 AINRMUX 0dB, -6dB, -12dB
SPKN SPKP
1xVMID, 1.27xVMID, 1.4xVMID, 1.52xVMID, 1.67xVMID 1.8xVMID
AINRMUX ROMIX
-73dB +6dB, steps
INMIXR
-71.625dB 0dB, 0.375dB steps
ROPGA
-73dB +6dB, steps
ROUT
0dB, +6dB, +12dB, +18dB
Mixer
OUT4 OUT4MIX
0dB, -6dB
Mixer
ROPMIX
0dB, -6dB Line
DIGITAL AUDIO INTERFACE GPIO
Line
RONMIX
SYSCLK
CONTROL INTERFACE
VMID
AGND AVDD BCLK DGND DCVDD DBVDD DACDAT DACLRC HPVDD HPGND SPKVDD SPKGND
MCLK
CSB/ADDR SDIN SCLK MODE
GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO1
2008,
WM8959
WM8959 CONFIGURATION
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ORDERING INFORMATION
ORDER CODE WM8959ECS/RV Note: Reel quantity 3500 TEMPERATURE RANGE -40°C +85°C PACKAGE 42-ball WCSP (Pb-free, Tape reel) MOISTURE SENSITIVITY LEVEL MSL3 PEAK SOLDERING TEMPERATURE 260°C
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WM8959
NAME MICBIAS LIN1 LIN2 LIN3 GPI7 LIN4 RIN1 RIN2 RIN3 GPI8 RIN4 DCVDD DGND DBVDD AVDD AGND HPVDD HPGND SPKVDD SPKGND MCLK BCLK DACLRC DACDAT GPIO1 MODE ADDR SCLK SDIN SPKP SPKN LOUT ROUT OUT3 OUT4 VMID GPIO3 BCLK2 TYPE Analogue Output Analogue Input Analogue Input Analogue Input Digital Input Analogue Input Microphone bias Left channel single-ended input Left channel negative differential input Left channel line input Left channel positive differential input Left channel line input Left channel negative differential input Accessory button detect input Left channel line input Left channel positive differential input Mono differential negative input voice Right channel single-ended input Right channel negative differential input Right channel line input Right channel positive differential input Right channel line input Right channel negative differential input Accessory button detect input Left channel line input Left channel positive differential input Mono differential positive input voice Digital core supply Digital ground (Return path both DCVDD DBVDD) Digital buffer (I/O) supply Analogue supply Analogue ground (Return path AVDD) Headphone supply Headphone ground (Return path HPVDD) Supply speaker driver Ground speaker driver (Return path from SPKVDD) Master clock Audio interface clock Audio interface left right clock digital audio data GPIO1 Selects 2-wire -wire control -wire chip select 2-wire address select Control interface clock input Control interface data input 2-wire acknowledge output Speaker positive output Speaker negative output Left headphone output Right headphone output Inverted left headphone output Mono inverted output Inverted right headphone output Mono non-inverted output Negative left line output Positive right line output Positive left line output Negative right line output Positive left line output Positive right line output Midrail voltage decoupling capacitor Alternative BCLK GPIO
Analogue Input Analogue Input Analogue Input Digital Input Analogue Input
Supply Supply Supply Supply Supply Supply Supply Supply Supply Digital Input Digital Input Output Digital Input Output Digital Input Digital Input Output Digital Input Digital Input Digital Input Digital Input Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Digital Input Output
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WM8959
NAME GPIO4 DACLRC2 GPIO5 DACDAT2 TYPE Digital Input Output Digital Input Output DESCRIPTION Alternative DACLRC GPIO Alternative DACDAT GPIO Connection
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WM8959
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Supply voltages (excluding SPKVDD) SPKVDD Voltage range digital inputs Voltage range analogue inputs Operating temperature range, Junction temperature, TJMAX Storage temperature after soldering -0.3V -0.3V DGND -0.3V AGND -0.3V +4.5V DBVDD +0.3V AVDD +0.3V
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Speaker supply range Ground Notes: Analogue, digital speaker grounds must always within 0.3V each other. digital analogue supplies completely independent from each other (i.e. internally connected). DCVDD must less than equal AVDD. DCVDD must less than equal DBVDD. AVDD must less than equal SPKVDD. SPKVDD must high enough support peak output voltage when using DCGAIN ACGAIN functions, avoid output waveform clipping. Peak output voltage AVDD*(DCGAIN+ACGAIN)/2. HPVDD must equal AVDD SYMBOL DCVDD DBVDD AVDD, HPVDD SPKVDD DGND, AGND, HPGND, SPKGND 1.71 1.71 UNIT
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WM8959 THERMAL PERFORMANCE
Pre-Production
Thermal analysis should performed intended application prevent WM8959 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably physical properties mechanical enclosure, location device relation surrounding components number layers. Connecting balls through thermal vias into large ground plane will heat extraction. Three main heat transfer paths exist surrounding illustrated below Figure Package (radiation). Package bottom (radiation). Package balls (conduction).
Figure Heat Transfer Paths
temperature rise given power dissipated device. thermal resistance from junction ambient temperature therefore measure heat transfer from surrounding air. determined with reference JEDEC standard JESD51-9.
junction temperature given +TR, where ambient temperature.
PARAMETER Operating temperature range Operating junction temperature Thermal Resistance
SYMBOL
UNIT °C/W
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WM8959
SPEAKER POWER DE-RATING CURVE
speaker driver been designed drive maximum into with supply. However, thermal restrictions defined W-CSP package limit amount power that safely dissipated device without exceeding maximum operating junction temperature. Power dissipated device correlates directly with speaker efficiency, hence there separate de-rating curves class class operation. Under circumstances should recommended maximum powers exceeded.
CLASS DE-RATING CURVES
de-rating curves shown Figure based full scale sinusoidal input.
SPKVDD 3.6V SPKVDD 3.3V SPKVDD 5.5V SPKVDD SPKVDD 4.2V
SPKVDD SPKVDD 2.7V
Figure Class Speaker Power De-Rating Curve
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WM8959
CLASS DE-RATING CURVE
de-rating curves shown Figure based full scale sinusoidal input
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SPKVDD 3.6V SPKVDD 3.3V SPKVDD 5.5V SPKVDD SPKVDD 4.2V
SPKVDD SPKVDD 2.7V
Figure Class Speaker Power De-Rating Curve
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WM8959
ELECTRICAL CHARACTERISTICS
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Maximum Full-Scale Input Signal Level Note This changes proportion AVDD (AVDD/3.3). Note When mixing input outputs line inputs total signal must exceed 1Vrms (0dBV). Note 1.0Vrms differential signal equates 0.5Vrms/-6dBV input. Maximum Full-Scale Line Input Signal Level Note This changes proportion AVDD (AVDD/3.3). Note When mixing line inputs, input outputs outputs total signal must exceed 1Vrms (0dBV). Note 1.0Vrms differential signal equates 0.5Vrms/-6dBV input. Line input LIN2 RIN2 SPKMIX Vrms TEST CONDITIONS Single-ended input LIN1, LIN3, RIN1 RIN3, output INMIXL INMIXR Differential input LIN1/LIN2, LIN3/LIN4, RIN1/RIN2 RIN3/RIN4, output INMIXL INMIXR Differential input single-ended inputs LIN1/LIN3 RIN1/RIN3, output DIFFINL DIFFINR UNIT Vrms
Analogue Input Maximum Signal Levels (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4)
Vrms
Vrms
Line input LIN2, LIN4, RIN2 RIN4 INMIXL INMIXR
Vrms
Line input LIN3 RIN3 LOMIX ROMIX
Vrms
Differential mono line input RXP/RXN RXVOICE
Vrms
Differential mono line input RXP/RXN differential output OUT3/OUT4
Vrms
2008,
WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input Resistance Note: this will seen parallel with resistance other enabled input paths from same TEST CONDITIONS LIN1, LIN3, RIN1 RIN3 (PGA Gain -16.5dB) LIN1, LIN3, RIN1 RIN3 (PGA Gain 0dB) LIN1, LIN3, RIN1 RIN3 (PGA Gain +30dB) LIN2, LIN4, RIN2 RIN4 (Constant gains)
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UNIT
Analogue Input Impedances (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4)
Line Input Resistance Note: this will seen parallel with resistance other enabled input paths from same
LIN2 RIN2 INMIXL INMIXR (-12dB) LIN2 RIN2 INMIXL INMIXR (0dB) LIN2 RIN2 INMIXL INMIXR (+6dB) LIN2 RIN2 SPKMIX (SPKATTN 0dB) LIN2 RIN2 SPKMIX (SPKATTN -12dB) LIN3 RIN3 LOMIX ROMIX (0dB) LIN3 RIN3 LOMIX ROMIX (-21dB) RXVOICE AINLMUX AINRMUX (Gain +6dB) RXVOICE AINLMUX AINRMUX (Gain 0dB) RXVOICE AINLMUX AINRMUX (Gain -12dB) RXVOICE AINLMUX AINRMUX (Gain +6dB) RXVOICE AINLMUX AINRMUX (Gain 0dB) RXVOICE AINLMUX AINRMUX (Gain -12dB) LIN4 OUT3 RIN4 OUT4 (Gain -6dB) LIN4 OUT3 RIN4 OUT4 (Gain 0dB)
Input Capacitance
analogue input pins
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WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Common Mode Rejection Ratio (1kHz input) Guaranteed monotonic Inputs disconnected Single differential mode, gain +30dB Single differential mode, gain Single differential mode, gain -16.5dB Differential input DIFFINL DIFFINR LIN1/LIN3 RIN1/RIN3, gain Received Voice (RXP-RXN) Differential Single-Ended Converter RXVOICE Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Fixed Gain Mute Attenuation Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation Guaranteed monotonic LOUT ROUT SPKPGA, LOPGA ROPGA Output Programmable Gain Amplifiers (PGAs) OUT3, OUT4, Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation OUT3 OUT4 (also applies RON) Speaker Attenuation (SPKATTN) Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE Outputs INMIXL INMIXR Outputs INMIXL INMIXR Outputs INMIXL INMIXR Line Inputs Record path INMIXL INMIXR Line Inputs Record path INMIXL INMIXR Line Inputs Record path INMIXL INMIXR TEST CONDITIONS -16.5 UNIT
Input Programmable Gain Amplifiers (PGAs) LIN12, LIN34, RIN12 RIN34
Output Differential Single Ended Converters DIFFINL DIFFINR
Input Mixers INMIXL INMIXR
Output Programmable Gain Amplifiers (PGAs) SPKPGA, LOPGA, ROPGA, LOUT ROUT
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WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated.
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Output Path (Line Outputs 50pF Load, Headphone Outputs Load, Speaker Output Load) (A-weighted) THD+N Crosstalk (L/R) AVDD PSRR (217Hz) (A-weighted) THD+N (A-weighted) THD+N Crosstalk (L/R) AVDD PSRR (217Hz) Offset Load (A-weighted) THD+N Minimum Line Resistance Maximum Line Capacitance (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) LOUT, ROUT, RL=16, AVDD=HPVDD= 2.7V
DACL DACR
singleended line out, 0dBFS input, AVDD 3.3V
-100
singleended line out, 0dBFS input, AVDD 2.7V differential line out, 0dBFS input, AVDD 3.3V
-100
differential line out, 0dBFS input, AVDD 2.7V LOP, LON, ROP, LOP, LON, ROP, LOUT ROUT, RL=32, AVDD=HPVDD= 3.3V
AC-Coupled Headphone Outputs -100
LOUT ROUT, RL=32, AVDD=HPVDD= 2.7V LOUT ROUT, RL=16, AVDD=HPVDD= 3.3V
AC-Coupled Headphone Outputs
LOUT ROUT
-100
LOMIX ROMIX
RLOAD 16Ohm
2008,
Pre-Production Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Offset Load (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Minimum Headphone Resistance SPKVDD Leakage Current (A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=1.0W) THD+N (PO=1.0W) SPKVDD PSRR(217Hz) (A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=1.0W) THD+N (PO=1.0W) SPKVDD PSRR(217Hz) Offset Load LOUT, ROUT Capless (OUT3 pseudo GND), RL=16, AVDD=HPVDD= 2.7V LOUT, ROUT, OUT3, OUT4 SPKVDD=5.0V, Speaker Output (Direct) AVDD=3.3V, SPKVDD=5V, class controlled using volume, ACGAIN=DCGA IN=1.52 Speaker Output (Direct) AVDD=3.3V, SPKVDD=5V, class controlled using volume LOUT/OUT3 ROUT/OUT4, RL=16, AVDD=HPVDD= 2.7V LOUT ROUT Capless (OUT3 pseudo GND), RL=16, AVDD=HPVDD= 3.3V LOUT/OUT3 ROUT/OUT4, RL=16, AVDD=HPVDD= 3.3V Fully Differential Headphone Outputs -100 Capless Headphone Outputs
WM8959
2008,
WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated.
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Bypass Path Performance (Line Outputs 50pF load, Headphone Outputs load, Speaker Output load) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Offset Load (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=1.0W) THD+N (PO=1.0W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) (A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=1.0W) THD+N (PO=1.0W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) Offset Load Line Input SPKMIX, AVDD=3.3V, SPKVDD=5V, Class Mode RXVOICE LOMIX ROMIX Headphone Outputs, AVDD=HPVDD= 2.7V Line Input SPKMIX, AVDD=3.3V, SPKVDD=5V, ACGAIN= DCGAIN=1.52, Class Mode Differential Input RXP/RXN Differential Output OUT3/OUT4, AVDD=HPVDD= 2.7V RXVOICE LOMIX ROMIX Headphone Outputs, AVDD=HPVDD= 3.3V Differential Input RXP/RXN Differential Output OUT3/OUT4, AVDD=HPVDD= 3.3V
2008,
Pre-Production Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. (A-weighted) (0dB output) THD+N (0dB output) AVDD PSRR (217Hz) Offset Load (A-weighted) (0dB output) THD+N (0dB output) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Line Input Headphones LOMIX ROMIX, RL=16, AVDD=HPVDD= 2.7V Input LOMIX ROMIX LOUT ROUT, RL=16, AVDD=HPVDD= 2.7V Line Input Headphones LOMIX ROMIX, RL=16, AVDD=HPVDD= 3.3V Input Differential Line Out, AVDD=2.7V Input LOMIX ROMIX LOUT ROUT, RL=16, AVDD=HPVDD= 3.3V Input Differential Line Out, AVDD=3.3V
WM8959
2008,
WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD +25oC, 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Multi-Path Channel Separation Headset Voice Call: DAC/Headset Voice Separation 1kHz 0dBFS playback LOUT ROUT; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output Headset Voice Call: DAC/Speaker Voice Separation 1kHz 0dBFS playback speaker, output; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output Speaker Voice Call: Voice Voice Separation 1kHz Full scale differential input RXP/RXN, output OUT3/OUT4; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output
Pre-Production
TEST CONDITIONS
UNIT
Headset Voice Call: Voice Voice Separation
LIN1 RIN1
LOAD
+12dB
LIN12 RIN12 (Single-ended differential mode)
1kHz full scale differential input RXP/RXN RXVOICE LOMIX ROMIX, output LOUT ROUT; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output
LIN2 RIN2
LOPMIX ROPMIX
Quiescent input
LOMIX
LOUT
Full scale input
RXVOICE
ROMIX
ROUT
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WM8959
Test Conditions DCVDD 1.8V, DBVDD 3.3V, AVDD HPVDD 3.3V, SPKVDD 1kHz signal, 48kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Reference Levels VMID Midrail Reference Voltage Bias Voltage load current M1BSEL=0 M2BSEL=0 load current M1BSEL=1 M2BSEL=1 Bias Current Source Output Noise Density AVDD PSRR (217Hz) 1kHz 20kHz 100mV pk-pk @217Hz AVDD AVDD/2 nV/Hz Microphone Bias TEST CONDITIONS UNIT
Digital Input Output Input HIGH Level Input Level
Note that digital input pins should left unconnected floating. Internal pull-up/pull-down resistors enabled GPIO1, GPIO3, GPIO4 GPIO5 required. GPIO Clock output duty cycle (Integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0000 SYSCLK=MCLK; OPCLKDIV=1000 SYSCLK=PLL output; OPCLKDIV=0000 SYSCLK=PLL output; OPCLKDIV=1000 Clock output duty cycle (Non-integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0100 SYSCLK=PLL output; OPCLKDIV=0100 Interrupt response time accessory button detect Input de-bounced Input de-bounced TOCLKSEL=1 Input de-bounced
Output HIGH Level Output Level Input capacitance Input leakage Input Frequency Lock time
IOL=1mA IOH=-1mA
-0.9 fSYSCLK fSYSCLK fSYSCLK fSYSCLK
PRESCALE PRESCALE
2008,
WM8959 TERMINOLOGY
Pre-Production
Signal-to-Noise Ratio (dB) measure difference level between maximum theoretical full scale output signal output with input signal applied. Total Harmonic Distortion (dB) level value harmonic distortion products relative amplitude measured output signal. Total Harmonic Distortion plus Noise (dB) THD+N level value harmonic distortion products plus noise specified bandwidth relative amplitude measured output signal. Crosstalk (L/R) (dB) left-to-right right-to-left channel crosstalk measured signal level idle channel test signal frequency relative signal level output active channel. active channel configured supplied with appropriate input signal drive full scale output, with signal measured output associated idle channel. example, measured signal level output idle right channel (RIN3 ROUT ROMIX) with full scale signal level output active left channel (LIN1 LOUT LOMIX). Multi-Path Channel Separation (dB) measured signal level idle path test signal frequency relative signal level output active path. active path configured supplied with appropriate input signal drive full scale output, with signal measured output specified idle path. performance measurements carried with 20kHz pass filter, where noted A-weighted filter. Failure such filter will result higher lower readings than found Electrical Characteristics. pass filter removes band noise; although audible affect dynamic specification values. Mute Attenuation This measure difference level between full scale output signal output with mute applied.
2008,
Pre-Production
WM8959
TYPICAL POWER CONSUMPTION
Control Register Mode (default state power-up) VSEL Other settings AVDD HPVDD SPKVDD DBVDD DCVDD IAVDD (mA) 0.028 0.029 0.030 0.031 0.008 0.008 0.009 0.009 0.087 0.096 0.106 0.117 2.950 3.315 3.684 4.055 2.951 3.315 3.683 4.055 2.950 3.315 3.684 4.056 2.950 3.315 3.683 4.055 2.952 3.316 3.683 4.055 2.951 3.317 3.684 4.055 2.951 3.315 3.684 4.056 2.950 3.315 3.683 4.055 2.950 3.315 3.683 4.055 2.955 3.319 3.686 4.057 3.934 4.184 4.672 5.166 3.621 4.080 4.548 5.021 3.087 3.470 3.856 4.246 0.442 0.499 0.556 0.613 2.307 2.374 2.660 2.953 IHPVDD ISPKVDD IDBVDD (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.705 0.558 0.640 0.726 1.430 1.367 1.544 1.742 0.828 0.743 0.835 0.937 2.563 2.476 2.508 2.556 15.767 15.789 15.675 15.836 0.699 0.550 0.629 0.711 1.019 0.915 1.045 1.180 0.748 0.624 0.704 0.789 1.950 1.868 1.905 1.950 11.421 11.362 11.349 11.406 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.697 0.544 0.621 0.702 0.796 0.615 0.703 0.794 (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 3.070 3.652 5.154 7.223 2.823 3.307 4.061 5.057 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.004 0.008 0.014 0.017 0.003 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.014 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.004 0.007 0.013 0.016 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 IDCVDD Total Power (mA) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.459 0.694 1.025 1.162 2.147 3.180 4.544 5.092 2.298 3.380 4.817 5.404 2.263 3.362 4.762 5.344 2.251 3.323 4.736 5.304 2.256 3.343 4.762 5.329 2.147 3.179 4.543 5.089 2.302 3.359 4.806 5.367 2.265 3.337 4.786 5.359 2.253 3.327 4.741 5.312 2.267 3.351 4.777 5.342 2.144 3.179 4.541 5.089 2.138 3.167 4.530 5.073 2.125 3.146 4.496 5.042 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 (mW) 0.074 0.086 0.099 0.114 0.019 0.024 0.028 0.035 1.067 2.043 3.779 4.667 13.739 19.586 29.307 35.600 15.971 22.513 33.189 40.381 14.279 20.596 30.671 37.270 18.943 25.698 36.103 42.951 54.608 65.690 79.640 90.850 13.725 19.565 29.268 35.536 14.868 21.105 31.509 38.228 14.067 20.177 30.314 36.789 17.291 23.883 34.129 40.799 42.901 52.438 65.423 74.956 14.487 20.517 30.446 36.976 23.763 33.322 51.648 72.511 21.482 30.198 44.662 58.780 3.074 3.128 3.884 4.735 8.377 8.966 11.097 13.490
(thermal sensor disabled) SLEEP (VMID enabled, thermal sensor anabled) Playback Coupled Headphones (DAC L/ROUT) 16ohm load Playback Coupled Headphones (DAC L/ROUT) -20dBV Pink Noise into 16ohm load Playback Coupled Headphones (DAC L/ROUT) -30dBV Pink Noise into 16ohm load Playback Coupled Headphones (DAC L/ROUT) 0.1mW/channel into 16ohm load Playback Coupled Headphones (DAC L/ROUT) 5mW/channel into 16ohm load Playback Coupled Headphones (DAC L/ROUT) 32ohm load Playback Coupled Headphones (DAC L/ROUT) -20dBV Pink Noise into 32ohm load Playback Coupled Headphones (DAC L/ROUT) -30dBV Pink Noise into 32ohm load Playback Coupled Headphones (DAC L/ROUT) 0.1mW/channel into 32ohm load Playback Coupled Headphones (DAC L/ROUT) 5mW/channel into 32ohm load Playback Line-Out (DAC ROP/RON) Playback Speaker Class (DAC SPK) 8ohm load Playback Speaker Class (DAC SPK) 8ohm load Radio Coupled Headphones (L/RIN3 L/ROUT bypass LROMIX) 16ohm load Analogue Voice Call Handset Speaker (MIC LIN12 LOP/LON) (RXP/RXN OUT3/4 RXVIOCE AINLMUX)
Clocks
Clocks
With Clocks
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
Notes: Power load included. figures quoted figures quoted quiescent current unless otherwise stated.
2008,
WM8959 SPEAKER DRIVER PERFORMANCE
Pre-Production
Typical speaker driver THD+N performance shown below both Class Class modes. Curves shown four typical SPKVDD supply voltage gain combinations. Load 10µH, Frequency 1kHz, +1dB gain active path.
SPEAKER CLASS INTO 10µH
Speaker Class (8+10µH)
THD+N Ratio Output Power
SPEAKER CLASS INTO 10µH
Speaker Class (8+10µH)
THD+N Ratio Output Power
THD+N Ratio
THD+N Ratio
0.01
0.01
SPKVDD=5.0V, SPKVDD=4.2V, SPKVDD=3.6V, SPKVDD=3.3V,
AC=DC=1.52x AC=DC=1.27x AC=DC=1.00x AC=DC=1.00x
SPKVDD=5.0V, SPKVDD=4.2V, SPKVDD=3.6V, SPKVDD=3.3V,
AC=DC=1.52x AC=DC=1.27x AC=DC=1.00x AC=DC=1.00x
0.001 0.25 0.75 1.25
0.001 0.25 0.75 1.25
Output Power
Output Power
HEADPHONE DRIVER PERFORMANCE
Typical THD+N performance Headphone Drivers shown below coupled LOUT/ROUT). Curves shown four HPVDD/AVDD supply voltages. Load Frequency 1kHz, +1dB gain active path.
COUPLED HEADPHONE INTO
Coupled Headphone (16ohm)
THD+N Ratio Output Power
COUPLED HEADPHONE INTO
Coupled Headphone (32ohm)
THD+N Ratio Output Power
THD+N Ratio
THD+N Ratio
HPVDD=AVDD=3.6V HPVDD=AVDD=3.3V HPVDD=AVDD=3.0V HPVDD=AVDD=2.7V
HPVDD=AVDD=3.6V HPVDD=AVDD=3.3V HPVDD=AVDD=3.0V HPVDD=AVDD=2.7V
0.01
0.01
Output Power (mW)
Output Power (mW)
2008,
Pre-Production
WM8959
PSRR PERFORMANCE
SPKVDD LIN2 SPEAKER
PSRR SPKVDD
PSRR (dB) Frequency (kHz) LIN2-SPK (Class SPKVDD LIN2-SPK (Class SPKVDD LIN2 class AB/D
AVDD LIN2 SPEAKER
PSRR AVDD
PSRR (dB) Frequency (kHz) LIN2-SPK (Class SPKVDD) 3.3V AVDD LIN2-SPK (Class SPKVDD) 3.3V AVDD LIN2 class AB/D
SPKVDD SPEAKER
PSRR SPKVDD
PSRR (dB)
PSRR (dB)
AVDD SPEAKER
PSRR AVDD
class AB/D
class AB/D
Frequency (kHz) DACL-SPK (Class SPKVDD DACL-SPK (Class SPKVDD
DACL-SPK (Class SPKVDD) 3.3V AVDD DACL-SPK (Class SPKVDD) 3.3V AVDD Frequency (kHz)
HPVDD HEADPHONE
PSRR HPVDD
PSRR (dB) Frequency (kHz) DAC-OMIX-LOUT/ROUT 3.3V HPVDD DAC-OMIX-OPGA-Differential 3.3V HPVDD Headphone
AVDD HEADPHONE
PSRR AVDD
PSRR (dB) Frequency (kHz) DAC-OMIX-LOUT/ROUT 3.3V AVDD DAC-OMIX-OPGA-Differential 3.3V AVDD Headphone
DCVDD HEADPHONE
PSRR DCVDD
PSRR (dB) Frequency (kHz) DAC-OMIX-LOUT/ROUT 3.3V DCVDD DAC-OMIX-LOUT/ROUT 2.0V DCVDD
PSRR (dB)
AVDD MICBIAS
PSRR AVDD MICBIAS
Frequency (kHz) MICBIAS MBSEL MICBIAS MBSEL
Headphone
2008,
WM8959
HPVDD BYPASS
PSRR HPVDD
IN1PGA-OMIX-LOUT/ROUT 3.3V HPVDD Frequency (kHz) Bypass
Pre-Production AVDD BYPASS
PSRR AVDD
PSRR (dB) Frequency (kHz) IN1PGA-OMIX-LOUT/ROUT 3.3V AVDD IN1PGA-LINEDIFF 3.3V AVDD Bypass
PSRR (dB)
HPVDD BYPASS
PSRR HPVDD
Frequency (kHz) IN3-OMIX-LOUT/ROUT 3.3V HPVDD IN3-OMIX-OPGA-OUT3/OUT4 3.3V HPVDD IN3-OMIX-OPGA-Differential 3.3V HPVDD Bypass
AVDD BYPASS
PSRR AVDD
PSRR (dB) Frequency (kHz) IN3-OMIX-LOUT/ROUT 3.3V AVDD IN3-OMIX-OPGA-OUT3/OUT4 3.3V AVDD IN3-OMIX-OPGA-Differential 3.3V AVDD Bypass
PSRR (dB)
HPVDD BYPASS
PSRR HPVDD
PSRR (dB) Frequency (kHz) RxVOICE-OMIX-LOUT 3.3V HPVDD IN4-OUT3/OUT4 (16Ohm BTL) 3.3V HPVDD Bypass
AVDD BYPASS
PSRR AVDD
PSRR (dB) Frequency (kHz) RxVOICE-OMIX-LOUT 3.3V AVDD IN4-OUT3/OUT4 (16Ohm BTL) 3.3V AVDD Bypass
Note: figures based 100mVp-p injected supply relevant test frequency.
2008,
LONMIX
LLOPGALON LROPGALON LON_ENA Line
MAIN REGISTER REFERENCE
REGISTER ALSO REFERENCED ELSEWHERE DIAGRAM
OUTPUT MIXERS
LL12LOP LR12LOP LOP_ENA Line
LOPLON
Pre-Production
READBACK AVAILABLE
INPUT MIXERS
LLOPGALOP
INPUT PGAs
LOPMIX
LOATTN
LMN3
LIN3/GPI7
DACL LRBLOVOL[2:0] LLBLOVOL[2:0] LI2SPK LOPGASPK LDSPK RDSPK
(RDRO RDSPK must enabled same time)
LIN34VOL[4:0], LI34MUTE LIN34_ENA
LMP4 LR12LOVOL[2:0]
AUDIO SIGNAL PATHS
LR4BVOL[2:0] DACL_VOL [7:0]
(LDLO LDSPK must enabled same time)
RXVOICE AINLMUX
MONO DAC_MONO ROPGASPK RI2SPK RB2SPK ROPGAVOL AINLMODE LOMIX_ENA
DIFFINL
AINL_ENA
RL4BVOL[2:0]
RR4BVOL[2:0] AINRMODE ROMIX_ENA AINR_ENA RRBROVOL[2:0] RLBROVOL[2:0] RR12ROVOL[2:0] RL12ROVOL[2:0] RLI3ROVOL [2:0] RRI3ROVOL[2:0] RL12RO RLI3RO RRI3RO RR12RO RLBRO RRBRO RPGAO4 RI4O4 DACR DACR_VOL [7:0] R34MNBST R12MNBST R12MNB R34MNB AINR_ENA
RXVOICE AINRMUX ROPGA
RDRO
AINR_ENA
DIFFINR ROMIX ROPGA_ENA [6:0]
RMN3
RIN34VOL[4:0], RI34MUTE RIN34_ENA
RMN1
RIN12VOL[4:0], RI12MUTE RIN12_ENA
MICBIAS Current Detect DACL_SRC DACR_SRC
MICBIAS_ENA
MICBIAS DCVDD
RIN1 RIN2 INMIXR
RMP2
RIN3/GPI8 RIN4/RXP
RMP4
RIN34
RI2BVOL[2:0] (000=MUTE)
RIN12
VREF
VREF
MBSEL
250k
250k
LL4BVOL[2:0]
LIN4/RXN INMIXL
AINL_ENA
LIN1 LIN2
LRI3LO OUT3_ENA LI4O3 LPGAO3 OUT3ATTN LOUT_ENA AINL_ENA LRBLO LLBLO LL12LO
LMP2
LI3LO
LMN1
LIN12VOL[4:0], LI12MUTE LIN12_ENA
OUT3MIX
LIN12
LI3LOVOL[2:0] LRI3LOVOL[2:0] LL12LOVOL[2:0]
DIGITAL CORE
LR12LO LI2BVOL[2:0] (000=MUTE) L12MNB L12MNBST L34MNB L34MNBST
OUT3
LOPGA SPKMIX
LB2SPK
LDLO
LOUT
LOUTVOL[6:0]
LIN34 LOMIX
LOPGA_ENA LOPGAVOL [6:0]
AINL_ENA
SPKPGA_ENA SPK_ENA SPK_ENA
SPKPGA
DCGAIN ACGAIN [2:0] [2:0] SPKVOL [6:0]
SPKN SPKP
AINR_ENA
SPKATTN [1:0] ROUT_ENA OUT4_ENA ROUTVOL[6:0]
ROUT
DAC_MUTE, DAC_MUTEMODE, DAC_MUTERATE, DAC_SB_FILT, DEEMP[1:0]
OUT4 OUT4MIX
OUT4ATTN
ROPMIX
RROPGAROP DAC_BOOST [1:0] DAC_BOOST +6dB +12dB +18dB RL12ROP RR12ROP ROATTN RON_ENA ROPRON RLOPGARON DACL_DATINV DACR_DATINV RROPGARON ROP_ENA
Line
Line
RONMIX
AVDD DIGITAL AUDIO INTERFACE
A-law u-law support Support
GPIO
Alternative Interface Button Control Accessory Detect Clock Output
VMIDSEL [1:0]
SYSCLK
CONTROL INTERFACE
VMID
AGND BCLK DGND DCVDD DBVDD HPVDD HPGND DACLRC DACDAT SPKVDD SPKGND
AVDD
MCLK
CSB/ADDR SDIN SCLK MODE
GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO1
2008,
WM8959
WM8959 SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
MCLKY MCLKH MCLKL
Pre-Production
Figure System Clock Timing Requirements
Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, +25oC PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle TMCLKY TMCLKH/TMCLKL 33.33 60:40 40:60 SYMBOL CONDITIONS UNIT
2008,
Pre-Production
WM8959
AUDIO INTERFACE TIMING MASTER MODE
Figure Digital Audio Data Timing Master Mode (see Control Interface)
Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 Slave Mode, fs=48kHz, MCLK=256fs, data, unless otherwise stated. PARAMETER Audio Data Input Timing Information DACLRC DACLRC2) propagation delay from BCLK BCLK2) falling edge DACDAT DACDAT2) setup time BCLK rising edge DACDAT DACDAT2) hold time from BCLK rising edge tDST tDHT SYMBOL UNIT
2008,
WM8959
AUDIO INTERFACE TIMING SLAVE MODE
Pre-Production
Figure Digital Audio Data Timing Slave Mode
Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK BCLK2) cycle time BCLK BCLK2) pulse width high BCLK BCLK2) pulse width DACLRC DACLRC2) set-up time BCLK BCLK2) rising edge DACLRC DACLRC2) hold time from BCLK BCLK2) rising edge DACDAT DACDAT2) hold time from BCLK BCLK2) rising edge DACDAT DACDAT2) set-up time BCLK BCLK2) rising edge Note: BCLK BCLK2) period should always greater than equal MCLK period. tBCY tBCH tBCL tLRSU tLRH SYMBOL UNIT
2008,
Pre-Production
WM8959
CONTROL INTERFACE TIMING 2-WIRE MODE
2-wire mode selected connecting MODE low.
SDIN SCLK
Figure Control Interface Timing 2-Wire Serial Control Mode
Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width spikes that will suppressed SYMBOL UNIT
2008,
WM8959
CONTROL INTERFACE TIMING 3-WIRE MODE
3-wire mode selected connecting MODE high.
Pre-Production
Figure Control Interface Timing 3-Wire Serial Control Mode (Write Cycle)
SCLK
SDOUT
Figure Control Interface Timing 3-Wire Serial Control Mode (Read Cycle)
Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information falling edge SCLK rising edge SCLK falling edge rising edge SCLK pulse cycle time SCLK pulse width SCLK pulse width high SDIN SCLK set-up time SDIN SCLK hold time Pulse width spikes that will suppressed SCLK falling edge SDOUT transition tCSU tCHO tSCY tSCL tSCH tDSU tDHO SYMBOL UNIT
2008,
Pre-Production
WM8959
CONTROL INTERFACE TIMING 4-WIRE MODE
4-wire mode supports readback SDOUT which available GPIO function.
SCLK
SDIN
Figure Control Interface Timing 4-Wire Serial Control Mode (Write Cycle)
SCLK
SDOUT
Figure Control Interface Timing 4-Wire Serial Control Mode (Read Cycle)
Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, =+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge falling edge SCLK falling edge rising edge SCLK pulse cycle time SCLK pulse width SCLK pulse width high SDIN SCLK set-up time SDIN SCLK hold time SDOUT propagation delay from SCLK rising edge Pulse width spikes that will suppressed SCLK falling edge SDOUT transition tCSU tCHO tSCY tSCL tSCH tDSU tDHO SYMBOL UNIT
2008,
WM8959 INTERNAL POWER RESET CIRCUIT
Pre-Production
Figure Internal Power Reset Circuit Schematic
WM8959 includes internal Power-On-Reset Circuit, shown Figure which used reset digital logic into default state after power circuit powered from AVDD monitors DCVDD. asserts PORB AVDD DCVDD below minimum threshold.
Figure Typical Power Sequence where AVDD Powered before DCVDD
Figure shows typical power-up sequence where AVDD comes first. When AVDD goes above minimum threshold, Vpora, there enough voltage circuit guarantee PORB asserted chip held reset. this condition, writes control interface ignored. AVDD full supply level. Next DCVDD rises Vpord_on PORB released high registers their default state writes control interface take place. power down, where AVDD falls first, PORB asserted whenever AVDD drops below minimum threshold Vpora_off.
2008,
Pre-Production
WM8959
Figure Typical Power Sequence where DCVDD powered before AVDD
Figure shows typical power-up sequence where DCVDD comes first. First assumed that DCVDD already specified operating voltage. When AVDD goes above minimum threshold, Vpora, there enough voltage circuit guarantee PORB asserted chip held reset. this condition, writes control interface ignored. When AVDD rises Vpora_on, PORB released high registers their default state writes control interface take place. power down, where DCVDD falls first, PORB asserted whenever DCVDD drops below minimum threshold Vpord_off. SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off 1.52 0.92 UNIT
Table Typical Operation (typical values, tested)
Notes: AVDD DCVDD suffer brown-out (i.e. drop below minimum recommended operating level below Vpora_off Vpord_off) then chip will reset will resume normal operation when voltage back recommended level again. chip will enter reset power down when AVDD DCVDD falls below Vpora_off Vpord_off. This important supply turned frequently power management system. minimum tpor period maintained even DCVDD AVDD have zero rise time. This specification guaranteed design rather than test.
2008,
WM8959 DEVICE INTRODUCTION
Pre-Production
WM8959 power, high quality audio designed interface with wide range processors analogue components. high level mixed-signal integration very small 3.226 3.44mm footprint makes ideal portable applications such mobile phones. Eight highly flexible analogue inputs allow interfacing four microphone inputs plus multiple stereo mono line inputs (single-ended differential). Connections external voice CODEC, radio, melody line input, handset headset fully supported. Signal routing output mixers within been designed maximum flexibility support wide variety usage modes. analogue output drivers integrated, including high power, high quality speaker driver, capable providing class mode class mode into BTL. Four headphone drivers provided, supporting speakers stereo headsets. Fully differential headphone drive supported excellent crosstalk performance removing need large expensive headphone capacitors. Four line outputs available voice output voice CODEC, interfacing additional speaker driver single-ended fully differential line output. outputs have integrated click suppression. speaker supply been designed with leakage high PSRR, support direct connection Lithium battery. addition speaker PGA, gain settings allow output signal level maximised many commonly-used SPKVDD/AVDD combinations. Internal signal routing amplifier configurations have been optimised provide lowest possible power consumption number common usage scenarios such voice calls music playback. stereo DACs hi-fi quality using 24-bit, low-order oversampling architecture deliver optimum performance. integrated ultra-low power provides flexible clocking capabilities. soft mute un-mute available pop-free music playback. WM8959 highly flexible digital audio interface, supporting number protocols, including I2S, DSP, MSB-First left/right justified. interface operate master slave modes. operation supported mode. A-law µ-law companding also supported. Time division multiplexing (TDM) available allow multiple devices stream data simultaneously same bus, saving space power. Alternative interface pins provided allow connection additional processor. SYSCLK (system clock) provides clocking DACs, DSP, Class outputs digital audio interface. SYSCLK derived directly from MCLK integrated PLL, providing flexibility support wide range clocking schemes. MCLK frequencies typically used portable systems supported sample rates between 8kHz 48kHz. flexible switching clock class speaker drivers (synchronous with audio clocks best performance) also derived from SYSCLK. allow full software control over features, WM8959 uses standard 2-wire 3/4-wire control interface with readback registers supported. fully compatible ideal partner wide range industry standard microprocessors, controllers DSPs. Unused circuitry disabled software save power, while leakage currents extend standby time portable battery-powered applications. device address selected using CSB/ADDR pin. Versatile GPIO functionality provided, with support four button/accessory detect inputs with interrupt status readback flexible de-bouncing options, clock output, logic logic control additional external circuitry.
2008,
Pre-Production
WM8959
ANALOGUE INPUT PATH
WM8959 eight highly flexible analogue input channels, configurable many combinations following: four pseudo-differential single-ended microphone inputs eight mono line inputs stereo line inputs Mono input from external voice CODEC fully balanced differential inputs These inputs mixed together independently routed different combinations output drivers. WM8959 input signal paths control registers illustrated Figure
Figure Control Registers Input Signal Path
2008,
WM8959
MICROPHONE INPUTS
Pre-Production
four microphones connected WM8959, either single-ended pseudodifferential mode. noise microphone bias fully integrated reduce need external components. single-ended microphone input configuration, microphone signal connected inverting input (LIN1, LIN3, RIN1 RIN3). non-inverting input PGAs should internally connected VMID this configuration. This enabled Input configuration register settings. this configuration, LIN2, LIN4, RIN2 RIN4 free used line input Input Mixer directly Speaker Mixer. pseudo-differential microphone input configuration, non-inverted microphone signal connected non-inverting input (LIN2, LIN4, RIN2 RIN4) inverted noisy ground) signal connected inverting input (LIN1, LIN3, RIN1 RIN3). input that used either microphone configuration should enabled line input path same time. gain input PGAs controlled register settings. Note that input impedance LIN1, LIN3, RIN1 RIN3 changes with input gain setting, described under "Electrical Characteristics". (Note this does apply input paths which bypass input PGA.) input impedance LIN2, LIN4, RIN2 RIN4 does change with input gain. inverting non-inverting inputs therefore matched differential configuration fully differential.
Figure Single-Ended Microphone Input
Figure Differential Microphone Input
LINE INPUTS
eight analogue input pins configured line inputs. Various signal paths exist provide flexibility, high performance power consumption different usage modes. LIN1 RIN1 operate line inputs Input PGAs LIN12 RIN12 provide high gain required small input signals. LIN2 RIN2 operate line inputs directly input mixers speaker output mixer. Direct routing speaker output minimises power consumption reducing number active amplifiers signal path. LIN3 RIN3 operate line inputs Input PGAs line input directly either output mixers LOMIX ROMIX. LIN1+LIN3 RIN1+RIN3 also used fully balanced differential inputs Input PGAs input mixers. (Note that these inputs have matched input impedances.) LIN4/RXN RIN4/RXP operate line inputs directly outputs OUT3 OUT4, providing ultra-low power stereo mono differential signal path (e.g. from external voice CODEC) speaker. LIN4/RXN RIN4/RXP also operate mono differential input directly output mixer stages.
2008,
Pre-Production
WM8959
Figure LIN1 RIN1 Line Inputs
Figure LIN2 RIN2 Line Inputs
Figure LIN3 RIN3 Line Inputs
Figure Fully Balanced Differential Input
power voice path OUT3
OUT3
LIN4/
Voice CODEC
RIN4/ RIN1 RIN2
Figure LIN4 RIN4 Voice Inputs with Direct Power Path Speaker
Figure LIN4 RIN4 Line Inputs
RIN3/ GPI8
LIN3/ GPI7
LIN1 LIN2
LIN12
OUT3
LIN34 SPKMIX
LOUT
Differential output handset speaker
input output mixers
SPKN SPKP
ROUT OUT4
RIN34
OUT4 RIN12
power voice path OUT4
2008,
WM8959
INPUT ENABLE
Pre-Production
Input PGAs enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA RIN34_ENA described Table REGISTER ADDRESS (02h) LABEL DEFAULT
LIN34_ENA (rw) LIN12_ENA (rw) RIN34_ENA (rw) RIN12_ENA (rw)
LIN34 Input Enable disabled enabled LIN12 Input Enable disabled enabled RIN34 Input Enable disabled enabled RIN12 Input Enable disabled enabled
Table Input Enable
enable input PGAs, reference voltage VMID bias current must also enabled. "Power Management" definitions associated controls VMID_MODE VREF_ENA.
2008,
Pre-Production
WM8959
MICROPHONE BIAS CONTROL
MICBIAS output provides noise reference voltage suitable biasing electret type microphones external resistor. Refer Applications Information section recommended external components. MICBIAS voltage enabled disabled using MICBIAS_ENA control voltage selected using MBSEL register detailed Table REGISTER ADDRESS (01h) LABEL MICBIAS_ENA (rw) MBSEL DEFAULT DESCRIPTION Microphone Bias (high impedance output) Microphone Bias Voltage Control AVDD 0.65 AVDD
(3Ah)
Table Microphone Bias Control Note that maximum source current capability MICBIAS 3mA. external biasing resistance must large enough limit MICBIAS current 3mA.
MICROPHONE CURRENT DETECT
MICBIAS current detect function allows detection accessories such headset microphones. When MICBIAS load current exceeds programmable thresholds, (e.g. short circuit current normal operating current), interrupt GPIO output generated. current detection circuit enabled bit; current thresholds selected MCDTHR MCDSCTH register fields described Table "General Purpose Input/Output" full description these fields.
2008,
WM8959
INPUT CONFIGURATION
Pre-Production
Each four Input PGAs configured single-ended pseudo-differential mode. Single-ended microphone operation Input selected connecting input source inverting input. non-inverting input must connected VMID setting appropriate register bits. pseudo-differential microphone operation, inverting non-inverting inputs both connected input source VMID. line input other connection using Input PGA, appropriate input should disconnected from external connected VMID. Register bits LMN1, LMP2, LMN3, LMP4, RMN1, RMP2, RMN3 RMP4 control connection inputs device pins shown Table maximum available attenuation these input paths achieved using these bits disable input path applicable PGA. When enabled analogue inputs General Purpose inputs, input pins biased VREF resistor setting BUFIOEN bit. "Pop Suppression Control" details. REGISTER ADDRESS (28h) LABEL LMP4 DEFAULT DESCRIPTION LIN34 Non-Inverting Input Select LIN4 connected LIN4 connected LIN34 Inverting Input Select LIN3 connected LIN3 connected LIN12 Non-Inverting Input Select LIN2 connected LIN2 connected LIN12 Inverting Input Select LIN1 connected LIN1 connected RIN34 Non-Inverting Input Select RIN4 connected RIN4 connected RIN34 Inverting Input Select RIN3 connected RIN3 connected RIN12 Non-Inverting Input Select RIN2 connected RIN2 connected RIN12 Inverting Input Select RIN1 connected RIN1 connected
LMN3
LMP2
LMN1
RMP4
RMN3
RMP2
RMN1
Table Input Configuration
2008,
Pre-Production
WM8959
INPUT VOLUME CONTROL
Each four Input PGAs independently controlled gain range -16.5dB +30dB 1.5dB steps. gains inverting non-inverting inputs PGAs always equal. Each Input independently muted using mute bits described Table with specified mute attenuation achieved simultaneously disconnecting corresponding inputs described Table prevent "zipper noise", zero-cross function provided, that when enabled, volume updates will take place until zero-crossing detected. event long period without zerocrossings, timeout function available. When this function enabled (using TOCLK_ENA register bit), volume will update after timeout period earlier zero-cross occurred. timeout period TOCLK_RATE. "Clocking Sample Rates" more information these fields. IPVU controls loading input volume data. When IPVU volume data will loaded into respective control register, will actually change gain setting. LIN12, RIN12, LIN34, RIN34 volume settings updated when written IPVU. This makes possible update gain input paths simultaneously. Input Volume Control register fields described Table Table REGISTER ADDRESS (18h) LABEL IPVU[0] DEFAULT DESCRIPTION Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) LIN12 Mute Disable Mute Enable Mute LIN12 Zero Cross Detector Change gain immediately Change gain zero cross only LIN12 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) LIN34 Mute Disable Mute Enable Mute LIN34 Zero Cross Detector Change gain immediately Change gain zero cross only LIN34 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) RIN12 Mute Disable Mute Enable Mute RIN12 Zero Cross Detector Change gain immediately Change gain zero cross only
LI12MUTE
LI12ZC
(19h)
LIN12VOL [4:0] IPVU[1]
01011b (0dB)
LI34MUTE
LI34ZC
(1Ah)
LIN34VOL [4:0] IPVU[2]
01011b (0dB)
RI12MUTE
RI12ZC
2008,
WM8959
REGISTER ADDRESS (1Bh) LABEL RIN12VOL [4:0] IPVU[3] DEFAULT 01011b (0dB)
Pre-Production DESCRIPTION RIN12 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) RIN34 Mute Disable Mute Enable Mute RIN34 Zero Cross Detector Change gain immediately Change gain zero cross only RIN34 Volume (See Table volume range)
RI34MUTE
RI34ZC
RIN34VOL [4:0]
01011b (0dB)
Table Input Volume Control
2008,
Pre-Production
WM8959
LIN12VOL[4:0], LIN34VOL[4:0], RIN12VOL[4:0], RIN34VOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Table Input Volume Range VOLUME (dB) -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 +1.5 +3.0 +4.5 +6.0 +7.5 +9.0 +10.5 +12.0 +13.5 +15.0 +16.5 +18.0 +19.5 +21.0 +22.5 +24.0 +25.5 +27.0 +28.5 +30.0
2008,
WM8959
INPUT MIXER ENABLE
Pre-Production
WM8959 analogue input mixers which allow Input PGAs Line Inputs combined number ways Output Mixers. input mixers INMIXL INMIXR enabled AINL_ENA AINR_ENA register bits, described Table These control bits also enable Input Multiplexers Differential Input drivers, described following section. REGISTER ADDRESS (02h) LABEL AINL_ENA (rw) DEFAULT DESCRIPTION Left Input Path Enable (Enables AINLMUX, INMIXL, DIFFINL RXVOICE input AINLMUX) Input Path disabled Input Path enabled Right Input Path Enable (Enables AINRMUX, INMIXR, DIFFINR RXVOICE input AINRMUX) Input Path disabled Input Path enabled
AINR_ENA (rw)
Table Input Mixer Enable
INPUT MIXER CONFIGURATION
left right channel input multiplexers AINLMUX AINRMUX select three input sources Left Right channels independently. three input sources follows: INMIXL INMIXR output combination Input PGAs line inputs). RXVOICE differential single-ended conversion inputs). DIFFINL DIFFINR output differential single-ended conversion Input PGAs). input source multiplexers controlled register bits AINLMODE AINRMODE described Table REGISTER ADDRESS (27h) LABEL AINLMODE [1:0] DEFAULT DESCRIPTION AINLMUX Input Source INMIXL (Left Input Mixer) RXVOICE (RXP RXN) DIFFINL (LIN12 LIN34 PGA) (Reserved) AINRMUX Input Source INMIXR (Right Input Mixer) RXVOICE (RXP RXN) DIFFINR (RIN12 RIN34 PGA) (Reserved)
AINRMODE [1:0]
Table Input Mixer Configuration
2008,
Pre-Production
WM8959
Input Mixer configuration described each three modes following sections. Note that Left Right multiplexer (mode) settings independently.
Mixer Mode (AINLMODE=00, AINRMODE=00), adjustable gain control available input mixers INMIXL INMIXR available input signals (PGA outputs, line inputs record paths). This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Mixer Mode (INMIXL AINLMUX) Select Mixer Mode Enable input paths required (see Table Table full definitions applicable settings listed here) Right Channel Mixer Mode (INMIXR AINRMUX) Select Mixer Mode Enable input paths required (see Table Table full definitions applicable settings listed here) Table Mixer Mode Register Settings REGISTER SETTINGS AINLMODE L12MNB, L12MNBST LIN12VOL, LIN12MUTE L34MNB, L34MNBST LIN34VOL, LIN34MUTE LI2BVOL AINRMODE R12MNB, R12MNBST RIN12VOL, RIN12MUTE R34MNB, R34MNBST RIN34VOL, RIN34MUTE RI2BVOL
Figure Mixer Mode Signal Paths
2008,
WM8959
Pre-Production Voice Mode (AINLMODE=01, AINRMODE=01), adjustable gain control available RXVOICE output LR4BVOL[2:0] LL4BVOL[2:0] register fields left channel RL4BVOL[2:0] RR4BVOL[2:0] right channel. Both Volume fields desired channel(s) must same value true Differential input characteristics. This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Voice Mode (RXVOICE AINLMUX) REGISTER SETTINGS Select Voice Mode Enable Voice input required Important: These register fields must same value. Table full definitions these fields. Select Voice Mode Enable Voice input required Important: These register fields must same value. Table full definitions these fields. AINLMODE LL4BVOL LR4BVOL
Right Channel Voice Mode (RXVOICE AINRMUX)
AINRMODE RL4BVOL RR4BVOL
Table RxVoice Mode Register Settings
Figure RxVoice Mode Signal Paths
2008,
Pre-Production
WM8959
Differential Mode (AINLMODE=10, AINRMODE=10), additional volume control available input signal path, Input volume control used adjust signal level with other modes. Both PGAs desired channel(s) must enabled, volumes each same value true Differential input characteristics. Output (LIN12 RIN12) Mixer (INMIXL INMIXR) path must also enabled desired channel(s) register L12MNB R12MNB. This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Differential Mode (DIFFINL AINLMUX) REGISTER SETTINGS Select Differential Mode Enable LIN12 input path channel volume required. Important: LIN12 LIN34 volume mute settings must same value. Table full definitions these fields. Select Differential Mode Enable RIN12 input path channel volume required. Important: RIN12 RIN34 volume mute settings must same value. Table full definitions these fields. AINLMODE L12MNB LIN12VOL, LIN12MUTE LIN34VOL, LIN34MUTE
Right Channel Differential Mode (DIFFINR AINRMUX)
AINRMODE R12MNB RIN12VOL, RIN12MUTE RIN34VOL, RIN34MUTE
Table Differential Mode Register Settings
Figure Differential Mode Signal Paths
2008,
WM8959
INPUT MIXER VOLUME CONTROL
Pre-Production
Input Mixer volume controls described Table Left Channel Table Right Channel. Input levels Mute, 30dB boost. other gain controls provide adjustment from -12dB +6dB steps. prevent noise recommended that gain mute controls input mixers modified while signal paths active. volume control required input signal path recommended that input volume controls used instead input mixer gain registers. REGISTER ADDRESS (29h) LABEL L34MNB DEFAULT DESCRIPTION LIN34 Output INMIXL Mute Mute Un-Mute LIN34 Output INMIXL Gain +30dB LIN12 Output INMIXL Mute Mute Un-Mute LIN12 Output INMIXL Gain +30dB LIN2 INMIXL Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE AINLMUX Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE INMIXL Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB Note LR4BVOL must same value LL4BVOL when AINLMODE=01.
L34MNBST
L12MNB
L12MNBST
(2Bh)
LI2BVOL [2:0]
000b (Mute)
LR4BVOL [2:0]
000b (Mute)
LL4BVOL [2:0]
000b (Mute)
Table Left Input Mixer Volume Control
2008,
Pre-Production
WM8959
REGISTER ADDRESS (2A) LABEL R34MNB DEFAULT DESCRIPTION RIN34 Output INMIXR Mute Mute Un-Mute RIN34 Output INMIXR Gain +30dB RIN12 Output INMIXR Mute Mute Un-Mute RIN12 Output INMIXR Gain +30dB RIN2 INMIXR Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE AINRMUX Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE INMIXR Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB Note RL4BVOL must same value RR4BVOL when AINRMODE=01.
R34MNBST
R12MNB
R12MNBST
(2Ch)
RI2BVOL [2:0]
000b (Mute)
RL4BVOL [2:0]
000b (Mute)
RR4BVOL [2:0]
000b (Mute)
Table Right Input Mixer Volume Control
2008,
WM8959
DIGITAL INPUT PATH
Pre-Production
input data manipulated various ways support range different usage modes. Data from either digital audio interface channels routed either left right DAC. Mono mixing digital volume control also possible. "Digital Audio Interface" more information audio interface.
DIGITAL MIXING PATHS
Figure shows digital mixing paths available WM8959 digital core.
Figure Digital Mixing Paths
2008,
Pre-Production
WM8959
input data source each changed under software control using register bits DACL_SRC DACR_SRC. polarity each input also modified using register bits DACL_DATINV DACR_DATINV. These register bits described Table REGISTER ADDRESS (05h) LABEL DACL_SRC DEFAULT DESCRIPTION Left Data Source Select Left outputs left channel data Left outputs right channel data Right Data Source Select Right outputs left channel data Right outputs right channel data Left Invert Left output inverted Left output inverted Right Invert Right output inverted Right output inverted
DACR_SRC
(0Ah)
DACL_DATINV
DACR_DATINV
Table Routing Control
INTERFACE VOLUME BOOST
digital gain function available audio interface boost volume when small signal received DACDAT. This controlled using register bits DAC_BOOST[1:0]. prevent clipping input, this function should used when boosted data expected greater than 0dBFS. REGISTER ADDRESS (05h) 11:10 LABEL DAC_BOOST [1:0] DEFAULT DESCRIPTION Input Volume Boost +6dB (Input data must exceed -6dBFS) +12dB (Input data must exceed -12dBFS) +18dB (Input data must exceed -18dBFS)
Table Interface Volume Boost
2008,
WM8959
DIGITAL ANALOGUE CONVERTER (DAC)
Pre-Production
WM8959 DACs receive digital input data from DACDAT pin. digital audio data converted oversampled streams on-chip, true 24-bit digital interpolation filters. bitstream data enters multi-bit, sigma-delta DACs, which convert them high quality analogue audio signals. multi-bit architecture reduces high frequency noise sensitivity clock jitter. also uses Dynamic Element Matching technique high linearity distortion. analogue outputs from DACs then mixed with other analogue inputs using output mixers LOMIX, ROMIX speaker output mixer SPKMIX. DACs enabled DACL_ENA DACR_ENA register bits. REGISTER ADDRESS (03h) LABEL DACL_ENA (rw) DACR_ENA (rw) DEFAULT DESCRIPTION Left Enable disabled enabled Right Enable disabled enabled
Table Enable Control
DIGITAL VOLUME CONTROL
output level each controlled digitally over range from -71.625dB 0.375dB steps. level attenuation eight-bit code given 0.375 (X-192) 192; MUTE
DAC_VU controls loading digital volume control data. When DAC_VU DACL_VOL DACR_VOL control data will loaded into respective control register, will actually change digital gain setting. Both left right gain settings updated when written DAC_VU. This makes possible update gain both channels simultaneously. REGISTER ADDRESS (0Bh) LABEL DAC_VU DEFAULT DESCRIPTION Volume Update Writing this will cause left right volume updated simultaneously Left Digital Volume (See Table volume range) Volume Update Writing this will cause left right volume updated simultaneously Right Digital Volume (See Table volume range)
(0Ch)
DACL_VOL [7:0] DAC_VU
1100_0000b (0dB)
DACR_VOL [7:0]
1100_0000b (0dB)
Table Digital Volume Control
2008,
Pre-Production
WM8959
MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000
DACL_VOL DACL_VOL DACL_VOL DACL_VOL DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB) DACR_VOL Volume (dB)
Table Digital Volume Range
2008,
WM8959
SOFT MUTE SOFT UN-MUTE
Pre-Production
WM8959 soft mute function which, when enabled, gradually attenuates volume output. When soft mute disabled, gain will either gradually ramp back digital gain setting, return instantly digital gain setting, depending DAC_MUTEMODE register bit. soft-muted default (DAC_MUTE play back audio signal, this function must first disabled setting DAC_MUTE Soft Mute Mode would typically enabled (DAC_MUTEMODE when using DAC_MUTE during playback audio data that when DAC_MUTE subsequently disabled, sudden volume increase will create noise jumping immediately previous volume level (e.g. resuming playback after pausing during track). Soft Mute Mode would typically disabled (DAC_MUTEMODE when un-muting start music file, order that first part track attenuated (e.g. when starting playback track, resuming playback after pausing between tracks). muting un-muting using volume control bits DACL_VOL DACR_VOL.
muting un-muting using soft mute DAC_MUTE. Soft Mute Mode enabled (DAC_MUTEMODE
muting un-muting using soft mute DAC_MUTE. Soft Mute Mode enabled (DAC_MUTEMODE
Figure Mute Control volume ramp rate during soft mute un-mute controlled DAC_MUTERATE bit. Ramp rates fs/32 fs/2 selectable shown Table ramp rate determines rate which volume will increased decreased. actual ramp time depends extent difference between muted un-muted volume settings. REGISTER ADDRESS (0Ah) LABEL DAC_MUTERATE DEFAULT DESCRIPTION Soft Mute Ramp Rate Fast ramp (fs/2, maximum ramp time 10.7ms fs=48k) Slow ramp (fs/32, maximum ramp time 171ms fs=48k) Soft Mute Mode Disabling soft-mute (DAC_MUTE=0) will cause volume change immediately DACL_VOL DACR_VOL settings Disabling soft-mute (DAC_MUTE=0) will cause volume ramp gradually DACL_VOL DACR_VOL settings Soft Mute Control Un-mute Mute
DAC_MUTEMODE
DAC_MUTE
Table Soft-Mute Control
2008,
Pre-Production
WM8959
MONO
digital mono-mix mode enabled using DAC_MONO register bit. This mono will output enabled DACs. prevent clipping, -6dB attenuation automatically applied mono mix. REGISTER ADDRESS (0Ah) LABEL DAC_MONO DEFAULT DESCRIPTION Mono Stereo Mono (Mono output enabled DACs)
Table Mono
DE-EMPHASIS
Digital de-emphasis applied playback data (e.g. when data comes from with pre-emphasis used recording). De-emphasis filtering available sample rates 48kHz, 44.1kHz 32kHz. "Digital Filter Characteristics" section details de-emphasis filter characteristics. REGISTER ADDRESS (0Ah) Control LABEL DEEMP [1:0] DEFAULT DESCRIPTION De-Emphasis Control de-emphasis 32kHz sample rate 44.1kHz sample rate 48kHz sample rate
Table De-Emphasis Control
SLOPING STOPBAND FILTER
filter types available, selected register DAC_SB_FILT. When operating lower sample rates (e.g. during voice communication) recommended that sloping stopband filter type selected (DAC_SB_FILT=1) reduce out-of-band noise which audible sample rates. "Digital Filter Characteristics" details filter characteristics. REGISTER ADDRESS (0Ah) Control LABEL DAC_SB_FILT DEFAULT DESCRIPTION Selects filter characteristics Normal mode Sloping stopband mode
Table Sloping Stopband Filter
2008,
WM8959
OUTPUT SIGNAL PATH
Pre-Production
WM8959 output routing mixers provide high degree flexibility, allowing operation many simultaneous signal paths through device various analogue outputs. outputs provide many combinations headphone, loudspeaker single-ended line drivers. "Analogue Outputs" further details these outputs. WM8959 output signal paths control registers illustrated Figure
LONMIX
LLOPGALON LROPGALON LON_ENA Line
MAIN REGISTER REFERENCE REGISTER ALSO REFERENCED ELSEWHERE DIAGRAM READBACK AVAILABLE
OUTPUT MIXERS
LOPLON
LL12LOP LR12LOP LLOPGALOP
Line LOATTN
LOP_ENA
LOPMIX
Left Line Input Speaker Voice Left Line Input Left Output Mixer Left AINLMUX output LI3LO LRI3LO LL12LO LR12LO LI3LOVOL[2:0] LRI3LOVOL[2:0] DACL LL12LOVOL[2:0] LR12LOVOL[2:0] LRBLOVOL[2:0] LLBLOVOL[2:0] LOMIX_ENA LB2SPK LI2SPK LOPGASPK LDSPK RDSPK
(RDRO RDSPK must enabled same time)
OUT3MIX
OUT3_ENA LI4O3 LPGAO3
OUT3ATTN LOUT_ENA
OUT3
LRBLO LLBLO
LDLO
LOPGA
LOUT
SPKMIX
LOUTVOL[6:0] SPKPGA_ENA SPK_ENA SPK_ENA
LOMIX
LOPGA_ENA
LOPGAVOL [6:0]
(LDLO LDSPK must enabled same time)
SPKPGA
DCGAIN ACGAIN [2:0] [2:0]
SPKN SPKP
ROPGASPK RI2SPK RB2SPK SPKATTN [1:0]
ROMIX_ENA
RRBROVOL[2:0] DAC_MUTE, DAC_MUTEMODE, DAC_MUTERATE, DAC_SB_FILT, DEEMP[1:0] DACR RLBROVOL[2:0] RR12ROVOL[2:0] RL12ROVOL[2:0] RLI3ROVOL [2:0] RRI3ROVOL[2:0] AINRMUX output Right Right Line Input Right Output Mixer Voice Right Line Input Speaker
ROMIX ROPGA_ENA [6:0]
ROPGAVOL
SPKVOL [6:0] ROUT_ENA ROUTVOL[6:0] OUT4_ENA
ROPGA
RDRO RRBRO RLBRO RR12RO RL12RO RLI3RO RRI3RO RPGAO4 RI4O4
ROUT
OUT4ATTN
OUT4
OUT4MIX
ROPMIX
RROPGAROP RL12ROP RR12ROP ROATTN RON_ENA Line ROP_ENA Line
ROPRON RLOPGARON RROPGARON
RONMIX
Figure Control Registers Output Signal Path
2008,
Pre-Production
WM8959
OUTPUT SIGNAL PATHS ENABLE
output mixers drivers independently enabled disabled described Table Note that headphone outputs LOUT ROUT have dedicated volume controls. result, output PGAs LOPGA ROPGA need enabled provide volume control LOUT ROUT outputs. REGISTER ADDRESS (03h) LABEL LON_ENA (rw) LOP_ENA (rw) RON_ENA (rw) ROP_ENA (rw) SPKPGA_ENA (rw) DEFAULT DESCRIPTION Line LONMIX Enable disabled enabled Line LOPMIX Enable disabled enabled Line RONMIX Enable disabled enabled Line ROPMIX Enable disabled enabled SPKMIX Mixer Speaker Enable disabled enabled Note that SPKMIX SPKPGA also enabled when SPK_ENA set. LOPGA Left Volume Control Enable disabled enabled ROPGA Right Volume Control Enable disabled enabled LOMIX Left Output Mixer Enable disabled enabled ROMIX Right Output Mixer Enable disabled enabled SPKMIX Mixer, Speaker Speaker Output Enable disabled enabled OUT3 OUT3MIX Enable disabled enabled OUT4 OUT4MIX Enable disabled enabled LOUT (Left Headphone Output) Enable disabled enabled ROUT (Right Headphone Output) Enable disabled enabled
LOPGA_ENA (rw) ROPGA_ENA (rw) LOMIX_ENA (rw) ROMIX_ENA (rw) SPK_ENA (rw)
(01h)
OUT3_ENA (rw) OUT4_ENA (rw) LOUT_ENA (rw) ROUT_ENA (rw)
Table Output Signal Paths Enable
2008,
WM8959
OUTPUT MIXER CONTROL
Pre-Production
Output Mixer volume controls described Table Left Channel Table Right Channel. gain each analogue input paths controlled independently range described Table input levels controlled digital volume control "Digital Analogue Converter (DAC)" further details this control. REGISTER ADDRESS (2Dh) LABEL LRI3LO DEFAULT DESCRIPTION RIN3 LOMIX Mute Mute Un-mute LIN3 LOMIX Mute Mute Un-mute RIN3 LOMIX Volume (See Table Volume Range) LIN3 LOMIX Volume (See Table Volume Range) LIN12 Output LOMIX Mute Mute Un-mute LIN12 Output LOMIX Volume (See Table Volume Range) RIN12 Output LOMIX Mute Mute Un-mute RIN12 Output LOMIX Volume (See Table Volume Range) AINRMUX Output LOMIX Mute Mute Un-mute AINRMUX Output LOMIX Volume (See Table Volume Range) AINLMUX Output LOMIX Mute Mute Un-mute AINLMUX Output LOMIX Volume (See Table Volume Range) Left LOMIX Mute Mute Un-mute Note: LDLO must muted when LDSPK=1
(2Dh)
LLI3LO
(31h) (2Fh) (2Dh)
LRI3LOVOL [2:0] LLI3LOVOL [2:0] LL12LO
000b 000b
(2Fh) (2Dh)
LL12LOVOL [2:0] LR12LO
000b
(2Fh) (2Dh)
LR12LOVOL [2:0] LRBLO
000b
(31h) (2Dh)
LRBLOVOL [2:0] LLBLO
000b
(31h) (2Dh)
LLBLOVOL [2:0] LDLO
000b
Table Left Output Mixer (LOMIX) Volume Control
2008,
Pre-Production
WM8959
REGISTER ADDRESS (2Eh) LABEL RLI3RO DEFAULT DESCRIPTION LIN3 ROMIX Mute Mute Un-mute RIN3 ROMIX Mute Mute Un-mute LIN3 ROMIX Volume (See Table Volume Range) RIN3 ROMIX Volume (See Table Volume Range) LIN12 Output ROMIX Mute Mute Un-mute LIN12 Output ROMIX Volume (See Table Volume Range) RIN12 Output ROMIX Mute Mute Un-mute RIN12 Output ROMIX Volume (See Table Volume Range) AINLMUX Output ROMIX Mute Mute Un-mute AINLMUX Output ROMIX Volume (See Table Volume Range) AINRMUX Output ROMIX Mute Un-mute AINRMUX Output ROMIX Volume (See Table Volume Range) Right ROMIX Mute Mute Un-mute Note: RDRO must muted when RDSPK=1
(2Eh)
RRI3RO
(32h) (30h) (2Eh)
RLI3ROVOL [2:0] RRI3ROVOL [2:0] RL12RO
000b 000b
(30h) (2Eh)
RL12ROVOL [2:0] RR12RO
000b
(30h) (2Eh)
RR12ROVOL [2:0] RLBRO
000b
(32h) (2Eh)
RLBROVOL [2:0] RRBRO
000b
(32h) (2Eh)
RRBROVOL [2:0] RDRO
000b
Table Right Output Mixer (ROMIX) Volume Control
VOLUME SETTING
VOLUME (dB)
Table LOMIX ROMIX Volume Range
2008,
WM8959
OUTPUT SIGNAL PATH VOLUME CONTROL
Pre-Production
output drivers LOPGA, ROPGA, LOUT ROUT independently controlled shown Table Table minimise noise recommended that only LOPGAVOL, ROPGAVOL, LOUTVOL ROUTVOL modified while output signal path active. Other gain controls provided output signal path provide appropriate relative scaling signals from different sources, prevent clipping when multiple signals mixed. prevent noise, only gain controls noted above should modified while playback active. prevent "zipper noise", zero-cross function provided these output paths, that when enabled, volume updates will take place until zero-crossing detected. event long period without zero-crossings, timeout function available. When this function enabled (using TOCLK_ENA register bit), volume will update after timeout period earlier zero-cross occurred. timeout period TOCLK_RATE. "Clocking Sample Rates" more information these fields. OPVU controls loading output driver volume data. When OPVU volume control data will loaded into respective control register, will actually change gain setting. LOPGA, ROPGA, LOUT ROUT volume settings updated when written OPVU. This makes possible update gain output paths simultaneously. Note that headphone outputs LOUT ROUT have dedicated volume controls. result, output PGAs LOPGA ROPGA need enabled provide volume control LOUT ROUT outputs. REGISTER ADDRESS (20h) LABEL OPVU[2] DEFAULT DESCRIPTION Output Volume Update Writing this will update LOPGA, ROPGA, LOUTVOL ROUTVOL volumes simultaneously. LOPGA Zero Cross Enable Zero cross disabled Zero cross enabled LOPGA Volume (See Table output volume control range) Output Volume Update Writing this will update LOPGA, ROPGA, LOUTVOL ROUTVOL volumes simultaneously. ROPGA Zero Cross Enable Zero cross disabled Zero cross enabled ROPGA Volume (See Table output volume control range) Output Volume Update Writing this will update LOPGA, ROPGA, LOUTVOL ROUTVOL volumes simultaneously. LOUT (Left Headphone Output) Zero Cross Enable Zero cross disabled Zero cross enabled LOUT (Left Headphone Output) Volume (See Table output volume control range)
LOPGAZC
LOPGAVOL [6:0] OPVU[3]
(0dB)
(21h)
ROPGAZC
ROPGAVOL [6:0] OPVU[0]
(0dB)
(1Ch)
LOZC
LOUTVOL [6:0]
(mute)
2008,
Pre-Production REGISTER ADDRESS (1Dh) LABEL OPVU[1] DEFAULT
WM8959
DESCRIPTION Output Volume Update Writing this will update LOPGA, ROPGA, LOUTVOL ROUTVOL volumes simultaneously. ROUT (Right Headphone Output) Zero Cross Enable Zero cross disabled Zero cross enabled ROUT (Right Headphone Output) Volume (See Table output volume control range)
ROZC
ROUTVOL [6:0]
(mute)
Table LOPGA, ROPGA, LOUT ROUT Volume Control
2008,
WM8959
LOPGAVOL, ROPGAVOL, LOUTVOL, ROUTVOL SPKVOL LOPGAVOL, ROPGAVOL, LOUTVOL, ROUTVOL SPKVOL
Pre-Production
Volume (dB) MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
Volume (dB)
Table LOPGA, ROPGA, LOUT, ROUT SPKVOL Volume Range
2008,
Pre-Production
WM8959
speaker mixer SPKMIX, speaker SPKPGA outputs SPKN SPKP controlled described Table Care should taken avoid clipping when enabling more than path speaker mixer. Register bits SPKATTN control speaker output attenuation used avoid clipping when more than full scale signal input mixer. Fine adjustment speaker output made using SPKVOL register field. prevent "zipper noise" when adjusting SPKVOL, zero-cross function provided that, when enabled, volume updates will take place until zero-crossing detected. event long period without zero-crossings, timeout function available. When this function enabled (using TOCLK_ENA register bit), volume will update after timeout period earlier zerocross occurred. timeout period TOCLK_RATE. "Clocking Sample Rates" more information these fields. REGISTER ADDRESS (36h) LABEL LB2SPK DEFAULT DESCRIPTION AINLMUX Output SPKMIX Mute Un-mute AINRMUX Output SPKMIX Mute Un-mute LIN2 SPKMIX Mute Un-mute RIN2 SPKMIX Mute Un-mute LOPGA SPKMIX Mute Un-mute ROPGA SPKMIX Mute Un-mute Left SPKMIX Mute Un-mute Note: LDSPK must muted when LDLO=1 Right SPKMIX Mute Un-mute Note: RDSPK must muted when RDRO=1 Speaker Output Attenuation (SPKN SPKP) -6dB -12dB mute SPKPGA Zero Cross Enable Zero cross disabled Zero cross enabled SPKPGA Volume (see Table SPKPGA volume control range)
RB2SPK
LI2SPK
RI2SPK
LOPGASPK
ROPGASPK
LDSPK
RDSPK
(22h)
SPKATTN [1:0]
(26h)
SPKZC
SPKVOL [6:0]
(0dB)
Table Speaker Output Volume Control
2008,
WM8959
Pre-Production output mixers OUT3MIX OUT4MIX their outputs OUT3 OUT4 controlled described Table Care should taken avoid clipping when enabling more than path OUT3 OUT4. OUT3ATTN OUT4ATTN attenuation controls used prevent clipping when more than full scale signal input mixers. REGISTER ADDRESS (1Fh) LABEL OUT3MUTE DEFAULT DESCRIPTION OUT3 Mute Un-mute Mute OUT3 Attenuation -6dB OUT4 Mute Un-mute Mute OUT4 Attenuation -6dB LIN4/RXN OUT3MIX Mute Un-mute LOPGA OUT3MIX Mute Un-mute RIN4/RXP OUT4MIX Mute Un-mute ROPGA OUT4MIX Mute Un-mute
OUT3ATTN
OUT4MUTE
OUT4ATTN
(33h)
LI4O3
LPGAO3
RI4O4
RPGAO4
Table OUT3 OUT4 Volume Control
2008,
Pre-Production
WM8959
output mixers LOPMIX LONMIX their outputs controlled described Table Care should taken avoid clipping when enabling more than path LON. LOATTN attenuation control used prevent clipping when more than full scale signal input mixer. REGISTER ADDRESS (1Eh) LABEL LONMUTE DEFAULT DESCRIPTION Line Output Mute Un-mute Mute Line Output Mute Un-mute Mute Attenuation -6dB LOPGA LONMIX Mute Un-mute ROPGA LONMIX Mute Un-mute Inverted Output LONMIX Mute Un-mute RIN12 Output LOPMIX Mute Un-mute LIN12 Output LOPMIX Mute Un-mute LOPGA LOPMIX Mute Un-mute
LOPMUTE
LOATTN
(34h)
LLOPGALON
LROPGALON
LOPLON
LR12LOP
LL12LOP
LLOPGALOP
Table Volume Control
2008,
WM8959
Pre-Production output mixers ROPMIX RONMIX their outputs controlled described Table Care should taken avoid clipping when enabling more than path RON. ROATTN attenuation control used prevent clipping when more than full scale signal input mixer. REGISTER ADDRESS (1Eh) LABEL RONMUTE DEFAULT DESCRIPTION Line Output Mute Un-mute Mute Line Output Mute Un-mute Mute Attenuation -6dB ROPGA RONMIX Mute Un-mute LOPGA RONMIX Mute Un-mute Inverted Output RONMIX Mute Un-mute LIN12 Output ROPMIX Mute Un-mute RIN12 Output ROPMIX Mute Un-mute ROPGA ROPMIX Mute Un-mute
ROPMUTE
ROATTN
(35h)
RROPGARON
RLOPGARON
ROPRON
RL12ROP
RR12ROP
RROPGAROP
Table Volume Control
2008,
Pre-Production
WM8959
ANALOGUE OUTPUTS
speaker, headphone line outputs highly configurable used many different ways.
SPEAKER OUTPUT CONFIGURATIONS
speaker outputs SPKP SPKN driven speaker mixer SPKMIX, speaker volume control SPKPGA, which output that combination following signals: Left Right outputs LOMIX ROMIX outputs volume controls LOPGA ROPGA Line inputs LIN2 RIN2 Output from left right input mixers (AINLMUX AINRMUX)
speaker mixer controlled described under "Output Signal Path". speaker mixer output attenuated avoid clipping when mixing multiple signal inputs. Fine adjustment speaker output made speaker volume control SPKPGA. speaker outputs SPKP SPKN operate configuration Class Class amplifier modes. mode selected register CDMODE. outputs capable driving into load 500mW class mode thermal reasons) room temperature. performance higher temperatures, Error! Reference source found. "Recommended Operating Conditions" section. Ultra-low leakage high PSRR allow speaker supply SPKVDD directly connected lithium battery. levels signal boost provided order deliver maximum output power many commonly-used SPKVDD/AVDD combinations. These boost options available both Class Class modes. gain levels from 1.0x 1.8x selected using register bits ACGAIN DCGAIN. prevent noise, DCGAIN ACGAIN should modified while speaker outputs enabled. Note that appropriate SPKVDD supply voltage must provided prevent waveform clipping when speaker boost used. AVDD SPKVDD
DCGAIN[2:0] SPKATTN[1:0] SPEAKER MIXER SPKVOL[6:0] ACGAIN[2:0]
SPKP SPKN
Connection provides additional gain
AGND
DCGAIN[2:0] ACGAIN[2:0] 1.00x 1.27x 1.40x 1.52x 1.67x 1.80x
SPKGND
SPKVDD AVDD VMID DCGAIN VMID AGND Signal ACGAIN VMID DCGAIN
Figure Speaker Boost Operation
2008,
WM8959
REGISTER ADDRESS (23h) LABEL CDMODE DEFAULT
Pre-Production
DESCRIPTION Speaker Class Mode Enable Class mode Class mode Speaker Boost 1.00x boost (+0dB) 1.27x boost (+2.1dB) 1.40x boost (+2.9dB) 1.52x boost (+3.6dB) 1.67x boost (+4.5dB) 1.80x boost (+5.1dB) Reserved Speaker Boost 1.00x boost (+0dB) 1.27x boost (+2.1dB) 1.40x boost (+2.9dB) 1.52x boost (+3.6dB) 1.67x boost (+4.5dB) 1.80x boost (+5.1dB) Reserved
(25h)
DCGAIN [2:0]
000b (1.0x)
ACGAIN [2:0]
000b (1.0x)
Table Speaker Boost Control
HEADPHONE OUTPUT CONFIGURATIONS
headphone outputs LOUT, ROUT, OUT3 OUT4 each driven different output mixers described below. LOUT ROUT pins output LOMIX ROMIX outputs respectively. OUT3 output mixer OUT3MIX, whose inputs are: LIN4/RXN LOMIX output volume control LOPGA
OUT4 output mixer OUT4MIX, whose inputs are: RIN4/RXP ROMIX output volume control ROPGA
Full volume control available LOUT ROUT. -6dB attenuation available OUT3 OUT4, with full volume control available using LOPGA ROPGA LOMIX ROMIX signals. outputs LOUT, ROUT, OUT3 OUT4 capable driving 40mW into loads such stereo headsets, headphones, and/or handset speaker. AC-coupled, capless mode fully differential headphone drive modes available. AC-coupled output possible each LOUT, ROUT, OUT3 OUT4 simultaneously. Capless headphone output possible LOUT ROUT using either OUT3 OUT4 common return path. (This achieved muting OUT3 OUT4 required.) mono differential input (e.g. connection external voice CODEC), then OUT3 OUT4 used differential output capable driving handset speaker. signal paths from OUT4 from OUT3 direct, pass through additional amplifiers. This reduces standby active power consumption improves signal quality.
2008,
Pre-Production
WM8959
When driving handset speaker using OUT3 OUT4 from LOMIX ROMIX, required phase difference provided inverting outputs. Alternatively, phase difference achieved mixing Left Right channels through LOMIX OUT3 muting OUT4. Similarly, phase difference achieved mixing Left Right channels through ROMIX OUT4 muting OUT3. Note that differential output will provide additional gain output pins. Register bits OUT3ATTN OUT4ATTN used compensate this gain required. Fully differential headphone drive possible between LOUT OUT3 between ROUT OUT4. Routing LOPGA OUT3 ROPGA OUT4 results phase inversion LOUT respect OUT3 ROUT with respect OUT4. This allows fully differential headset drive, greatly improved crosstalk performance, improved bass response, increased noise immunity removing need large expensive DC-blocking capacitors. with with
ensure fully balanced differential operation, LOUT OUT3 must same gain each other, ROUT OUT4 must same gain each other. This best achieved setting OUT3ATTN OUT4ATTN 0dB, whilst setting volume controls LOPGAVOL LOUTVOL matching levels setting volume controls ROPGAVOL ROUTVOL matching levels. Some example headphone output configurations shown below.
Figure AC-Coupled Headphone Drive
Figure Capless Mode Headphone Drive
Figure Headphone Speaker Drive
Figure Fully Differential Headphone Drive
LINE OUTPUT CONFIGURATIONS
line outputs LON, LOP, each driven different output mixers described below. pins output LIN12 input PGA, RIN12 input either LOMIX ROMIX outputs. output ROMIX, LOMIX phase-inverted copy LOP. output LOMIX, ROMIX phase-inverted copy ROP. Volume control LOMIX ROMIX available cases above LOPGA ROPGA. additional -6dB attenuation option provided outputs. 2008,
WM8959
Pre-Production outputs LON, LOP, capable driving line loads only. Single ended output possible these output simultaneously. Differential output also possible between between RON. Typical applications line outputs (single-ended differential) are: Handset headset microphone output external voice CODEC Stereo line output Output external speaker driver(s) support stereo loudspeakers
Some example line output configurations shown below.
Figure Stereo Line
Figure Differential Output
Figure Stereo Line
Figure Differential Output Speaker Driver
Figure Stereo Line
Figure Stereo Differential Line 2008,
Pre-Production
WM8959
DISABLED OUTPUTS
Whenever analogue output disabled, connected VREF through resistor; this feature enabled setting BUFIOEN "Pop Suppression Control". This helps prevent noise when output re-enabled. resistance between VREF each output controlled using register VROI. default, high resistance used Headphone outputs (LOUT, ROUT, OUT3 OUT4) Line outputs (LON, LOP, ROP). impedance desired disabled outputs, VROI then decreasing resistance about cases. Note that disabled output used common ground connection capless headphone output described earlier. REGISTER ADDRESS (37h) Additional Control LABEL VROI DEFAULT DESCRIPTION VREF Analogue Output Resistance (Disabled Outputs) (Headphone) (Line Out) from buffered VMID output from buffered VMID output
Table Disabled Outputs VREF Resistance
THERMAL SHUTDOWN
speaker headphone outputs drive very large currents. protect WM8959 from overheating thermal shutdown circuit included. device temperature reaches approximately thermal shutdown circuit enabled (TSHUT_ENA TSHUT_OPDIS speaker headphone amplifiers (LOUT, ROUT, SPKP, SPKN, OUT3 OUT4) will disabled. TSHUT_ENA must enable temperature sensor when using TSHUT_OPDIS thermal shutdown function. output temperature sensor also output GPIO pins. REGISTER ADDRESS (02h) LABEL TSHUT_ENA (rw) TSHUT_OPDIS (rw) DEFAULT DESCRIPTION Thermal Sensor Enable Thermal sensor disabled Thermal sensor enabled Thermal Shutdown Enable (Requires thermal sensor enabled) Thermal shutdown disabled Thermal shutdown enabled
Table Thermal Shutdown
When speaker driver operating class mode internal power dissipation WM8959 likely significantly higher than when operating class mode. Note: prevent potential pops clicks THSUT_ENA TSHUT_OPDIS need configured while speaker headphone outputs off, i.e. LOUT_ENA, ROUT_ENA, OUT3_ENA, OUT4_ENA SPK_ENA (see also Table 70).
2008,
WM8959
GENERAL PURPOSE INPUT/OUTPUT
Pre-Production
WM8959 provides number versatile GPIO functions enable features such mobile support, Wi-Fi voice call recording, button accessory detection clock output. WM8959 multi-purpose pins these functions. GPIO1, GPIO3, GPIO4 GPIO5: Dedicated GPIO pins. LIN3/GPI7 RIN3/GPI8: Analogue inputs button/accessory detect inputs.
following functions available some GPIO pins. Alternative interface (DACDAT, DACLRC, BCLK) Button detect (latched with programmable de-bounce) MICBIAS Accessory current short circuit detect Clock output Temperature sensor output lock output Logic logic output Interrupt event output Serial data output (register readback)
functions available each GPIO pins identified Table GPIO FUNCTION GPIO1 BCLK2 DACLRC2 DACDAT2 Button/Accessory Detect Input Clock Output Temperature Lock Logic Logic Interrupt SDOUT (Readback Data) Pull-up Pull-down Available GPIO3 GPIO PINS GPIO4 GPIO5 GPI7 GPI8
Table Functions Available GPIO Pins
GPIO pins configured combination register settings described Table Table following section. order precedence control GPIO pins listed below. pull-up pull-down (GPIOn_PU, GPIOn_PD) Audio Interface GPIO Tristate (AIF_TRIS) configuration (AIFSEL GPIO1_ENA) GPIO functionality (GPIOn_SEL)
2008,
Pre-Production
WM8959
GPIO CONTROL REGISTERS
Table shows dual-function GPIO pins configured operate their different modes. Note that order precedence described earlier applies. Register field AIF_SEL selects function GPIO3, GPIO4 GPIO5 between Audio Interface GPIO functions. Register field GPIO1_ENA enables GPIO functionality GPIO1. Register AIF_TRIS, when set, takes precedence over AIF_SEL GPIO1 tri-states GPIO pins. REGISTER ADDRESS (08h) LABEL AIF_SEL DEFAULT DESCRIPTION Audio Interface Select Audio interface Audio interface (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) GPIO1 Enable GPIO1 enabled GPIO1 enabled Audio Interface GPIO Tristate Audio interface GPIO pins operate normally Tristate audio interface GPIO pins
(09h)
GPIO1_ENA
AIF_TRIS
Table GPIO Function Select
GPIO pins GPIO Register behaviour also controlled register fields described Table Note order precedence described earlier applies. Pull-up pull-down resistors enabled GPIO1, GPIO3, GPIO4 GPIO5. enabled, these settings take precedence over other GPIO selections that pin. Note that, default, pull-down resistors GPIO3, GPIO4 GPIO5 enabled. When GPIO pins used inputs, de-bounce interrupt masking controlled GPIO pins (including GPI7 GPI8) using GPIOn_DEB_ENA GPIOn_IRQ_ENA bits shown Table each GPIO1 GPIO3 GPIO5, register field GPIOn_SEL used select functions individual GPIO pins shown Table Note that this control lowest precedence only effective when GPIOn_PU, GPIOn_PD, AIF_TRIS, AIFSEL GPIO1_ENA allow GPIO functionality that GPIO pin.
2008,
WM8959
REGISTER ADDRESS (13h) (14h) 11:8 (15h) (16h) LABEL GPIO1_DEB_ENA GPIO1_IRQ_ENA GPIO1_PU GPIO1_PD GPIO1_SEL[3:0] GPIO4_DEB_ENA GPIO4_IRQ_ENA GPIO4_PU GPIO4_PD GPIO4_SEL[3:0] GPIO3_DEB_ENA GPIO3_IRQ_ENA GPIO3_PU GPIO3_PD GPIO3_SEL[3:0] GPIO5_DEB_ENA GPIO5_IRQ_ENA GPIO5_PU GPIO5_PD GPIO5_SEL[3:0] GPI8_DEB_ENA GPI8_IRQ_ENA GPI8_ENA GPI7_DEB_ENA GPI7_IRQ_ENA GPI7_ENA DEFAULT 0000b 0000b 0000b 0000b
Pre-Production
DESCRIPTION Table GPIO1 control description
Table GPIO4 control description
Table GPIO3 control description
Table GPIO5 control description
Table GPIn control description Table GPIn control description
Table GPIO Control
2008,
Pre-Production following table describes coding fields listed Table REGISTER ADDRESS Registers (13h) (15h) (See Table LABEL GPIOn_DEB_ENA DEFAULT
WM8959
De-Bounce disabled (Not de-bounced) enabled (Requires MCLK input TOCLK_ENA Enable disabled enabled GPIO Pull-Up Resistor Enable Pull-up disabled Pull-up enabled (Approx 150k) GPIO Pull-Down Resistor Enable Pull-down disabled Pull-down enabled (Approx 150k) GPIOn Function Select 0000 Input 0001 Clock output (SYSCLK/OPCLKDIV) 0010 Logic 0011 Logic 0100 Lock output 0101 Temperature output 0110 SDOUT data output 0111 output 1000 Detect 1001 Short Circuit Detect 1010 1111 Reserved GPIn Input Enable disabled GPIn input enabled GPIn input
GPIOn_IRQ_ENA GPIOn_PU GPIOn_PD GPIOn_SEL[3:0]
Table 0000b
GPIn_ENA Table GPIO Function Control Bits
polarity GPIO/GPI inputs configured using GPIO_POL register bits. This described Table REGISTER ADDRESS (17h) LABEL GPIO_POL [7:0] (rw) DEFAULT DESCRIPTION GPIOn Input Polarity Non-inverted Inverted GPIO_POL[7] GPI8 polarity GPIO_POL[6] GPI7 polarity GPIO_POL[5] Reserved GPIO_POL[4] GPIO5 polarity GPIO_POL[3] GPIO4 polarity GPIO_POL[2] GPIO3 polarity GPIO_POL[1] Reserved GPIO_POL[0] GPIO1 polarity
Table GPIO Polarity
Each available GPIO functions described turn following sections.
2008,
WM8959
ALTERNATIVE INTERFACE
Pre-Production
WM8959 configured select between different audio interfaces, providing capability receive input data BCLK2, DACLRC2 DACDAT2 instead BCLK, DACLRC DACDAT. This selection made register AIF_SEL, described Table alternative interface, following register settings required: AIF_TRIS AIF_SEL GPIO3_PU GPIO4_PU GPIO5_PU GPIO3_PD GPIO4_PD GPIO5_PD
Note that additional devices also connected main interface pins using mode. "Digital Audio Interface" section further details controlling audio interface pins. alternative interface connection illustrated Figure
DIGITAL AUDIO INTERFACE
A-law u-law support Support
GPIO
Alternative Interface Button Control Accessory Detect Clock Output
AIF_SEL
Processor
Figure Alternative Interface
Processor
GPIO3/BCLK2 GPIO4/DACLRC2 GPIO5/DACDAT2
2008,
BCLK
DACDAT
DACLRC
Pre-Production
WM8959
BUTTON CONTROL
WM8959 GPIO supports button control detection with full status readback inputs five inputs output). inputs latched Register, with de-bounce available normal operation. De-bouncing disabled order allow device respond wakeup events while processor disabled unable provide clock de-bouncing. enable button control accessory detection, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) LMN3 LLI3LO RLI3LO (only required using GPI7) RMN3 RRI3LO RI3RO (only required using GPI8) AIF_TRIS GPIOn_SEL 0000 each required GPIO button input
Programmable pull-up pull-down resistors available GPIO1 GPIO3 GPIO5. These should according external circuit configuration. Note that pull-up pull-down resistors available GPI7 GPI8 input pins. Note that analogue input paths GPI7 GPI8 must disabled described above when using these digital inputs. this application, more GPIO pins configured Interrupt event desired. This controlled GPIOn_IRQ_ENA bits described Table GPIO status fields contained Register (R18) read time else response Interrupt event. Table more details Interrupt function. example configuration button control GPIO function illustrated Figure
Figure Example Button Control Using GPIO Pins
Note: GPIOs referenced DBVDD GPIs referenced AVDD
2008,
WM8959
MICBIAS CURRENT ACCESSORY DETECT
Pre-Production
MICBIAS current detect function provided accessory detection. When microphone current detected (e.g. when headset inserted), interrupt event generated microphone status read back control interface. MICBIAS current detect threshold programmable. short-circuit current detection also available, with programmable threshold. These functions enabled register MCD; thresholds programmable register fields MCDTHR MCDSCTR shown Table polarity current detect GPIO signals controlled register bits MICDET_POL MICSHRT_POL. Note that these polarity inversion bits apply Interrupt register behaviour only; they affect direct GPIO output Current Detect functions. respective interrupt events masked enabled register bits MICDET_IRQ_ENA MICSHRT_IRQ_ENA. MICBIAS current threshold status bits contained Register (R18) read time else response Interrupt event. Table more details Interrupt function. direct output MICBIAS current detect function required external pins WM8959, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 1000 selected GPIO MICBIAS Current Detect output GPIOn_SEL 1001 selected GPIO MICBIAS Short Circuit Detect output GPIOn_PU selected GPIO MICBIAS output pins GPIOn_PD selected GPIO MICBIAS output pins
register fields used configure MICBIAS Current Detect function described Table REGISTER ADDRESS (3Ah) LABEL MCDSCTH [1:0] DEFAULT DESCRIPTION MICBIAS Short Circuit Detect Threshold 600uA 1200uA 1800uA 2400uA These values AVDD=3.3V scale proportionally with AVDD. MICBIAS Current Detect Threshold 200uA 350uA 500uA 650uA 800uA 950uA 1100uA 1250uA These values AVDD=3.3V scale proportionally with AVDD. MICBIAS Current Short Circuit Detect Enable disabled enabled MICBIAS short circuit detect polarity Non-inverted Inverted
MCDTHR [2:0]
000b
(17h)
MICSHRT_POL (rw)
2008,
Pre-Production REGISTER ADDRESS LABEL MICDET_POL (rw) MICSHRT_IRQ_ENA DEFAULT
WM8959
DESCRIPTION MICBIAS current detect polarity Non-inverted Inverted MICBIAS short circuit detect Enable disabled enabled MICBIAS current detect Enable disabled enabled
(16h)
MICDET_IRQ_ENA
Table MICBIAS Current Detect Control
current detect function operates according following truth table: LABEL Short Circuit Detect Short Circuit Detect Current Detect Current Detect VALUE DESCRIPTION MCDSCTH current threshold exceeded MCDSCTH current threshold exceeded MCDTHR current threshold exceeded MCDTHR current threshold exceeded
Table Truth Table GPIO Output MICBIAS Current Detect Function
CLOCK OUTPUT
clock output (OPCLK) derived from SYSCLK output GPIO1 GPIO3 GPIO5. SYSCLK derived from MCLK (either directly, conjunction with PLL), used provide internal clocking WM8959 (see "Clocking Sample Rates" section more information). programmable clock divider OPCLKDIV controls frequency OPCLK output. This clock enabled register OPCLK_ENA. "Clocking Sample Rates" definition this register field. enable clock output more GPIO pins, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0001 selected GPIO clock output GPIOn_PU selected GPIO clock output GPIOn_PD selected GPIO clock output
2008,
WM8959
TEMPERATURE SENSOR OUTPUT
Pre-Production
WM8959 output drivers generate large amount heat. protect device from overheating thermal shutdown function provided (see "Thermal Shutdown" section more information). polarity Thermal Shutdown sensor controlled register TEMPOK_POL. Note that this polarity inversion applies Interrupt register behaviour only; does affect direct GPIO output Temperature Sensor function. associated interrupt event masked enabled register TEMPOK_IRQ_ENA. Temperature status contained Register (R18) read time else response Interrupt event. Table more details Interrupt function. direct output Temperature status required external pins WM8959, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0101 selected GPIO Temperature status output GPIOn_PU selected GPIO Temperature status output GPIOn_PD selected GPIO Temperature status output
register fields used configure Temperature Sensor GPIO function described Table REGISTER ADDRESS (17h) LABEL TEMPOK_POL (rw) TEMPOK_IRQ_ DEFAULT DESCRIPTION Temperature Sensor polarity Non-inverted Inverted Temperature Sensor Enable disabled enabled
(16h)
Table Temperature Sensor GPIO Control
temperature sensor function operates according following truth table: LABEL Temperature Sensor output Temperature Sensor output VALUE DESCRIPTION Overheat temperature exceeded Overheat temperature exceeded
Table Truth Table GPIO Output Temperature Sensor Function
2008,
Pre-Production
WM8959
LOCK OUTPUT
internal signal used indicate lock status output GPIO used trigger Interrupt event. polarity Lock indication controlled register PLL_LCK_POL. Note that this polarity inversion applies Interrupt register behaviour only; does affect direct GPIO output Lock function. associated interrupt event masked enabled register PLL_LCK_IRQ_ENA. Lock status Register (R18) read time else response Interrupt event. Table more details Interrupt function. direct output Lock status required external pins WM8959, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0100 selected Lock status output GPIOn_PU selected Lock status output GPIOn_PD selected Lock status output
register fields used configure Lock GPIO function described Table REGISTER ADDRESS (17h) LABEL PLL_LCK_POL (rw) PLL_LCK_IRQ_ DEFAULT DESCRIPTION Lock polarity Non-inverted Inverted Lock Enable disabled enabled
(16h)
Table Lock GPIO Control
Lock function operates according following truth table: LABEL Lock output Lock output VALUE Locked DESCRIPTION Locked
Table Truth Table GPIO Output Lock function
LOGIC LOGIC OUTPUT
GPIO pins programmed drive logic high logic signal. following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0010 each Logic output GPIOn_SEL 0011 each Logic output GPIOn_PU each Logic Logic GPIO GPIOn_PD each Logic Logic GPIO
2008,
WM8959
INTERRUPT EVENT OUTPUT
interrupt generated following events described earlier: Button Control input GPIO1, GPIO3 GPIO5, GPI7 GPI8) MICBIAS current short circuit accessory detect Lock Temperature Sensor
Pre-Production
interrupt status flag asserted when un-masked Interrupt input asserted. OR'd combination un-masked Interrupt inputs. required, this flag inverted using IRQ_INV register bit. GPIO pins configured output signal. interrupt behaviour driven level detection (not edge detection) un-masked inputs. Therefore, input remains asserted after interrupt register been reset, then interrupt status flag will triggered again even though transition occurred. edge detection required (eg. confirming that input been de-asserted), then polarity inversion used after each event order detect each rising falling edge separately. This described further "GPIO Summary" section. status flag read back control interface. status each GPIO internal signals PLL_LCK, TEMPOK, MICSHRT MICDET also read back same way. register (R18) described Table status GPIO pins other Interrupt inputs read back read/write bits R18[11:0]. Interrupt inputs latched once set. Each input reset writing appropriate bit. cannot reset; OR'd combination other registers will reset only R18[11:0] direct output Interrupt signal required external pins WM8959, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0111 selected Interrupt (IRQ) output GPIOn_PU selected Interrupt (IRQ) output GPIOn_PD selected Interrupt (IRQ) output
2008,
Pre-Production register (R18) described Table REGISTER ADDRESS (12h) (ro) TEMPOK (rr) LABEL DEFAULT Read Only Read Reset
WM8959
Readback (Allows polling status) Temperature status Read0 Device temperature Device temperature Write Reset TEMPOK latch MICBIAS short status Read0 MICBIAS MICBIAS shorted Write1 Reset MICSHRT latch MICBIAS detect status MICBIAS microphone detect Readback Read0 Microphone detected Microphone detected Write1 Reset MICDET latch Lock status Read0 locked locked Write1 Reset PLL_LCK latch GPIO Input Status GPIO_STATUS[7] GPI8 status GPIO_STATUS[6] GPI7 status GPIO_STATUS[5] Reserved GPIO_STATUS[4] GPIO5 status GPIO_STATUS[3] GPIO4 status GPIO_STATUS[2] GPIO3 status GPIO_STATUS[1] Reserved GPIO_STATUS[0] GPIO1 status Invert output active high output active
MICSHRT (rr)
Read Reset
MICDET (rr)
Read Reset
PLL_LCK (rr)
Read Reset
GPIO_STATUS [7:0] (rr)
Read Reset
(17h) GPIO Control
IRQ_INV (rw)
Table GPIO Interrupt Status Readback
2008,
WM8959
SERIAL DATA OUTPUT (REGISTER READBACK)
Pre-Production
GPIO pins configured output serial data during register readback 3-wire (open-drain) 4-wire mode. readback mode configured using register bits RD_3W_ENA MODE_3W4W described Table Setting RD_3W_ENA enables 3-wire readback using SDIN open-drain mode. Setting RD_3W_ENA requires GPIO SDOUT. enable SDOUT GPIO pin, following register settings required: GPIO1_ENA (only required using GPIO1) AIF_SEL (only required using GPIO3, GPIO4 GPIO5) AIF_TRIS GPIOn_SEL 0110 selected SDOUT output GPIOn_PU selected SDOUT output GPIOn_PD selected SDOUT output
register fields used configure SDOUT GPIO pins described Table Refer "Control Interface" more details 3-wire 4-wire interfacing. REGISTER ADDRESS (16h) LABEL RD_3W_ENA DEFAULT DESCRIPTION 4-wire readback configuration 3-wire mode 4-wire mode, using GPIO 3-wire mode push open-drain 4-wire mode push wired-OR
MODE_3W4W
Table GPIO 3-Wire Readback Enable
2008,
Pre-Production
WM8959
GPIO SUMMARY
GPIO functions summarised Figure
Figure GPIO Control Diagram
2008,
WM8959
Pre-Production Details GPIO implementation shown below. order avoid GPIO loops GPIO configured output corresponding input disabled, shown Figure below.
Figure GPIO
GPIO register, i.e. latch structure, shown Figure below. de-bounce Control fields GPIOn_DEB_ENA determine whether signal de-bounced not. (Note that TOCLK (via SYSCLK) needs present order debounce circuit work.) polarity bits GPIO_POL[7:0] control whether interrupt triggered logic level (for GPIO_POL[n] logic level (for GPIO_POL[n] latch will cause interrupt stored until reset writing Interrupt Register. latched signal processed circuit, shown Figure above. interrupt
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