8-Bit, 350MSPS Analog-to-Digital Converter Kenet KAD2708L industr
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KAD2708L
8-Bit, 350MSPS Analog-to-Digital Converter
Kenet KAD2708L industry's lowest power, 8bit, high performance Analog-to-Digital converter. converter runs sampling rates 350MSPS, fabricated with Kenet's proprietary FemtoCharge® CMOS technology. Users obtain industry-leading SFDR specifications while nearly halving power consumption. Sampling rates 275, 210, 105MSPS also available same pin-compatible package versions with 10-bit resolution. available 68-pin RoHS-compliant packages with exposed paddle. Performance specified over full industrial temperature range (-40 +85°C).
Specifications
48.8dB Nyquist SFDR 64dBc Nyquist Power consumption 320mW 350MSPS
Features
On-chip reference Internal track hold 1.5VPP differential input voltage 600MHz analog input bandwidth Two's complement binary output Over-range indicator Selectable Clock Input LVDS compatible outputs Resolution, Speed Bits 350MSPS Bits 275MSPS Bits 275MSPS Bits 210MSPS Bits 210MSPS Bits 170MSPS Bits 170MSPS Bits 105MSPS Bits 105MSPS LVDS Outputs KAD2708L-35 KAD2710L-27 KAD2708L-27 KAD2710L-21 KAD2708L-21 KAD2710L-17 KAD2708L-17 KAD2710L-10 KAD2708L-10 KAD2710C-27 KAD2708C-27 KAD2710C-21 KAD2708C-21 KAD2710C-17 KAD2708C-17 KAD2710C-10 KAD2708C-10 LVCMOS Outputs
Applications
High-Performance Data Acquisition Portable Oscilloscope Medical Imaging Cable Head Ends Power-Amplifier Linearization Radar Satellite Antenna Array Processing Broadband Communications Local Multipoint Distribution System (LMDS) Communications Test Equipment
Table Pin-Compatible Products
Unicorn Park Dr., Woburn, 01801 Sales: 1-781-497-0060 FemtoCharge registered trademark Kenet, Inc.
Sales@kenetinc.com Copyright 2007, Kenet, Inc. Page
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Absolute Maximum Ratings1
Parameter AVDD2 AVSS AVDD3 AVSS OVDD2 OVSS Analog Inputs AVSS Clock Inputs AVSS Logic Inputs AVSS (VREFSEL, CLKDIV) Logic Inputs OVSS (RST, 2SC) VREF AVSS Analog Output Currents Logic Output Currents LVDS Output Currents Operating Temperature Storage Temperature Junction Temperature -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 AVDD3 AVDD2 AVDD3 OVDD2 AVDD3 Unit
Exposing device levels excess maximum ratings cause permanent damage. Operation maximum conditions extended periods affect device reliability.
Thermal Impedance
Parameter Junction Paddle2 Paddle soldered ground plane. Symbol Unit °C/W
Electrostatic charge accumulates humans, tools equipment, discharge through metallic package contacts (pins, balls, exposed paddle, etc.) integrated circuit. Industry-standard protection techniques have been utilized design this product. However, reasonable care must taken storage handling sensitive products. Contact Kenet specific sensitivity rating this product.
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Electrical Specifications
specifications apply under following conditions unless otherwise noted: AVDD2 1.8V, AVDD3 3.3V, OVDD 1.8V. -40°C +85°C, values 25°C. fSAMPLE 350MSPS, Nyquist.
Specifications
Parameter Power Requirements 1.8V Analog Supply Voltage 3.3V Analog Supply Voltage 1.8V Output Supply Voltage 1.8V Analog Supply Current 3.3V Analog Supply Current 1.8V Output Supply Current Power Dissipation AVDD2 AVDD3 OVDD IAVDD2 IAVDD3 IOVDD 3.15 3.45 Symbol Conditions Units
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Analog Specifications
Parameter Analog Input Full-Scale Differential Analog Input Voltage Gain Temperature Coefficient Full Power Bandwidth Clock Input Sampling Clock Frequency Range CLKP, CLKN Differential Input Voltage CLKP, CLKN Differential Input Resistance CLKP, CLKN Common-Mode Input Voltage Reference Internal Reference Voltage Reference Voltage Temperature Coefficient Common-Mode Output Voltage VREF VRTC Full Temp 1.18 1.21 0.86 1.24 ppm/°C fSAMPLE VCDI RCDI VCCI AVTC FPBW Full Temp Symbol Conditions Units
Specifications
Parameter Signal Noise Ratio Signal Noise Distortion Effective Number Bits Spurious Free Dynamic Range Two-Tone SFDR Integral Nonlinearity Differential Nonlinearity Power Supply Rejection Ratio Word Error Rate Symbol SINAD ENOB SFDR 2TSFDR PSRR Conditions Full Temp Full Temp Full Temp Full Temp f1=133MHz, f2=135MHz -0.8 -0.3 45.8 45.7 48.8 48.7 ±0.2 ±0.2 1x10-12 Units Bits
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Digital Specifications
Parameter Inputs High Input Voltage (VREFSEL) Input Voltage (VREFSEL) Input Current High (VREFSEL) Input Current (VREFSEL) High Input Voltage (CLKDIV) Input Voltage (CLKDIV) Input Current High (CLKDIV) Input Current (CLKDIV) High Input Voltage (RST,2SC) Input Voltage (RST,2SC) Input Current High (RST,2SC) Input Current (RST,2SC) Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time 1.15 VREFSEL VREFSEL VREFSEL VREFSEL CLKDIV CLKDIV CLKDIV CLKDIV RST,2SC RST,2SC RST,2SC RST,2SC OVDD OVSS AVDD3 AVSS 0.8*OVDD2 0.2*OVDD2 AVDD3 AVSS 0.8*AVDD3 0.2*AVDD3 0.8*AVDD3 0.2*AVDD3 Symbol Conditions Units
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Timing Diagram
Figure LVDS Timing Diagram
Timing Specifications
Parameter Aperture Delay Aperture Jitter Input Clock Data Propagation Delay Input Clock Output Clock Propagation Delay Output Clock Data Propagation Delay Output Data Output Clock Setup Time Output Clock Output Data Hold Time Latency (Pipeline Delay) Over Voltage Recovery Symbol tCPD tOVR Units cycles cycle
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Descriptions
11-13, 29-36, 64-66 Exposed Paddle AVSS
Name
AVDD2 AVSS VREF VREFSEL AVDD3 INP, CLKDIV CLKN, CLKP OVSS OVDD2 D0N, D1N, D2N, D3N, D4N, D5N, D6N, D7N, ORN,
Function
1.8V Analog Supply Analog Supply Return Reference Voltage Out/In Reference Voltage Select (0:Int 1:Ext) Common Mode Voltage Output 3.3V Analog Supply Analog Input Positive, Negative Connect Clock Divide (Active Low) Clock Input Complement, True Output Supply Return 1.8V LVDS Supply Power Reset (Active Low) LVDS (LSB) Output Complement, True LVDS Output Complement, True LVDS Output Complement, True LVDS Output Complement, True LVDS Output Complement, True LVDS Output Complement, True LVDS Output Complement, True LVDS Output Complement, True Over Range Complement, True Connect OVDD2 Two's Complement Select (Active Low) Analog Supply Return
CLKOUTN, CLKOUTP LVDS Clock Output Complement, True
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Configuration
OVDD2
OVDD2
OVDD2
OVDD2
OVSS
AVDD2 AVSS VREF VREFSEL AVDD3 AVSS AVSS AVDD2 AVDD3 AVDD3 CLKDIV
View Scale
OVSS OVDD2 CLKOUTP CLKOUTN OVDD2
KAD2708L
CLKP
AVSS
AVSS
AVSS
OVSS
CLKN
AVDD2
AVDD2
AVDD3
Figure Configuration
OVDD2
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Typical Operating Characteristics
AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25°C, fSAMPLE=350MHz, VIN= 6.865MHz -0.5dBFS unless noted.
SFDR (dB)
(dB)
Analog Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure
HD2, (mW)
Figure SFDR
SAMPLE (MHz)
Input Amplitude (dBFS)
Figure HD2,
Figure Power Dissipation fSAMPLE
49.5 (dB)
48.5 SAMPLE (MHz) SAMPLE (MHz)
Figure fSAMPLE
Figure HD2, fSAMPLE Page
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25°C, fSAMPLE=350MHz, VIN= 6.865MHz -0.5dBFS unless noted.
SFDR (dBc) SAMPLE (MHz)
0.25
(LSBs)
-0.25
-0.5
code
Figure SFDR fSAMPLE
(LSBs) -0.1 -0.2
Code Counts
Figure Differential Nonlinearity Output Code
40,000 35,000 30,000 25,000 20,000 15,000 10,000
-0.3 -0.4 -0.5 code
5,000
Code
Figure Integral Nonlinearity Output Code
Amplitude (dB) -100 Frequency (MHz) -0.50dBFS -48.4dB SFDR 64.5dBc mplitude (dB) SINAD 48.2dB -81dBc -66dBc -100
Figure Noise Histogram
-0.49dBFS 48.1dB SFDR 67.5dBc SINAD 48.1dB -78dBc -71dBc
Frequency (MHz)
Figure Output Spectrum 6.865MHz
Figure Output Spectrum 68.465MHz Page
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
AVDD3 3.3V, AVDD2 OVDD2 =1.8V, TAMBIENT (TA)= 25°C, fSAMPLE 350MHz unless noted.
Amplitude (dB) -100 Frequency (MHz) -0.52dBFS 47.7dB SFDR 68.2dBc
Amplitude (dB) -100 Frequency (MHz) -0.50dBFS 48dB SFDR 65.8dBc SINAD 47.9dB -73dBc -67.1dBc
SINAD 47.6dB -81dBc -69dBc
Figure Output Spectrum 174.905MHz
Amplitude (dB) -100 Frequency (MHz) 0.50dBFS 48.0dB SFDR 65.8dBc SINAD 46.8dB -73dBc -67.1dBc
Figure Output Spectrum 175.105MHz
Figure Output Spectrum 492.965MHz
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Functional KAD2708 based upon eight bit, 350MSPS converter pipelined architecture. input voltage captured sample hold circuit converted unit charge. Proprietary charge domain techniques used compare input series reference charges. These comparisons determine digital code each input value. converter pipeline requires sample clocks produce result. Digital error correction also applied, resulting total latency clock cycles. This evident user latency between start conversion data being available digital outputs. start-up, self-calibration performed minimize gain offset errors. reset (RST) initially held internally power-up will remain that state until calibration complete. clock frequency should remain fixed during this time. Calibration accuracy maintained sample rate which performed, therefore should repeated clock frequency changed more than 10%. Recalibration initiated pin, power cycling, time. system. Additionally, externally provided reference changed from nominal value adjust full-scale input voltage within limited range. select whether full-scale reference internally generated externally provided, digital input port VREFSEL should appropriately, internal high external. This also internal pull-up resistor. internally generated reference VREFSEL tied directly AVSS, external reference VREFSEL allowed float.
Analog Input
fully differential input (INP/INN) connects sample hold circuit. ideal full-scale input voltage 1.5VPP, centered voltage 0.86V shown Figure
Reset
KAD2708L resets calibrates automatically power-up. force reset initiate recalibration after power-up, connect open-drain output device drive (RST) pull least sample clock periods. device with pull-up reset pin, prevent KAD2708 from properly executing power-on reset.
Figure Analog Input Range Best performance obtained when analog inputs driven differentially ac-coupled configuration. common mode output voltage, VCM, should used properly bias each input shown Figures transformer will give best noise distortion performance wideband and/or high intermediate frequency (IF) inputs. recommended biasing shown Figure
Voltage Reference
VREF full-scale reference, which sets full-scale input voltage chip requires bypass capacitor 0.1uF larger. internally generated reference voltage provided from bandgap voltage buffer. This buffer sink source 50µA externally. external voltage applied this provide more accurate reference than internally generated bandgap voltage match full-scale reference among system KAD2708L chips. option latter configuration KAD2708L's internally generated reference external reference voltage other chips
Figure Transformer Input Page
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
value termination resistor should determined based desired impedance. differential input impedance KAD2708 10M. differential amplifier used applications that require coupling, expense reduced dynamic performance. this configuration amplifier will typically reduce achievable distortion performance. typical differential amplifier configuration shown Figure rate, then KAD2708L's divide-by-2 generate 50%-duty-cycle clock. divider only uses rising edge clock, clock duty cycle assured CLKDIV
AVSS AVDD
Divide Ratio
Table CLKDIV Settings
Jitter
sampled data system, clock jitter directly impacts achievable performance. theoretical relationship between clock jitter maximum shown Equation illustrated Figure
Figure Differential Amplifier Input
Where uncertainty sampling instant.
Clock Input
clock input circuit differential pair (see Figure 24). Driving these inputs with high level 1.8VPP each input) sine square wave will provide lowest jitter performance. recommended drive circuit shown Figure clock inputs driven single-ended, this recommended performance will suffer.
Equation This relationship shows that would achieved clock jitter were only non-ideal factor. reality, achievable limited internal factors such linearity (DNL), aperture jitter thermal noise.
tj=0.1ps Bits
tj=100ps tj=10ps
tj=1ps
Bits
Bits
Figure Recommended Clock drive CLKDIV 1.8V CMOS control (input) that selects whether input clock frequency passed directly divided two. Applying level left floating) will divide two; pulling CLKDIV 1.8V will divide. clock divider optional. KAD2708L's requires clock with duty cycle optimum performance. such clock available, option generate twice desired sampling
1000
Input Frequency
Figure Clock Jitter internal aperture jitter combines with input clock jitter, root-sum-square fashion since they statistically correlated, this determines total jitter system. total jitter, combined with other noise sources, then determines achievable SNR. Page
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Equivalent Circuits Layout Considerations
Split Ground Power Planes
Data converters operating high sampling frequencies require extra care board layout. Many complex board designs benefit from isolating analog digital sections. Analog supply ground planes should laid under signal clock inputs. Locate digital planes under outputs logic pins. Grounds should joined under chip. Figure Analog Inputs
Clock Input Considerations
matched transmission lines inputs analog input clock signals. Locate transformers, drivers terminations close chip possible.
Bypass Filtering
Bulk capacitors should have equivalent series resistance. Tantalum good choice. best performance, keep ceramic bypass capacitors very close device pins. Longer traces will increase inductance, resulting diminished dynamic performance accuracy. Make sure that connections ground direct impedance. Avoid forming ground loops.
LVDS Outputs
Figure Clock Inputs
OVDD OVDD DATA DATA D[7:0]P OVDD
Output traces connections must designed (100 differential) characteristic impedance. Keep traces direct, minimize bends where possible. Avoid crossing ground power plane breaks with signal traces.
Unused Inputs
Three four standard logic inputs (RESET, CLKDIV, 2SC) which will operated require connection best performance. These inputs left open they used. VREFSEL must held internal reference, left open external reference.
D[7:0]N
DATA
DATA
Figure LVDS Outputs
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Definitions
Analog Input Bandwidth analog input frequency which spectral output power fundamental frequency determined analysis) reduced from full-scale low-frequency value. This also referred Full Power Bandwidth. Aperture Delay Sampling Delay time required after rise clock input sampling switch open, which time signal held conversion. Aperture Jitter variation aperture delay samples. Clock Duty Cycle ratio time clock wave logic high total time clock period. Differential Non-Linearity (DNL) deviation code width from ideal step. Effective Number Bits (ENOB) alternate method specifying Signal Noise-and-Distortion Ratio (SINAD). calculated ENOB (SINAD-1.76) 6.02. Integral Non-Linearity (INL) deviation each individual code from line drawn from negative fullscale (1/2 below first code transition) through positive full-scale (1/2 above last code transition). deviation given code from this line measured from center that code. Least Significant (LSB) that smallest value weight digital word. value terms input voltage VFS/(2N-1) where resolution bits. Missing Codes output codes that skipped will never appear output. These codes cannot reached with input value. Most Significant (MSB) that largest value weight. value terms input voltage VFS/2. Pipeline Delay number clock cycles between initiation conversion appearance output pins corresponding data. Power Supply Rejection Ratio (PSRR) ratio change power supply voltage input voltage necessary negate resultant change output code. Signal Noise-and-Distortion (SINAD) ratio signal amplitude value Page other spectral components below half clock frequency, including harmonics excluding Signal-to-Noise Ratio (without Harmonics) ratio signal amplitude other spectral components below one-half sampling frequency, excluding harmonics Spurious-Free-Dynamic Range (SFDR) ratio signal amplitude value peak spurious spectral component. peak spurious spectral component harmonic. Two-Tone SFDR ratio value either input tone value peak spurious component. peak spurious component product.
KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Outline Dimensions
D1/2
0.80 E1/2
VIEW
TERMINAL
SECTION "C-C" SCALE: NONE
D2/2 0.45
16Xe REF.
E2/2
0.25 0.25 SEATING PLANE 16Xe REF. BOTTOM VIEW
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KAD2708L 8-Bit, 350MSPS Analog-to-Digital Converter
Package Dimensions (mm)
0.42 7.55 0.50 7.55 0.00 0.18 0.90 0.01 0.23 10.00 9.75 7.70 0.50 10.00 9.75 7.70 0.60 0.60 7.85 0.65 Total terminals Terminals direction Terminals direction 7.85 1.00 0.05 0.30 JEDEC MO-220 Measured between 0.20 0.25mm from plated terminal Note
Ordering Guide
RoHS stances (RoHS). Contact Kenet materials declaration this product.
This product compliant with directive 2002/95/EC regarding Restriction Hazardous Sub-
Model
KAD2708L-35Q68 KAD2708L-27Q68 KAD2708L-21Q68 KAD2708L-17Q68 KAD2708L-10Q68
Speed
350MSPS 275MSPS 210MSPS 170MSPS 105MSPS
Package
68-QFN 68-QFN 68-QFN 68-QFN 68-QFN
Temp. Range
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
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