High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMITM) 24-MHz System Clock (48-MHz Pipeline) Independent 16/32-Bit Instruction Open Architecture With Third-Party Support Built-In Debug Module Integrated Memory 288K-Byte Program Flash Banks With Contiguous Sectors 16K-Byte Static (SRAM) Memory Security Module (MSM) JTAG Security Module Operating Features Low-Power Modes: STANDBY HALT Industrial/Automotive Temperature Ranges 470+ System Module 32-Bit Address Space Decoding Supervision Memory/Peripherals Digital Watchdog (DWD) Timer Analog Watchdog (AWD) Timer Enhanced Real-Time Interrupt (RTI) Interrupt Expansion Module (IEM) System Integrity Failure Detection Breaker Direct Memory Access (DMA) Controller Control Packets Channels Frequency-Modulated Zero-Pin Phase-Locked Loop (FMZPLL)-Based Clock Module With Prescaler Multiply-by-8 Internal FMZPLL Option ZPLL Bypass Mode Communication Interfaces: Serial Peripheral Interfaces (SPIs) Programmable Baud Rates Serial Communication Interfaces (SCIs) Selectable Baud Rates Asynchronous/Isosynchronous Modes Standard Controllers (SCC) 16-Mailbox Capacity Fully Compliant With Protocol, Version 2.0B Class Serial Interface (C2SIb) Normal 10.4 Kbps Mode 41.6 Kbps
Three Inter-Integrated Circuit (I2C) Modules Multi-Master Slave Interfaces Kbps (Fast Mode) 10-Bit Address Capability High-End Timer Lite (HET) Programmable Channels: High-Resolution Pins High-Resolution Share Feature (XOR) High-End Timer 64-Instruction Capacity External Clock Prescale (ECP) Module Programmable Low-Frequency External Clock (CLK) 12-Channel 10-Bit Multi-Buffered (MibADC) 64-Word FIFO Buffer Single- Continuous-Conversion Modes 1.55 Minimum Sample/Conversion Time Calibration Mode Self-Test Features Flexible Interrupt Handling Expansion Module (EBM) (PGE only) Supports 16-Bit Expansion Memory Interface Mappings Expansion Pins Dedicated General-Purpose (GIO) Pins Additional Peripheral I/Os (PGE) Dedicated General-Purpose (GIO) Pins Additional Peripheral I/Os (PZ) Sixteen External Interrupts Compatible Device (Planned) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) 100-Pin Plastic Low-Profile Quad Flatpack Suffix) Development System Support Tools Available Code Composer StudioIntegrated Development Environment (IDE) Assembler Simulator Real-Time In-Circuit Emulation Flash Programming
Please aware that important notice concerning availability, standard warranty, critical applications TexasInstruments semiconductor products disclaimers thereto appears this data sheet. Code Composer Studio trademark Texas Instruments. ARM7TDMI trademark Advanced RISC Machines Limited (ARM). trademarks property their respective owners. test-access port compatible with IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port Boundary Scan Architecture specification. Boundary scan supported this device.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice. POST OFFICE 1443
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PRODUCT PREVIEW
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
TMS470R1VF288 144-PIN PACKAGE (TOP VIEW) (without Expansion Bus)
ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADEVT GIOF[7] GIOF[6] GIOA[5]/INT[5] PLLDIS GIOF[5] I2C2SCL I2C2SDA GIOF[4] GIOF[3] GIOF[2] I2C1SCL I2C1SDA VCCIO VSSIO CAN1STX CAN1SRX GIOF[1] CLKOUT GIOF[0] GIOA[7]/INT[7] GIOA[6]/INT[6] GIOE[7] HET[0]
ADREFHI ADREFLO VCCAD VSSAD ADIN[4]
ADIN[3]
ADIN[2] ADIN[1] ADIN[0] PORRST GIOC[4] GIOC[3] TEST GIOH[5]/INT[13] GIOC[2] GIOA[4]/INT[4] GIOC[1] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] GIOC[0] GIOA[0]/INT[1]/ECLK VCCIO VSSIO GIOH[0]/INT[8] GIOG[7] GIOA[0]/INT0 GIOG[6] GIOG[5] TRST
HET[1] HET[2] GIOE[6] VCCIO VSSIO GIOE[5] HET[3] HET[4] GIOE[4] HET[5] SPI2SCS GIOE[3] SPI2ENA SPI2SIMO GIOE[2] SPI2SOMI SPI2CLK CAN2STX CAN2SRX SCI2CLK SCI2RX SCI2TX SCI1CLK GIOE[1] SCI1RX SCI1TX GIOE[0] GIOB[0] GIOD[0] GIOH[1]/INT[9] GIOH[2]/INT[10] GIOD[1] GIOH[3]/INT[11] GIOH[4]/INT[12]
PRODUCT PREVIEW
SPI1SCS SPI1ENA GIOG[4] SPI1CLK SPI1SIMO GIOG[3] SPI1SOMI GIOG[2] HET[6] GIOG[1] HET[7] HET[8] HET[18] TMS2 HET[20] HET[22] GIOG[0] C2SILPN C2SIRX GIOD[5] C2SITX VCCIO VSSIO GIOD[4] I2C3SCL I2C3SDA GIOD[3] OSCOUT OSCIN GIOD[2]
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
TMS470R1VF288 144-PIN PACKAGE (TOP VIEW) (with Expansion Bus)
ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADEVT EBDAAR[13]/EBDATA[15] EBADDR[12]/EBDATA[14] GIOA[5]/INT[5] PLLDIS EBADDR[11]/EBDATA[13] I2C2SCL I2C2SDA EBADDR[10]/EBDATA[12] EBADDR[9]/EBDATA[11] EBADDR[8]/EBDATA[10] I2C1SCL I2C1SDA VCCIO VSSIO CAN1STX CAN1SRX EBADDR[7]/EBDATA[9] CLKOUT EBADDR[6]/EBDATA[8] GIOA[7]/INT[7] GIOA[6]/INT[6] EBDATA[7] HET[0]
EBADDR[22]/EBADDR[14] EBADDR[21]/EBADDR[13]
EBADDR[23]/EBADDR[15] EBADDR[24]/EBADDR[16]
GIOA[0]/INT[0]
EBADDR[20]/EBADDR[12] EBADDR[19]/EBADDR[11]
EBADDR[1]
EBADDR[25]/EBADDR[17] EBADDR[26]/EBADDR[18]
TRST
SPI1SCS SPI1ENA EBADDR[18]/EBADDR[10] SPI1CLK SPI1SIMO EBADDR[17]/EBADDR[9] SPI1SOMI EBADDR[16]/EBADDR[8] HET[6] EBADDR[15]/EBADDR[7] HET[7] HET[8] HET[18] TMS2 HET[20] HET[22] EBADDR[14]/EBADDR[6] C2SILPN C2SIRX EBADDR[5] C2SITX VCCIO VSSIO EBADDR[4] I2C3SCL I2C3SDA EBADDR[3] OSCOUT OSCIN EBADDR[2]
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ADREFHI ADREFLO VCCAD VSSAD ADIN[4] ADIN[3] ADIN[2] ADIN[1] ADIN[0] PORRST EBCS[6] EBCS[5] TEST EBHOLD EBWR[1] GIOA[4]/INT[4] EBWR[0] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] EBOE GIOA[0]/INT1/ECLK VCCIO VSSIO
HET[1] HET[2] EBDATA[6] VCCIO VSSIO EBDATA[5] HET[3] HET[4] EBDATA[4] HET[5] SPI2SCS EBDATA[3] SPI2ENA SPI2SIMO EBDATA[2] SPI2SOMI SPI2CLK CAN2STX CAN2SRX SCI2CLK SCI2RX SCI2TX SCI1CLK EBDATA[1] SCI1RX SCI1TX EBDATA[0] DMAREQ[0] EBADDR[0]
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
TMS470R1VF288 100-PIN PACKAGE (TOP VIEW)
GIOA[5]/INT[5]
GIOA[6]/INT[6]
GIOA[7]/INT[7]
I2C2SDA
CAN1SRX
CAN1STX
I2C1SDA
I2C2SCL
ADIN[10]
I2C1SCL
ADIN[11]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
PLLDIS
ADEVT
CLKOUT
HET[0]
ADREFHI ADREFLO VCCAD VSSAD ADIN[4] ADIN[3] ADIN[2] ADIN[1] ADIN[0] PORRST TEST GIOH[5]/INT[13] GIOA[4]/INT[4] VCCP FLTP2 GIOA[3]/INT[3] GIOA[2]/INT[2] GIOA[1]/INT[1]/ECLK VCCIO VSSIO GIOA[0]/INT[0] TRST
HET[1] HET[2] VCCIO VSSIO HET[3] HET[4] HET[5] SPI2SCS SPI2ENA SPI2SIMO SPI2SOMI SPI2CLK CAN2STX CAN2SRX SCI2CLK SCI2RX SCI2TX SCI1CLK SCI1RX SCI1TX GIOB[0] GIOH[1]/INT[9] GIOH[2]/INT[10] GIOH[3]/INT[11] GIOH[4]/INT[12]
PRODUCT PREVIEW
I2C3SDA
HET[20]
HET[6]
HET[7]
HET[8]
VCCIO
VSSIO
HET[22]
HET[18]
OSCOUT
C2SILPN
SPI1CKL
SPI1SCS
C2SIRX
SPI1SOMI
SPI1SIMO
C2SITX
SPI1ENA
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I2C3SCL
OSCIN
TMS2
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
description
TMS470R1VF288(1) devices members Texas Instruments TMS470R1x family generalpurpose16/32-bit reduced instruction computer (RISC) microcontrollers. VF288 microcontroller offers high performance utilizing high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting high instruction throughput while maintaining greater code efficiency. ARM7TDMI 16/32-bit RISC views memory linear collection bytes numbered upwards from zero. TMS470R1VF288 utilizes big-endian format where most significant byte word stored lowest numbered byte least significant byte highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining costs. VF288 RISC core architecture offers solutions these performance cost demands while maintaining power consumption. VF288 devices contain following: ARM7TDMI 16/32-Bit RISC TMS470R1x system module (SYS) with 470+ enhancements 288K-byte flash 16K-byte SRAM Frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module Digital watchdog (DWD) timer Analog watchdog (AWD) timer Enhanced real-time interrupt (RTI) module Interrupt expansion module (IEM) Memory security module (MSM) JTAG security module serial peripheral interface (SPI) modules serial communications interface (SCI) modules standard controllers (SCC) Three inter-integrated circuit (I2C) modules Class Serial Interface (C2SIb) module 10-bit multi-buffered analog-to-digital converter (MibADC), with input channels High-end timer lite (HET) controlling I/Os External Clock Prescale (ECP) Expansion Module (EBM) pins (PGE only), only) functions performed 470+ system module (SYS) include: Address decoding Memory protection Memory peripherals supervision Reset abort exception management Prioritization internal interrupt sources Device clock control Parallel signature analysis (PSA) enhanced real-time interrupt (RTI) module VF288 option driven oscillator clock. digital watchdog (DWD) 25-bit resettable decrementing counter that provides system reset when watchdog counter expires. This data sheet includes device-specific information such memory peripheral select assignment, interrupt priority, device memory map. more detailed functional description module, TMS470R1x System Module Reference Guide (literature number SPNU189).
Throughout remainder this document, TMS470R1VF288 shall referred either full device name VF288.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
description (continued)
VF288 memory includes general-purpose SRAM supporting single-cycle read/write accesses byte, half-word, word modes. flash memory this device nonvolatile, electrically erasable programmable memory implemented with 32-bit-wide data interface.The flash operates with system clock frequency MHz. When pipeline mode, flash operates with system clock frequency MHz. more detailed information flash, flash section this data sheet TMS470R1x Flash Reference Guide (literature number SPNU213). memory security module (MSM) JTAG security module prevent unauthorized access visibility on-chip memory, thereby preventing reverse engineering manipulation proprietary code. more information, TMS470R1x Memory Security Module Reference Guide (literature number SPNU246) TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245). VF288 device communication interfaces: SPIs, SCIs, SCCs, C2SI, three I2Cs. provides convenient method serial interaction high-speed communications between similar shift-register type devices. full-duplex, serial interface intended asynchronous communication between other peripherals using standard non-return-to-zero (NRZ) format. uses serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates megabit second (Mbps). ideal applications operating noisy harsh environments (e.g., automotive industrial fields) that require reliable serial communication multiplexed wiring. C2SIb allows VF68x transmit receive messages class network following Standard J1850 Class Data Communication Network Interface standard. module multi-master communication module providing interface between VF288 microcontroller I2Ccompatible device serial bus. supports both Kbps Kbps speeds. more detailed functional information SPI, SCI, peripherals, specific reference guides (literature numbers SPNU195, SPNU196, SPNU197). more detailed functional information I2C, TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). more detailed functional information C2SI, TMS470R1x Class Serial Interface (C2SIb) Reference Guide (literature number SPNU214). advanced intelligent timer that provides sophisticated timing functions real-time applications. timer software-controlled, using reduced instruction set, with specialized timer micromachine attached port. used compare, capture, general-purpose I/O. especially well suited applications requiring multiple sensor information drive actuators with complex accurate time pulses. used this device high-end timer lite. fewer I/Os than usual standard HET. more detailed functional information HET, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). VF288 peripheral contains XOR-share feature. This feature allows adjacent high- resolution channels XORed together, making possible output smaller pulses than standard HET. more detailed information XOR-share feature, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). VF288 device 10-bit-resolution, sample-and-hold MibADC. Each MibADC channels converted individually grouped software sequential conversion sequences. There three separate groupings, which triggered external event. Each sequence converted once when triggered configured continuous conversion mode. more detailed functional information MibADC, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
description (continued)
frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module contains phase-locked loop, clock-monitor circuit, clock-enable circuit, prescaler (with prescale values 1-8). function FMZPLL multiply external frequency reference higher frequency internal use. FMZPLL provides ACLK system (SYS) module. module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), clock (MCLK), peripheral interface clock (ICLK) other VF288 device modules. more detailed functional information FMZPLL, TMS470R1x FrequencyModulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221). NOTE ACLK should confused with MibADC internal clock, ADCLK. ACLK continuous system clock from external resonator/crystal reference. expansion module (EBM) standalone module that supports multiplexing functions expansion interface. more information EBM, TMS470R1x Expansion Module (EBM) Reference Guide (literature number SPNU222).
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VF288 device also external clock prescaler (ECP) module that when enabled, outputs continuous external clock (ECLK) specified pin. ECLK frequency user-programmable ratio peripheral interface clock (ICLK) frequency. more detailed functional information ECP, TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
device characteristics
VF288 device derivative system emulation device SE470R1VB8AD. Table identifies characteristics VF288 device except SYSTEM CPU, which generic. Table Device Characteristics
CHARACTERISTICS DEVICE DESCRIPTION TMS470R1VF288 MEMORY number memory selects this device, TMS470VF288 Memory Selection Assignment table (Table Pipeline/Non-Pipeline Flash pipeline-capable INTERNAL MEMORY 288K-Byte Flash 16K-Byte SRAM Memory Security Module (MSM) JTAG Security Module VF288 implemented array selected memory-select signals (see TMS470R1VF288 Memory Selection Assignment table, Table COMMENTS VF288
PERIPHERALS device-specific interrupt priority configurations, Interrupt Priority Table (Table peripheral address ranges their peripheral selects, VF288 Peripherals, System Module, Flash Base Addresses table (Table
PRODUCT PREVIEW
CLOCK Expansion
FMZPLL
Frequency-modulated zero-pin external loop filter pins. Expansion module with pins. Supports 16-bit memories. Table details. package, Port eight external pins, Port only external pin, Port five external pins, Port external pins, Ports each have eight external pins, Port external pins. package, Port eight external pins, Port only external pin, Port five external pins.
GENERAL-PURPOSE I/Os
(PGE Suffix) Suffix)
(HECC and/or SCC) (5-pin, 4-pin 3-pin) C2SIb
(3-pin) (5-pin) high-resolution (HR) SHARE feature allows even-numbered pins share next higher odd-numbered structures. This sharing independent whether available externally. available externally shared, then only used general-purpose I/O. more information SHARE, theTMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). standard controllers
with Share
MibADC CORE VOLTAGE VOLTAGE PINS PACKAGES
64-Instruction Capacity 10-bit, 12-channel 64-word FIFO Both logic registers full 16-channel MibADC present.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
functional block diagram
External Pins VCCP FLTP2 FLASH (288K Bytes) Banks Sectors Memory Security Module (MSM) External Pins OSCIN (16K Bytes) FMZPLL OSCOUT PLLDIS Crystal
ADIN[11:0] Address/Data TMS470R1x Breaker MibADC 64-Word FIFO ADEVT ADREFHI ADREFLO VCCAD VSSAD Words Expansion Address/Data [0:8;18,20,22]
TRST TMS2 TEST PORRST CLKOUT
TMS470R1x SYSTEM MODULE with Enhanced Module(A)
SCC1
CAN1RX CAN2TX CAN2RX SCI1CLK SCI1 SCI1TX SCI1RX SCI2CLK SCI2 SCI2TX SCI2RX
Controller Channels
Interrupt Expansion Module (IEM)
SCC2
Digital Watchdog (DWD)
Analog Watchdog (AWD)
HECC I2C3
I2C3SDA I2C3SCL I2C2SDA I2C2SCL
I2C2 C2SI SPI2 SPI1 GIO/EBM(B) I2C1
I2C1SDA I2C1SCL
C2SITX C2SIRX C2SILPN SPI2SCS SPI2ENA SPI2SIMO SPI2SOMI SPI2CLK SPI1SCS SPI1ENA SPI1SIMO SPI1SOMI SPI1CLK
GIOA[1]/INT[1]/ECLK
Enhanced module System Module with extra bits disable FMZPLL while STANDBY mode. GIOC[4:0], GIOD[5:0], GIOE[5:0], GIOF[7:0], GIOH[0], which muxed with EBM, available package. Table mapping.
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GIOA[0]/INT[0] GIOA[7:2]/INT[7:2] GIOB[0] GIOC[4:0](B) GIOD[5:0](B) GIOE[7:0](B) GIOF[7:0](B) GIOG[7:0](B) GIOH[5:0/INT[13:8](B)
PRODUCT PREVIEW
CAN1TX
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Terminal Functions
TERMINAL NAME INPUT VOLTAGE(1)(2) OUTPUT CURRENT(1)(2) INTERNAL PULLUP/ PULLDOWN(3) DESCRIPTION
HIGH-END TIMER (HET) HET[0] HET[1] HET[2] HET[3] HET[4] HET[5] HET[6] HET[7] HET[8] HET[18] HET[20] HET[22] STANDARD CONTROLLER (SCC) CAN1SRX CAN1STX CAN2SRX CAN2STX C2SIbLPN C2SIbRX C2SIbTX GIOA[0]/INT[0] GIOA[1]/INT[1]/ ECLK GIOA[2]/INT[2] GIOA[3]/INT[3] GIOA[4]/INT[4] GIOA[5]/INT[5] GIOA[6]/INT[6] GIOA[7]/INT[7] GIOB[0]/ EBDMAREQ[0] GIOC[0]/EBOE GIOC[1]/EBWR[0] GIOC[2]/EBWR[1] GIOC[3]/EBCS[5] GIOC[4]/EBCS[6] Table 3.3-V GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. tolerant General-purpose input/output pins. GIOA[7:0]/INT[7:0] interrupt-capable pins. GIOA[1]/INT[1]/ECLK multiplexed with external clockout function external clock prescale (ECP) module. tolerant 3.3-V tolerant 3.3-V 3.3-V tolerant 3.3-V SCC1 receive SCC1 transmit SCC2 receive transmit C2SIb module loopback enable C2SIb module receive data input C2SIb module transmit data output 3.3-V high-resolution (HR) SHARE feature allows even pins share next higher structures. This sharing independent whether available externally. available externally shared, then only used general-purpose I/O. more information SHARE, TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). Timer input capture output compare. HET[8:0,18,20,22] applicable pins programmed general-purpose input/ output (GIO) pins. high-resolution pins.
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CLASS SERIAL INTERFACE (C2SIB)
GENERAL-PURPOSE (GIO)
power, ground, reference voltage, connect pins, except RST, configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL NAME INPUT VOLTAGE(1)(2) OUTPUT CURRENT(1)(2) INTERNAL PULLUP/ PULLDOWN(3) DESCRIPTION
GENERAL-PURPOSE (GIO) (CONTINUED) GIOD[0]/EBADDR[0] GIOD[1]/EBADDR[1] GIOD[2]/EBADDR[2] GIOD[3]/EBADDR[3] GIOD[4]/EBADDR[4] GIOD[5]/EBADDR[5] GIOE[0]/EBDATA[0] GIOE[1]/EBDATA[1] GIOE[2]/EBDATA[2] GIOE[3]/EBDATA[3] GIOE[4]/EBDATA[4] GIOE[5]/EBDATA[5] GIOE[6]/EBDATA[6] GIOE[7]/EBDATA[7] GIOF[0]/EBADDR[6]/ EBDATA[8] GIOF[1]/EBADDR[7]/ EBDATA[9] GIOF[2]/EBADDR[8]/ EBDATA[10] GIOF[3]/EBADDR[9]/ EBDATA[11] GIOF[4]/EBADDR[10]/ EBDATA[12] GIOF[5]/EBADDR[11]/ EBDATA[13] GIOF[6]/EBADDR[12]/ EBDATA[14] GIOF[7]/EBADDR[13]/ EBDATA[15] GIOG[0]/EBADDR[14]/ EBADDR[6] GIOG[1]/EBADDR[15]/ EBADDR[7] GIOG[2]/EBADDR[16]/ EBADDR[8] GIOG[3]/EBADDR[17]/ EBADDR[9] GIOG[4]/EBADDR[18]/ EBADDR[10] GIOG[5]/EBADDR[19]/ EBADDR[11] GIOG[6]/EBADDR[20]/ EBADDR[12] 3.3-V GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. Table
GIOG[7]/EBADDR[21]/ EBADDR[13] power, ground, reference voltage, connect pins, except RST, configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL NAME INPUT VOLTAGE(1)(2) OUTPUT CURRENT(1)(2) INTERNAL PULLUP/ PULLDOWN(3) DESCRIPTION
GENERAL-PURPOSE (GIO) (CONTINUED) GIOH[0]/EBADDR[22]/ EBADDR[14]/INT[8] GIOH[1]/EBADDR[23]/ EBADDR[15]/INT[9] GIOH[2]/EBADDR[24]/ EBADDR[16]/INT[10] GIOH[3]/EBADDR[25]/ EBADDR[17]/INT[11] GIOH[4]/EBADDR[26]/ EBADDR[18]/INT[12] GIOH[5]/EBHOLD/INT[13] ADEVT MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) tolerant SPI1SIMO SPI1SOMI 3.3-V 3.3-V MibADC module high-voltage reference input MibADC module low-voltage reference input MibADC analog supply voltage MibADC analog ground reference SPI1 clock. SPI1CLK programmed pin. SPI1 chip enable. programmed pin. SPI1 slave chip select. programmed pin. SPI1 data stream. Slave in/master out. programmed pin. SPI1 data stream. Slave out/master programmed pin. SERIAL PERIPHERAL INTERFACE (SPI2) SPI2CLK SPI2ENA SPI2SCS tolerant SPI2 clock. programmed pin. SPI2 chip enable. programmed pin. SPI2 slave chip select. programmed pin. 3.3-V MibADC analog input pins 3.3-V MibADC event input. programmed pin. ADIN[0] ADIN[1] ADIN[2] ADIN[3] ADIN[4] ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADREFHI ADREFLO VCCAD VSSAD SPI1CLK SPI1ENA SPI1SCS GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], GIOH[5:0] multiplexed with expansion module. GIOH[5:0]/INT[13:8] interrupt-capable pins.
3.3-V
PRODUCT PREVIEW
SERIAL PERIPHERAL INTERFACE (SPI1)
power, ground, reference voltage, connect pins, except RST, configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL NAME INPUT VOLTAGE(1)(2) OUTPUT CURRENT(1)(2) INTERNAL PULLUP/ PULLDOWN(3) DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI2) (CONTINUED) SPI2SIMO SPI2SOMI I2C1SDA I2C1SCL I2C2SDA I2C2SCL I2C3SDA I2C3SCL OSCIN OSCOUT PLLDIS 3.3-V 1.8-V tolerant tolerant SPI2 data stream. Slave in/master out. programmed pin. SPI2 data stream. Slave out/master programmed pin. INTER-INTEGRATED CIRCUIT (I2C) I2C1 serial data I2C1 serial clock I2C2 serial data I2C2 serial clock I2C3 serial data I2C3 serial clock FREQUENCY-MODULATED ZERO-PIN PHASE-LOCKED LOOP (FMZPLL) Crystal connection external clock input External crystal connection Enable/disable FMZPLL. FMZPLL bypassed oscillator becomes system clock. SCI1 clock. SCI1CLK programmed pin. SCI1 data receive. SCI1RX programmed pin. SCI1 data transmit. SCI1TX programmed pin. SCI2 clock. SCI2CLK programmed pin. SCI2 data receive. SCI2RX programmed pin. SCI2 data transmit. SCI2TX programmed pin. SYSTEM MODULE (SYS) CLKOUT PORRST 3.3-V 3.3-V Bidirectional pin. CLKOUT programmed output SYSCLK, ICLK, MCLK. Input master chip power-up reset. External monitor circuitry must assert power-on reset. Bidirectional reset. internal circuitry assert reset, external system reset assert device reset. this pin, output buffer implemented open drain (drives only). ensure external reset arbitrarily generated, recommends that external pullup resistor connected this pin. Analog watchdog reset. provides system reset written time system, providing external network circuit connected. user using AWD, recommends that this connected ground pulled down ground external resistor. more details external network circuit, TMS470R1x System Module Reference Guide (literature number SPNU189) application note Analog Watchdog Resistor, Capacitor Discharge Interval Selection Constraints (literature number SPNA005). power, ground, reference voltage, connect pins, except RST, configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
SERIAL COMMUNICATIONS INTERFACE (SCI1) SCI1CLK SCI1RX SCI1TX SCI2CLK SCI2RX SCI2TX 3.3-V tolerant 3.3-V 3.3-V tolerant 3.3-V
SERIAL COMMUNICATIONS INTERFACE (SCI2)
3.3-V
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
3.3-V
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Terminal Functions (Continued)
TERMINAL NAME INPUT VOLTAGE(1)(2) OUTPUT CURRENT(1)(2) INTERNAL PULLUP/ PULLDOWN(3) TEST/DEBUG (T/D) Test clock. controls test hardware (JTAG). Test data inputs serial data test instruction register, test data register, programmable test address (JTAG). DESCRIPTION
Test data out. outputs serial data from test instruction register, test data register, identification register, programmable test address (JTAG). Test enable. Reserved internal only. recommends that this connected ground pulled down ground external resistor. Serial input controlling state test access port (TAP) controller (JTAG). Serial input controlling second TAP. recommends that this connected VCCIO pulled VCCIO external resistor.
TEST TMS2
3.3-V
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TRST
Test hardware reset TAP1 TAP2. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic. recommends that this pulled down ground external resistor. FLASH Flash test proper operation, this must connected connect (NC)]. Flash external pump voltage (3.3 SUPPLY VOLTAGE CORE (1.8
FLTP2 VCCP
3.3-V 1.8-V
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL (3.3 SUPPLY GROUND CORE VSSIO SUPPLY GROUND DIGITAL Digital supply ground reference Core supply ground reference 3.3-V Digital supply voltage
VCCIO
power, ground, reference voltage, connect pins, except RST, configured inputs while PORRST immediately after PORRST goes high. internal pulldown, internal pullup (all internal pullups pulldowns active input pins, independent PORRST state.)
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
VF288 DEVICE-SPECIFIC INFORMATION memory
Figure shows memory VF288 device.
Memory Bytes) 0xFFFF_FFFF System Module Control Registers (512K Bytes) 0xFFF8_0000 0xFFF7_FFFF Peripheral Control Registers (512K Bytes) 0xFFF0_0000 0xFFEF_FFFF 0xFFE8_C000 0xFFE8_BFFF 0xFFE8_8000 0xFFE8_7FFF 0xFFE8_4021 0xFFE8_4020 0xFFE8_4000 Reserved Flash Control Registers Reserved Control Registers Reserved MByte) 0xFFE0_0000 SYSTEM with PSA, CIM, RTI, DEC, DMA, MMC, Reserved Reserved Reserved SPI1 Reserved SCI2 SCI1 Reserved MibADC Reserved HECC HECC SCC2 SCC1 Reserved 0x7FFF_FFFF SCC2 Reserved SCC1 Reserved I2C3 I2C2 Program Data Area I2C1 Reserved FLASH (288K Bytes) Banks SPI2 Reserved C2SIb Reserved Byte) 0x0000_0024 0x0000_0023 0x0000_0000 Exception, Interrupt, Reset Vectors Reserved Reserved Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0xFFF7_C800 0xFFF0_0000 0x0000_0023 0x0000_0020 0x0000_001C 0x0000_0018 0x0000_0014 0x0000_0010 0x0000_000C 0x0000_0008 0x0000_0004 0xFFF7_D400 0xFFF7_DA00 0xFFF7_D900 0xFFF7_D800 0xFFFF_FFFF 0xFFFF_FD00 0xFFFF_FC00 0xFFFF_F700 0xFFF8_0000
0xFFF7_FC00 0xFFF7_F800 0xFFF7_F500 0xFFF7_F400 0xFFF7_F000 0xFFF7_EF00 0xFFF7_ED00 0xFFF7_EC00 0xFFF7_E200 0xFFF7_E000 0xFFF7_DE00 0xFFF7_DC00
(16K Bytes)
0x0000_0000 Memory addresses configurable system (SYS) module within range 0x0000_0000 0xFFE0_0000. registers part memory map.
Figure TMS470R1VF288 Memory
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
memory selects
Memory selects allow user address memory arrays (i.e., flash, RAM, RAM) user-defined addresses. Each memory select (low high) memory base address registers (MFBAHRx MFBALRx) that, together, define array's starting (base) address, size, protection. base address each memory select configurable memory address boundary that multiple decoded block size. decoded block size flash memory this device 0x00200000. more information control configure these memory select registers, structure memory sections TMS470R1x System Module Reference Guide (literature number SPNU189). memory selection assignments memory selected, Table Table TMS470R1VF288 Memory Selection Assignment
MEMORY SELECT (fine) (fine) (fine) (fine) (fine) (coarse) (coarse) MEMORY SELECTED (ALL INTERNAL) FLASH/ROM FLASH/ROM CS[5]/GIOC[3] CS[6]/GIOC[4] MEMORY SIZE(1) 288K 16K(2) 128MB (x8) (x16) 128MB (x8) (x16) MEMORY BASE ADDRESS REGISTER MFBAHR0 MFBALR0 MFBAHR1 MFBALR1 MFBAHR2 MFBALR2 MFBAHR3 MFBALR3 MFBAHR4 MFBALR4 MCBAHR2 MCBALR2 MCBAHR3 MCBALR3 SMCR1 SMCR5 SMCR6 STATIC REGISTER
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refers size memory 8-bits; refers size memory 16-bits. starting addresses both memory-select signals cannot offset from each other multiple user-defined block size memory-base address register.
JTAG security module VF288 device includes JTAG security module provide maximum security memory contents. visible unlock code chosen sector first bank user-programmable memory. VF288, visible unlock code sector address 0x0000_01F8. memory security module VF288 device also includes memory security module (MSM) provide additional security flexibility memory contents' protection. password unlocking located four words just before flash protection keys (see page 17). VF288 device contains 16K-bytes internal static configurable module addressed within range 0x0000_0000 0xFFE0_0000. This VF288 implemented array selected memory-select signals. This VF288 configuration imposes additional constraint memory RAM; starting addresses both memory selects cannot offset from each other multiples size physical (i.e., VF288 device). VF288 addressed through memory selects protected memory protection unit (MPU) portion module, allowing user finer blocks memory protection than allowed memory selects. ideal protecting operating system while allowing access current task. more detailed information portion module memory protection, memory section TMS470R1x System Module Reference Guide (literature number SPNU189).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Flash flash memory nonvolatile electrically erasable programmable memory implemented with 32-bit-wide data interface. flash external state machine programming erase functions. flash read flash program erase sections following. flash protection keys VF288 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/ compaction operations from occurring until after four protection keys have been matched loading correct user keys into FMPKEY control register. protection keys VF288 located last words first sector. more detailed information flash protection keys FMPKEY control register, Optional Quadruple Protection Keys Programming Protection Keys portions TMS470R1x Flash Reference Guide (literature number SPNU213). flash read VF288 flash memory configurable module addressed within range 0x0000_0000 0xFFE0_0000. Flash addressed through memory selects NOTE flash external pump voltage (VCCP) required operations (program, erase, read). flash pipeline mode When pipeline mode, flash operates with system clock frequency (versus system clock frequency normal mode). Flash pipeline mode capable accessing 64-bit words provides 32-bit pipelined words CPU. Also, pipeline mode Flash read with wait states when memory addresses contiguous (after initial 2-wait-state reads). NOTE After system reset, pipeline mode disabled (ENPIPE [FMREGOPT.0] "0"). other words, VF288 device powers comes reset non-pipeline mode. Furthermore, setting Flash configuration mode (GBLCTRL.4) will override pipeline mode.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
flash program erase VF288 device Flash contains 32K-byte memory array bank) 256K-byte bank, total 288K-bytes Flash, consists eight sectors. These eight sectors sized follows:
SECTOR SEGMENT Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes ADDRESS 0x0000_0000 0x0000_0000 0x0000_2000 0x0000_4000 0x0000_6000 0x0004_0000 0x0005_0000 0x0006_0000 0x0007_0000 HIGH ADDRESS 0x0000_07FF 0x0000_1FFF 0x0000_3FFF 0x0000_5FFF 0x0000_7FFF 0x0004_FFFF 0x0005_FFFF 0x0006_FFFF 0x0007_FFFF BANK1 (256K Bytes) BANK0 (32K Bytes) MEMORY ARRAYS BANKS)
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minimum size erase operation sector. maximum size program operation 16-bit word. NOTE flash external pump voltage (VCCP) required operations (program, erase, read). Execution occur from bank while programming/erasing sectors another bank. However, execution occur from sector within bank that being programmed erased. NOTE When sector enabled, rest flash memory disabled. memory only read programmed from code executed RAM. more detailed information Flash program erase operations, TMS470R1x Flash Reference Guide (literature number SPNU213). VF288 device contains RAM. 64-instruction capability. configurable module addressed within range 0x0000_0000 0xFFE0_0000. addressed through memory select
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
peripheral selects base addresses
VF288 device uses sixteen peripheral selects decode base addresses peripherals. These peripheral selects fixed transparent user since they part decoding scheme used module. Control registers peripherals, module, flash begin base addresses shown Table Table VF288 Peripherals, System Module, Flash Base Addresses
CONNECTING MODULE SYSTEM RESERVED RESERVED RESERVED RESERVED BUFFER RESERVED RESERVED RESERVED SPI1 RESERVED SCI2 SCI1 RESERVED MibADC RESERVED ADDRESS RANGE BASE ADDRESS 0xFFFF_FFCC 0xFFFF_FF70 0xFFFF_FF60 0xFFFF_FF40 0xFFFF_FF20 0xFFFF_FF00 0xFFFF_FE80 0xFFFF_FE00 0xFFFF_FD80 0xFFFF_FD00 0xFFFF_FC00 0xFFFF_FB00 0xFFFF_FA00 0xFFFF_F800 0xFFFF_F700 0xFFF8_0000 0xFFF7_FD00 0xFFF7_FC00 0xFFF7_F900 0xFFF7_F800 0xFFF7_F600 0XFFF7_F500 0xFFF7_F400 0xFFF7_F100 0xFFF7_F000 0xFFF7_EF00 0xFFF7_EE00 0xFFF7_ED00 0xFFF7_EC00 ENDING ADDRESS 0xFFFF_FFFF 0xFFFF_FFCB 0xFFFF_FF6F 0xFFFF_FF5F 0xFFFF_FF3F 0xFFFF_FF1F 0xFFFF_FEFF 0xFFFF_FE7F 0xFFFF_FDFF 0xFFFF_FD7F 0xFFFF_FCFF 0xFFFF_FBFF 0xFFFF_FAFF 0xFFFF_F9FF 0xFFFF_F7FF 0xFFFF_F6FF 0xFFF7_FFFF 0xFFF7_FCFF 0xFFF7_FBFF 0xFFF7_F8FF 0xFFF7_F7FF 0XFFF7_F5FF 0xFFF7_F4FF 0xFFF7_F3FF 0xFFF7_F0FF 0xFFF7_EFFF 0xFFF7_EEFF 0xFFF7_EDFF 0xFFF7_ECFF PS[4] PS[3] PS[2] PERIPHERAL SELECTS PS[0] PS[1]
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
Table VF288 Peripherals, System Module, Flash Base Addresses (Continued)
CONNECTING MODULE HECC RESERVED HECC RESERVED RESERVED SCC2 RESERVED SCC1 RESERVED SCC2 RESERVED SCC1 RESERVED I2C3 I2C2 I2C1 RESERVED SPI2 RESERVED RESERVED C2SIb RESERVED RESERVED Flash Control Registers RESERVED CONTROL REGISTERS RESERVED ADDRESS RANGE BASE ADDRESS 0xFFF7_EA00 0xFFF7_E800 0xFFF7_E600 0xFFF7_E400 0xFFF7_E300 0xFFF7_E200 0xFFF7_E100 0xFFF7_E000 0xFFF7_DF00 0xFFF7_DE00 0xFFF7_DD00 0xFFF7_DC00 0xFFF7_DB00 0xFFF7_DA00 0xFFF7_D900 0xFFF7_D800 0xFFF7_D500 0xFFF7_D400 0xFFF7_CC00 0xFFF7_C900 0xFFF7_C800 0xFFF7_C000 0xFFF0_0000 0xFFE8_8000 0xFFF8_4024 0xFFE8_4000 0xFFF8_0000 ENDING ADDRESS 0xFFF7_EBFF 0xFFF7_E9FF 0xFFF7_E7FF 0xFFF7_E5FF 0xFFF7_E3FF 0xFFF7_E2FF 0xFFF7_E1FF 0xFFF7_E0FF 0xFFF7_DFFF 0xFFF7_DEFF 0xFFF7_DDFF 0xFFF7_DCFF 0xFFF7_DBFF 0xFFF7_DAFF 0xFFF7_D9FF 0xFFF7_D8FF 0xFFF7_D7FF 0xFFF7_D4FF 0xFFF7_D3FF 0xFFF7_CBFF 0xFFF7_C8FF 0xFFF7_C7FF 0xFFF7_BFFF 0xFFE8_BFFF 0xFFF8_7FFF 0xFFE8_4023 0xFFF8_3FFF PS[10] PS[11] PS[12] PS[13] PS[14] PS[15] PS[9] PS[8] PS[7] PERIPHERAL SELECTS PS[5] PS[6]
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
direct-memory access (DMA)
direct-memory access (DMA) controller transfers data from specified location VF288 memory (except restricted memory locations like system control registers area). manages channels, supports data transfer both on-chip off-chip memories peripherals. controller connected both peripheral busses, enabling these data transfers occur parallel with activity thus maximizing overall system performance. Although controller possible configurations, VF288 device, controller configuration control packets channels. VF288 request hardwired configuration, Table Table Request Lines Connections(1)
MODULES SPI1 SPI1 MibADC/I2C1 MibADC/SCI1 MibADC/SCI1 I2C1 SPI2 SPI2 I2C2/C2SIb I2C2/C2SIb I2C3 I2C3 RESERVED SCI2 SCI2 SCI2 end-receive SCI2 end-transmit SCI2DMA0 SCI2DMA1 SPI1 end-receive SPI1 end-transmit EV/I2C1 read G1/SCI1 end-receive G2/SCI1 end-transmit I2C1 write SPI2 end-receive SPI2 end-transmit I2C2 read end-receive/C2SIb end-receive I2C3 read I2C3 write REQUEST INTERRUPT SOURCES Expansion request EBDMAREQ0 SPI1DMA0 SPI1DMA1 MibADCDMA0/I2C1DMA0 MibADCDMA1/SCI1DMA0 MibADCDMA2/SCI1DMA1 I2C1DMA1 SPI2DMA0 SPI2DMA1 I2C2DMA0/C2SIDMA0 I2C3DMA0 I2C3DMA1 CHANNEL DMAREQ[0] DMAREQ[1] DMAREQ[2] DMAREQ[3] DMAREQ[5] DMAREQ[6] DMAREQ[7] DMAREQ[8] DMAREQ[9] DMAREQ[10] DMAREQ[11] DMAREQ[12] DMAREQ[13] DMAREQ[14] DMAREQ[15] DMAREQ[4]
I2C2 write end-transmit/C2SIb end-transmit I2C2DMA1/C2SIDMA1
channels with more than assigned request source, only sources listed request generator given application. device software control ensure that there conflicts between requesting modules.
Each channel control packets attached allowing continuously load generate periodic interrupts that data read CPU. control packets allow interrupt enable, channels determine priority level interrupt. transfers occur modes: Non-request mode (used when transferring from memory memory) Request mode (used when transferring from memory peripheral) more detailed functional information controller, TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
interrupt priority (IEM CIM)
Interrupt requests originating from VF288 peripheral modules (i.e., SPI1 SPI2; SCI1 SCI2; RTI; etc.) assigned channels within 48-channel interrupt expansion module (IEM) where, programmable register mapping, these channels then mapped 32-channel central interrupt manager (CIM) portion module. Programming multiple interrupt sources same channel effectively shares channel between sources. request channels maskable that individual channels selectively disabled. interrupt requests programmed either type: Fast interrupt request (FIQ) Normal interrupt request (IRQ) prioritizes interrupts. precedences request channels decrease with ascending channel order [highest] [lowest] priority). IEM-to-CIM default mapping, channel priorities, their associated modules, Table
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Table Interrupt Priority (IEM CIM)
MODULES SPI1 SPI2 RESERVED I2C1 SCI1/SCI2 SCI1 C2SIb I2C2 SCC2 SCC1 RESERVED MibADC SCI2 I2C3 SCI1 System RESERVED SCC2 SCC1 interrupt SCC2 interrupt SCC1 interrupt MibADC event conversion SCI2 receive interrupt interrupt I2C3 interrupt SCI1 transmit interrupt interrupt (SSI) interrupt I2C1 interrupt SCI1 SCI2 error interrupt SCI1 receive interrupt C2SIb interrupt I2C2 interrupt SCC2 interrupt SCC1 interrupt INTERRUPT SOURCES SPI1 end-transfer/overrun COMP2 interrupt COMP1 interrupt interrupt SPI2 end-transfer/overrun interrupt DEFAULT INTERRUPT LEVEL/ CHANNEL CHANNEL
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interrupt priority (IEM CIM) (continued)
Table Interrupt Priority (IEM CIM) (Continued)
MODULES SCI2 MibADC MibADC RESERVED RESERVED HECC HECC RESERVED HECC interrupt HECC interrupt INTERRUPT SOURCES SCI2 transmit interrupt MibADC Group conversion Interrupt interrupt MibADC Group conversion DEFAULT INTERRUPT LEVEL/ CHANNEL CHANNEL 32-37 40-47
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more detailed functional information IEM, TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). more detailed functional information CIM, TMS470R1x System Module Reference Guide (literature number SPNU189).
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
expansion module (EBM)
expansion module (EBM) standalone module used bond both general-purpose input/output pins expansion interface pins. This module supports multiplexing functions expansion interface functions. module also supports expansion memory interface mappings, well mapping following expansion signals: 27-bit address (EBADDR[26:0]) 19-bit address (EBADDR[18:0]) 16-bit data (EBDATA[7:0] EBDATA[15:0]) write strobes (EBWR[1:0]) memory chip selects (EBCS[6:5]) output enable (EBOE) external hold signal interfacing slow memories (EBHOLD) request line (EBDMAREQ[0]) Table shows multiplexing signals with expansion interface signals. mapping these pins varies depending memory mode.
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Table Expansion Mapping(1)
GIOB[0] GIOC[0] GIOC[2:1] GIOC[4:3] GIOD[5:0] GIOE[7:0] GIOF[7:0] GIOG[7:0] GIOH[4:0] GIOH[5] EXPANSION MODULE PINS(2) EBDMAREQ[0] EBOE EBWR[1:0] EBCS[6:5] EBADDR[5:0] EBDATA[7:0] EBADDR[13:6] EBADDR[21:14] EBADDR[26:22] EBHOLD EBDMAREQ[0] EBOE EBWR[1:0] EBCS[6:5] EBADDR[5:0] EBDATA[7:0] EBDATA[15:8] EBADDR[13:6] EBADDR[18:14] EBHOLD
These mappings controlled control registers (EBMXCRB EBMXCRH) control register (EBMCR1). GPIO functions, GIODIRx, GIODINx, GIODOUTx, GIODSETx, GIODCLRx. more detailed information, TMS470R1x General-Purpose Input/Output (GIO) Reference Guide (literature number SPNU192) TMS470R1x Expansion Module (EBM) Reference Guide (literature number SPNU222). refers size memory 8-bits; refers size memory 16-bits.
Table lists names expansion interface signals their functions. Table Expansion Pins
EBDMAREQ EBOE EBWR EBCS EBADDR EBDATA EBHOLD DESCRIPTION
Expansion request Expansion enable Expansion write strobe. EBWR[1] controls EBDATA[15:8] EBWR[0] controls EBDATA[7:0] Expansion chip select Expansion address Expansion data Expansion hold. external device assert this signal wait states expansion transaction.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
MibADC
multi-buffered analog-to-digital converter (MibADC) accepts analog signal converts signal 10-bit digital value. VF288 MibADC module function modes: compatibility mode, where programmer's model compatible with TMS470R1x module digital results stored digital result registers; buffered mode, where digital result registers replaced with three FIFO buffers, each conversion group [event, group1 (G1), group2 (G2)]. buffered mode, MibADC buffers serviced interrupts DMA. MibADC event trigger enhancements MibADC includes major enhancements over event-triggering capability TMS470R1x ADC. Both group event group configured event-triggered operation, providing event-triggered groups. trigger source polarity selected individually both group event group from options identified Table Table MibADC Event Hookup Configuration
EVENT EVENT1 EVENT2 EVENT3 EVENT4 SOURCE SELECT BITS EVENT (G1SRC[1:0] EVSRC[1:0]) SIGNAL NAME ADEVT HET18 Reserved Reserved
group these event-triggered selections configured group source select bits (G1SRC[1:0]) event source register (ADEVTSRC.[5:4]). event group, these event-triggered selections configured event group source select bits (EVSRC[1:0]) event source register (ADEVTSRC.[1:0]). more detailed functional information MibADC, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
JTAG interface
There main test access ports (TAPs) VF748C device: TMS470R1x Device factory test Some JTAG pins shared among these TAPs. hookup illustrated Figure
TSM470R1x
TRST
TRST
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Factory TEST
TRST TMS2
Figure JTAG Interface
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
development system support
Texas Instruments provides extensive hardware software development support tools TMS470R1x family. These support tools include: Code Composer StudioIntegrated Development Environment (IDE) Fully integrated suite software development tools Includes Compiler/Assembler/Linker, Debugger, Simulator Supports Real-Time analysis, data visualization, open Supports high-level language programming Full implementation standard ANSI language Powerful optimizer that improves code-execution speed reduces code size Extensive run-time support library included TMS470R1x control registers easily accessible from program Interfaces functions assembly functions easily Establishes comprehensive, easy-to-use tool development high-performance microcontroller applications C/C++ Provides extensive macro capability Allows high-speed operation Allows extensive control assembly process using assembler directives Automatically resolves memory references assembly modules combined Provides capability simulate operation without emulation hardware Allows inspection modifications memory locations Allows debugging programs assembly language Allows high-speed JTAG communication TMS470R1x emulator target board
Optimizing compiler
TMS470R1x Simulator
emulation communication kits more information pricing availability, contact nearest field sales office authorized distributor.
Code Composer Studio trademark Texas Instruments.
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Assembly language tools (assembler linker)
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
documentation support
Extensive documentation supports TMS470 microcontroller family generation devices. types documentation available include: data sheets with design specifications; complete user's guides devices development support tools; hardware software applications. Useful reference documentation includes: User's Guides TMS470R1x 32-Bit RISC Microcontroller Family User's Guide (literature number SPNU134) TMS470R1x C/C++ Compiler User's Guide (literature number SPNU151) TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117) TMS470R1x Source Debugger User's Guide (literature number SPNU124) TMS470R1x Assembly Language Tools User's Guide (literature number SPNU118) TMS470R1x System Module Reference Guide (literature number SPNU189) TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194) TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195) TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196) TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197) TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199) TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202) TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206) TMS470R1x Flash Reference Guide (literature number SPNU213) TMS470R1x Class Serial Interface (C2SIb) Reference Guide (literature number SPNU214) TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221) TMS470R1x Expansion Module (EBM) Reference Guide (literature number SPNU222) TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
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Application Reports: Analog Watchdog Resistor, Capacitor Discharge Interval Selection Constraints (literature number SPNA005) F05/C05 Power Reset Power Sequencing Requirements (literature number SPNA009)
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
device numbering conventions
Figure illustrates numbering symbol nomenclature TMS470R1x family.
Prefix: Standard Prefix Fully Qualified Devices Family: TMS470 RISC-Embedded Microcontroller Family 1.8-V Core Voltage Program Memory Types: Masked Flash ROM-less System Emulator Development Tools
Type: Device Type:
Program Memory Size
on-chip program memory
128K Bytes 128K Bytes Bytes Bytes Operating Free-Air Temperature Ranges: -40°C 85°C -40°C 105°C -40°C 125°C
Package: 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) 100-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure TMS470R1x Family Nomenclature
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ARM7TDMI Devices Containing Following Modules: FMZPLL Clock 16K-Byte Static 1K-Byte Instructions) Digital Watchdog (DWD) Interrupt Expansion Module (IEM) Memory Security Module (MSM) High-End Lite (HET) Real-Time Interrupt (RTI) 10-Bit, 12-Input Multi-buffered Analog-to-Digital Converter (MibADC) Serial Peripheral Interface (SPI) Modules Serial Communications Interface (SCI) Modules Three Inter-Integrated Circuit (I2C) Modules Class Serial Interface (C2SIb) Module Standard Controller Area Network (CAN) [SCC] External Clock Prescaler (ECP)
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
device identification code register
device identification code register identifies silicon version, technology family (TF), flash device, assigned device-specific part number (see Table VF288 device identification code register value 0x095F. Table TMS470 Device Allocation Register
FFFF_FFF0
Reserved
VERSION LEGEND: bits 3-15: bits 0-2:
PART NUMBER
Read only, Value constant after RESET Read only, Value after RESET
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Transmission Request Reset Register (CANTRR) Field Descriptions
31-16 15-12 Name Value Description
Reserved VERSION
Reads undefined writes have effect. Silicon version (revision) bits These bits identify silicon version device. Technology family This distinguishes technology family core power supply: F10/C10 devices F05/C05 devices ROM/Flash This distinguishes between Flash devices:
Flash device device Device-specific part number bits These bits identify assigned device-specific part number. assigned device-specific part number VF288 device 0101011. Bits tied high default.
PART NUMBER
Mandatory High
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
device part numbers
Table lists available TMS470R1VF288 devices. Table Device Part Number
DEVICE PART NUMBER TMS470R1VF288PGEA TMS470R1VF288PGEQ TMS470R1VF288PZA TMS470R1VF288PZQ TMS470R1VF288PGEAR TMS470R1VF288PGEQR TMS470R1VF288PZAR TMS470R1VF288PZQR PROGRAM MEMORY FLASH EEPROM PACKAGE TYPE 100-PIN LQFP 144-PIN LQFP TEMPERATURE RANGES -40°C 85°C -40°C 105°C -40°C 125°C
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
DEVICE ELECTRICAL SPECIFICATIONS TIMING PARAMETERS absolute maximum ratings over operating free-air temperature range(1)
Supply voltage ranges: -0.3 Supply voltage ranges: VCCIO VCCAD VCCP (flash pump)(2) -0.3 Input voltage range: tolerant input pins -0.3 other input pins. -0.3 Input clamp current: tolerant pins, PORRST, TRST, TEST -20mA(3) ADIN[0:11] VCCAD) .±10 other pins VCCIO) Operating free-air temperature ranges, version. -40°C 85°C version -40°C 125°C Operating junction temperature range, -40°C 150°C Storage temperature range, Tstg -40°C 150°C
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Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect their associated grounds. These pins have internal clamp diode positive supply voltage.
device recommended operating conditions(4)
VCCIO VCCAD VCCP VSSAD Digital logic supply voltage (Core) Digital logic supply voltage (I/O) supply voltage Flash pump supply voltage Digital logic supply ground supply ground version Operating free-air temperature version Operating junction temperature 1.71 2.05 UNIT
voltages with respect VSS, except VCCAD, which with respect VSSAD.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature range(1)
PARAMETER Vhys Input hysteresis Low-level input voltage High-level input voltage Input threshold voltage Low-level output voltage(4) High-level output voltage(4) Input clamp current (I/O pins)(5) Pulldown Pulldown Input current (3.3 input pins) Pullup Pullup other pins inputs(2) TEST CONDITIONS 0.15 1.35 VSSIO VCCIO VCCIO VCCIO pullup pulldown Input current tolerant input pins) VCCIO CLKOUT, AWD, TDI, TDO, TMS, TMS2 Low-level output current other tolerant CLKOUT, TDI, TDO, TMS, TMS2 High-level output current other tolerant
UNIT
VCCIO VCCIO
inputs only(3)
VCCIO VCCIO
Source currents (out device) negative while sink currents (into device) positive. This does apply PORRST pin. PORRST exceptions, PORRST timings section page These values help determine external network circuit. more details, TMS470R1x System Module Reference Guide (literature number SPNU189). linear with respect amount load current (IOL/IOH) applied. Parameter does apply input-only output-only pins. Some buffers this device zero-dominant buffers, indicated Output Current column Terminal Functions table. these buffers shorted together outputting level other outputting high level, resulting value will always low. Flash banks/pumps sleep mode. halt mode linear between 85C. pins configured inputs outputs with load. pulldown inputs pullup inputs VCCIO
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
electrical characteristics over recommended operating free-air temperature range(1) (continued)
PARAMETER digital supply current (operating mode) TEST CONDITIONS SYSCLK MHz, 2.05 SYSCLK MHz, 2.05 version (85°C) OSCIN MHz, 2.05 version (125°C) OSCIN MHz, 2.05 30°C, 2.05 digital supply current (halt mode)
(7)(8)
1.25
UNIT
digital supply current (standby mode)(7)
version (85°C), 2.05 version (125°C), 2.05 load, VCCIO V(9) load, VCCIO load, VCCIO
VCCIO digital supply current (operating mode) ICCIO VCCIO digital supply current (standby mode) VCCIO digital supply current (halt mode) VCCAD supply current (operating mode)
frequencies, VCCAD load, VCCAD VCCAD VCCP read operation VCCP program erase
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ICCAD
VCCAD supply current (standby mode) VCCAD supply current (halt mode)
ICCP
VCCP pump supply current
VCCP standby mode
operation(7)
VCCP halt mode operation(7) Input capacitance Output capacitance
Source currents (out device) negative while sink currents (into device) positive. This does apply PORRST pin. PORRST exceptions, PORRST timings section page These values help determine external network circuit. more details, TMS470R1x System Module Reference Guide (literature number SPNU189). linear with respect amount load current (IOL/IOH) applied. Parameter does apply input-only output-only pins. Some buffers this device zero-dominant buffers, indicated Output Current column Terminal Functions table. these buffers shorted together outputting level other outputting high level, resulting value will always low. Flash banks/pumps sleep mode. halt mode linear between 30°C 85°C. 9I/O pins configured inputs outputs with load. pulldown inputs pullup inputs VCCIO
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PARAMETER MEASUREMENT INFORMATION
Tester Electronics Output Under Test
VLOAD
Where: respective pin(A)
respective pin(A) VLOAD
Figure Test Load Circuit
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150-pF typical load-circuit capacitance(B) NOTES: these values, "electrical characteristics over recommended operating free-air temperature range" table. timing parameters measured using external load capacitance unless otherwise noted.
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
timing parameter symbology
Timing parameter symbols have been created accordance with JEDEC Standard 100. order shorten symbols, some names other related terminology have been abbreviated follows: ICLK OSC, OSCI OSCO Compaction, CMPCT CLKOUT Erase Interface clock Master mode OSCIN OSCOUT Program, PROG Ready Read margin RDMRGN0 Read margin RDMRGN1 SIMO SOMI Read Reset, SCInRX Slave mode SCInCLK SPInSIMO SPInSOMI SPInCLK System clock SCInTX
Lowercase subscripts their meanings are:
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access time cycle time (period) delay time fall time hold time
rise time setup time transition time valid time pulse duration (width)
following additional letters used with these meanings: High Valid Unknown, changing, don't care level High impedance
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external reference resonator/crystal oscillator clock option
oscillator enabled connecting appropriate fundamental 4-10 resonator/crystal load capacitors across external OSCIN OSCOUT pins shown Figure oscillator singlestage inverter held bias integrated bias resistor. This resistor disabled during leakage test measurement HALT mode. strongly encourages each customer submit samples device resonator/crystal vendors validation. vendors equipped determine what load capacitors will best tune their resonator/crystal microcontroller device optimum start-up operation over temperature/voltage extremes. external oscillator source used connecting clock signal OSCIN leaving OSCOUT unconnected (open) shown Figure
OSCIN
OSCOUT
OSCIN
OSCOUT
C1(A)
Crystal
C2(A)
values should provided resonator/crystal vendor.
Figure Crystal/Clock Connection
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External Clock Signal (toggling 0-1.8
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
FMZPLL clock specifications timing requirements FMZPLL circuits enabled disabled
f(OSC) tc(OSC) tw(OSCIL) tw(OSCIH) f(OSCRST) Input clock frequency Cycle time, OSCIN Pulse duration, OSCIN Pulse duration, OSCIN high FAIL frequency
UNIT
Causes device reset (specifically clock reset) setting FAIL (GLBCTRL.15) FAIL flag (GLBSTAT.1) bits equal more detailed information these bits device resets, TMS470R1x System Module Reference Guide (literature number SPNU189).
switching characteristics over recommended operating conditions clocks(1)(2)(3)
PARAMETER TEST CONDITIONS(3) Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled 20.8 41.6 41.6 41.6 41.6 UNIT
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f(SYS) f(CONFIG) f(ICLK) f(ECLK) tc(SYS) tc(CONFIG) tc(ICLK) tc(ECLK)
System clock frequency(4) System clock frequency Flash config mode Interface clock frequency External clock output frequency module Cycle time, system clock Cycle time, system clock flash config mode Cycle time, interface clock Cycle time, module external clock output
f(SYS) f(OSC) where {8}, {1,2,3,4,5,6,7,8} when PLLDIS system-clock divider determined CLKDIVPRE [2:0] bits global control register (GLBCTRL.[2:0]) multiplier determined MULT4 also GLBCTRL register (GLBCTRL.3). f(SYS) f(OSC) where {1,2,3,4,5,6,7,8} when PLLDIS f(ICLK) f(SYS) where interface clock divider ratio determined PCR0.[4:1] bits module. f(ECLK) f(ICLK) where 256}. prescale value defined ECPCTRL.[7:0] register bits module. Pipeline mode enabled disabled determined ENPIPE (FMREGOPT.0). Flash Vread must achieve maximum system clock frequency.
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FMZPLL clock specifications (continued) switching characteristics over recommended operating conditions external clocks (see Figure Figure 7)(1)(2)(3)
tw(COL) PARAMETER TEST CONDITIONS SYSCLK MCLK Pulse duration, CLKOUT
0.5tc(SYS) 0.5tc(ICLK)
UNIT
ICLK: even 1(5) ICLK: SYSCLK MCLK
1(5)
0.5tc(ICLK) 0.5tc(SYS) 0.5tc(SYS) 0.5tc(ICLK)
tw(COH)
Pulse duration, CLKOUT high ICLK: even 1(5) ICLK: 1(5)
0.5tc(ICLK) 0.5tc(SYS) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(SYS) 0.5tc(ECLK) 0.5tc(ECLK) 0.5tc(SYS) 0.5tc(ECLK)
even even tw(EOL) Pulse duration, ECLK even even even tw(EOH) Pulse duration, ECLK high even
interface clock divider ratio determined PCR0.[4:1] bits module. 256}. prescale value defined ECPCTRL.[7:0] register bits module. CLKOUT/ECLK pulse durations (low/high) function OSCIN pulse durations when PLLDIS active. Clock source bits selected either SYSCLK (CLKCNTL.[6:5] binary) MCLK (CLKCNTL.[6:5] binary). Clock source bits selected ICLK (CLKCNTL.[6:5] binary).
CLKOUT
Figure CLKOUT Timing Diagram
ECLK
Figure ECLK Timing Diagram
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PRODUCT PREVIEW
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
PORRST timings timing requirements PORRST (see Figure
VCCPORL VCCPORH VCCIOPORL VCCIOPORH VIL(PORRST) tsu(PORRST)r tsu(VCCIO)r th(PORRST)r tsu(PORRST)f th(PORRST)rio th(PORRST)d tsu(PORRST)fio tsu(VCCIO)f supply level when PORRST must active during power high supply level when PORRST must remain active during power become active during power down VCCIO supply level when PORRST must active during power VCCIO high supply level when PORRST must remain active during power become active during power down Low-level input voltage after VCCIO VCCIOPORH Low-level input voltage PORRST before VCCIO VCCIOPORL Setup time, PORRST active before VCCIO VCCIOPORL during power Setup time, VCCIO VCCIOPORL before VCCPORL Hold time, PORRST active after VCCPORH Setup time, PORRST active before VCCPORH during power down Hold time, PORRST active after VCCIO VCCIOPORH Hold time, PORRST active after VCCPORL Setup time, PORRST active before VCCIO VCCIOPORH during power down Setup time, VCCPORL before VCCIO VCCIOPORL 2.75 VCCIO UNIT
PRODUCT PREVIEW
VCCP/VCCIO
VCCIOPORH
VCCIO
VCCIOPORH VCCPORH VCCPORL VCCIOPORL
VCCPORH
VCCIOPORL VCCP/VCCIO PORRST
VCCPORL
VIL(PORRST)
VIL(PORRST)
Figure PORRST Timing Diagram
switching characteristics over recommended operating conditions RST(1)
PARAMETER tv(RST)
tfsu
4112tc(OSC) 8tc(SYS)
670tc(OSC)
UNIT
Valid time, active after PORRST inactive Valid time, active (all others)
Flash start time, from inactive fetch first instruction from Flash (Flash pump stabilization time)
Specified values include rise/fall times. rise fall timings, "switching characteristics output timings versus load capacitance" table.
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JTAG scan interface timing (JTAG clock specification 10-MHz 50-pF load output)
tc(JTAG) tsu(TDI/TMS TCKr) th(TCKr -TDI/TMS) th(TCKf -TDO) td(TCKf -TDO) Cycle time, JTAG high period Setup time, TDI, before rise (TCKr) Hold time, TDI, after TCKr Hold time, after TCKf Delay time, valid after fall (TCKf) UNIT
Figure JTAG Scan Timings
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
output timings switching characteristics output timings versus load capacitance (CL) (see Figure
PARAMETER Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2 Rise time, Fall time, Rise time,4mA, tolerant pins Fall time, 4mA, tolerant pins Rise time, other output pins Fall time, other output pins Output UNIT 12.5 12.5
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Figure CMOS-Level Outputs
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input timings timing requirements input timings(1) (see Figure
Input minimum pulse width tc(ICLK) UNIT
tc(ICLK) interface clock cycle time 1/f(ICLK) Input
Figure CMOS-Level Inputs
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
flash timings timing requirements program flash(1)(2)
tprog(16-bit) tprog(Total) terase(sector) twec
tfp(RST) tfp(SLEEP) tfp(STANDBY)
UNIT cycles
Half word (16-bit) programming time 288K-byte programming Sector erase time Write/erase cycles
Flash pump settling time from SLEEP Initial flash pump settling time from SLEEP STANDBY Initial flash pump settling time from STANDBY ACTIVE
time(3) 1000
10000
134tc(SYS) 134tc(SYS) 67tc(SYS)
more detailed information flash core sectors, flash program erase section this data sheet. Flash program/erase specified only temperature range 25°C 85°C version), 25°C 125°C version). 288K-byte programming time includes overhead state machine.
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SPIn master mode timing parameters SPIn master mode external timing parameters (CLOCK PHASE SPInCLK output, SPInSIMO output, SPInSOMI input)(1)(2)(3)(see Figure
2(5) 3(5) tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M td(SPCH-SIMO)M
Cycle time, SPInCLK
256tc(ICLK) 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M
UNIT
0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M
Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Delay time, SPInCLK high SPInSIMO valid (clock polarity Delay time, SPInCLK SPInSIMO valid (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Setup time, SPInSOMI before SPInCLK (clock polarity Setup time, SPInSOMI before SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity
td(SPCL-SIMO)M 5(5) tv(SPCL-SIMO)M tv(SPCH-SIMO)M tsu(SOMI-SPCL)M 6(5) tsu(SOMI-SPCH)M 7(5) tv(SPCL-SOMI)M tv(SPCH-SOMI)M
tc(SPC)M tc(SPC)M
MASTER (SPInCTRL2.3) CLOCK PHASE (SPInCTRL2.0) cleared. tc(ICLK) interface clock cycle time 1/f(ICLK) rise fall timings, "switching characteristics output timings versus load capacitance" table. When Master mode, following must true: values from 255:tc(SPC)M +1)tc(ICLK) where prescale value SPInCTL1.[12:5] register bits. values 0:tc(SPC)M 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2.1).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SPIn master mode timing parameters (continued)
SPInCLK (clock polarity SPInCLK (clock polarity SPInSIMO Master Data Valid
PRODUCT PREVIEW
SPInSOMI Master Data Must Valid
Figure SPIn Master Mode External Timing (CLOCK PHASE
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SPIn master mode timing parameters (continued) SPIn master mode external timing parameters (CLOCK PHASE SPInCLK output, SPInSIMO output, SPInSOMI input)(1)(2)(3) (see Figure
2(5) 3(5) tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M tv(SIMO-SPCH)M 4(5) v(SIMO-SPCH)M tv(SIMO-SPCL)M 5(5) 6(5) 7(5) tv(SPCH-SIMO)M tv(SPCL-SIMO)M tsu(SOMI-SPCL)M tv(SPCH-SOMI)M tv(SPCL-SOMI)M Cycle time, SPInCLK
0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M
256tc(ICLK) 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M
UNIT
Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Valid time, SPInCLK high after SPInSIMO data valid (clock polarity 85°C Valid time, SPInCLK high after SPInSIMO data valid (clock polarity 125°C Valid time, SPInCLK after SPInSIMO data valid (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity Setup time, SPInSOMI before SPInCLK (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity
MASTER (SPInCTRL2.3) CLOCK PHASE (SPInCTRL2.0) set. tc(ICLK) interface clock cycle time 1/f(ICLK) rise fall timings, "switching characteristics output timings versus load capacitance" table. When Master mode, following must true: values from 255:tc(SPC)M +1)tc(ICLK) where prescale value SPInCTL1.[12:5] register bits. values 0:tc(SPC)M 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2.1).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SPIn master mode timing parameters (continued)
SPInCLK (clock polarity SPInCLK (clock polarity SPInSIMO Master Data Valid Data Valid
PRODUCT PREVIEW
SPInSOMI
Master Data Must Valid
Figure SPIn Master Mode External Timing (CLOCK PHASE
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SPIn slave mode timing parameters SPIn slave mode external timing parameters (CLOCK PHASE SPInCLK input, SPInSIMO input, SPInSOMI output)(1)(2)(3)(4)(see Figure
2(6) 3(6) tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S td(SPCH-SOMI)S 4(6) td(SPCL-SOMI)S tv(SPCH-SOMI)S 5(6) tv(SPCL-SOMI)S tsu(SIMO-SPCL)S 6(6) tsu(SIMO-SPCH)S tv(SPCL-SIMO)S 7(6) tv(SPCH-SIMO)S Cycle time, SPInCLK
0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK)
256tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK)
UNIT
Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Delay time, SPInCLK high SPInSOMI valid (clock polarity Delay time, SPInCLK SPInSOMI valid (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity
tc(SPC)S tc(SPC)S
MASTER (SPInCTRL2.3) cleared CLOCK PHASE (SPInCTRL2.0) cleared. slave mode, following must true: tc(SPC)S tc(ICLK), where prescale value SPInCTL1.[12:5]. rise fall timings, "switching characteristics output timings versus load capacitance" table. tc(ICLK) interface clock cycle time 1/f(ICLK) When SPIn Slave mode, following must true: values from 255:tc(SPC)S +1)tc(ICLK) where prescale value SPInCTL1.[12:5] register bits. values 0:tc(SPC)S 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2.1).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SPIn slave mode timing parameters (continued)
SPInCLK (clock polarity SPInCLK (clock polarity SPInSOMI SPISOMI Data Valid
PRODUCT PREVIEW
SPInSIMO
SPISIMO Data Must Valid
Figure SPIn Slave Mode External Timing (CLOCK PHASE
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SPIn slave mode timing parameters (continued) SPIn slave mode external timing parameters (CLOCK PHASE SPInCLK input, SPInSIMO input, SPInSOMI output)(1)(2)(3)(4)(see Figure
2(6) 3(6) tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S tv(SOMI-SPCH)S 4(6) tv(SOMI-SPCL)S tv(SPCH-SOMI)S 5(6) tv(SPCL-SOMI)S tsu(SIMO-SPCH)S 6(6) tsu(SIMO-SPCL)S tv(SPCH-SIMO)S
Cycle time, SPInCLK
256tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S 0.25tc(ICLK)
UNIT
0.5tc(SPC)S -0.25tc(ICLK) 0.5tc(SPC)S -0.25tc(ICLK) 0.5tc(SPC)S -0.25tc(ICLK) 0.5tc(SPC)S -0.25tc(ICLK) 0.5tc(SPC)S 0.5tc(SPC)S 0.5tc(SPC)S 0.5tc(SPC)S
Pulse duration, SPInCLK high (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK (clock polarity Pulse duration, SPInCLK high (clock polarity Valid time, SPInCLK high after SPInSOMI data valid (clock polarity Valid time, SPInCLK after SPInSOMI data valid (clock polarity Valid time, SPInSOMI data valid after SPInCLK high (clock polarity Valid time, SPInSOMI data valid after SPInCLK (clock polarity Setup time, SPInSIMO before SPInCLK high (clock polarity Setup time, SPInSIMO before SPInCLK (clock polarity Valid time, SPInSIMO data valid after SPInCLK high (clock polarity Valid time, SPInSIMO data valid after SPInCLK (clock polarity
tv(SPCL-SIMO)S
MASTER (SPInCTRL2.3) cleared CLOCK PHASE (SPInCTRL2.0) set. slave mode, following must true: tc(SPC)S tc(ICLK), where prescale value SPInCTL1.[12:5]. rise fall timings, "switching characteristics output timings versus load capacitance" table. tc(ICLK) interface clock cycle time 1/f(ICLK) When SPIn Slave mode, following must true: values from 255:tc(SPC)S +1)tc(ICLK) where prescale value SPInCTL1.[12:5] register bits. values 0:tc(SPC)S 2tc(ICLK) active edge SPInCLK signal referenced controlled CLOCK POLARITY (SPInCTRL2.1).
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SPIn slave mode timing parameters (continued)
SPInCLK (clock polarity SPInCLK (clock polarity SPInSOMI SPISOMI Data Valid Data Valid
PRODUCT PREVIEW
SPInSIMO
SPISIMO Data Must Valid
Figure SPIn Slave Mode External Timing (CLOCK PHASE
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SCIn isosynchronous mode timings internal clock timing requirements internal clock SCIn isosynchronous mode(1)(2)(3) (see Figure
tc(SCC) tw(SCCL) tw(SCCH) td(SCCH-TXV) tv(TX) tsu(RX-SCCL) tv(SCCL-RX) Cycle time, SCInCLK Pulse duration, SCInCLK Pulse duration, SCInCLK high Delay time, SCInCLK high SCInTX valid Valid time, SCInTX data after SCInCLK Setup time, SCInRX before SCInCLK tc(SCC) tc(ICLK) (BAUD EVEN BAUD 2tc(ICLK) 0.5tc(SCC) 0.5tc(SCC) 224tc(ICLK) 0.5tc(SCC) 0.5tc(SCC) tc(SCC) tc(ICLK) tc(ICLK) (BAUD BAUD 3tc(ICLK) (224 tc(ICLK) UNIT
0.5tc(SCC) +0.5tc(ICLK) 0.5tc(SCC) +0.5tc(ICLK) 0.5tc(SCC) -0.5tc(ICLK) 0.5tc(SCC) -0.5tc(ICLK)
BAUD 24-bit concatenated value formed SCI[H,M,L]BAUD registers. tc(ICLK) interface clock cycle time 1/f(ICLK) rise fall timings, "switching characteristics output timings versus load capacitance" table. SCICLK SCITX SCIRX NOTE Data Valid Data Valid
Data transmission/reception characteristics isosynchronous mode with internal clocking similar asynchronous mode. Data transmission occurs SCICLK rising edge, data reception SCICLK falling edge.
Figure SCIn Isosynchronous Mode Timing Diagram Internal Clock
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Valid time, SCInRX data tc(ICLK) after SCInCLK
TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
SCIn isosynchronous mode timings external clock timing requirements external clock SCIn isosynchronous mode(1)(2) (see Figure
tc(SCC) tw(SCCH) tw(SCCL) td(SCCH-TXV) tv(TX) tsu(RX-SCCL) tv(SCCL-RX) Cycle time, SCInCLK
8tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 2tc(SCC)-10 2tc(ICLK)
UNIT
Pulse duration, SCInCLK high Pulse duration, SCInCLK Delay time, SCInCLK high SCInTX valid Valid time, SCInTX data after SCInCLK Setup time, SCInRX before SCInCLK Valid time, SCInRX data after SCInCLK
0.5tc(SCC) 0.25tc(ICLK) 0.5tc(SCC) 0.25tc(ICLK) 2tc(ICLK)
tc(ICLK) interface clock cycle time 1/f(ICLK) rise fall timings, "switching characteristics output timings versus load capacitance" table. When driving external SCInCLK, following must true: tc(SCC) 8tc(ICLK)
PRODUCT PREVIEW
SCICLK SCITX SCIRX NOTE Data Valid Data Valid
Data transmission/reception characteristics isosynchronous mode with external clocking similar asynchronous mode. Data transmission occurs SCICLK rising edge, data reception SCICLK falling edge.
Figure SCIn Isosynchronous Mode Timing Diagram External Clock
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
timing
Table below assumes testing over recommended operating conditions. Table Signals (SDA SCL) Switching Characteristics(1)
PARAMETER tc(I2CCLK) tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SCLH) th(SDA-SCLL) tw(SDAH) tw(SP)
STANDARD FAST MODE MODE UNIT devices 3.45(2)
Cycle time, module clock Cycle time, Setup time, high before (for repeated START condition) Hold time, after (for repeated START condition) Pulse duration, Pulse duration, high Setup time, valid before high Hold time, valid after
Pulse duration, high between STOP START conditions
tsu(SCLH-SDAH) Setup time, high before high (for STOP condition) Pulse duration, spike (must suppressed) Capacitive load each line
pins feature fail-safe buffers. These pins could potentially draw current when device powered down. maximum th(SDA-SCLL) devices needs only device does stretch period (tw(SCLL)) signal. total capacitance line
tw(SDAH) tw(SCLL) tr(SCL) tc(SCL) th(SCLL-SDAL) Stop Start tf(SCL) th(SDA-SCLL) th(SCLL-SDAL) tsu(SCLH-SDAL) tw(SCLH) tsu(SDA-SCLH) tw(SP) tsu(SCLH-SDAH)
Repeated Start
Stop
NOTE:A device must internally provide hold time least signal (referred VIHmin signal) bridge undefined region falling edge SCL. NOTE:The maximum th(SDA-SCLL) needs only device does stretch period (tw(SCLL)) signal. NOTE:A Fast-mode I2C-bus device used standard-mode I2C-bus system, requirement tsu(SDA-SCLH) must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line tsu(SDA-SCLH). NOTE:Cb total capacitance line mixed with fast-mode devices, faster fall-times allowed.
Figure Timings
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
standard controller (SCC) mode timings dynamic characteristics CANSTX CANSRX pins
PARAMETER td(CANSTX) td(CANSRX) Delay time, transmit shift register CANSTX pin(1) Delay time, CANSRX receive shift register UNIT
These values include rise/fall times output buffer.
expansion timing parameters, -40°C 150°C, (see figure figure
tc(CO) td(COH-EBADV) th(COH-EBADIV) td(COH-EBOE) th(COH-EBOEH) td(COL-EBWR) th(COL-EBWRH) tsu(EBRDATV-COH) th(COH-EBRDATIV) td(COL-EBWDATV) th(COL-EBWDATIV) td(COH-EBCS0) th(COH-EBCS0H) tsu(COH-EBHOLDL) tsu(COH-EBHOLDH) PARAMETER Cycle time, CLKOUT Delay Time, CLKOUT high EBADDR valid Hold Time, EBADDR invalid after CLKOUT high Delay Time, CLKOUT high EBOE fall Hold Time, EBOE rise after CLKOUT high Delay Time, CLKOUT write strobe (EBWR) Hold Time, EBWR high after CLKOUT Setup time, EBDATA valid before CLKOUT high (READ)(2) Hold time, EBDATA invalid after CLKOUT high (READ) Delay time, CLKOUT EBDATA valid SECONDARY TIMES Delay, CLKOUT high EBCS0 fall Hold, EBCS0 rise after CLKOUT high Setup time, EBHOLD CLKOUT high(2) high(2) (WRITE)(3) 20.8 UNIT
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Hold time, EBDATA invalid after CLKOUT (WRITE)
Setup time, EBHOLD high CLKOUT
Setup time minimum time under worst case conditions. Data with less setup time will work. Valid after CLKOUT goes write cycles.
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
expansion module timing
CLKOUT EBADDR Valid EBDATA EBOE EBCS0 EBHOLD Hold State Valid
Figure Expansion Memory Signal Timing Reads
CLKOUT EBADDR EBDATA EBWR EBCS0 EBHOLD Hold State Valid Valid
Figure Expansion Memory Signal Timing Writes
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
high-end timer (HET) timings
minimum output pulse width: This equal high resolution clock period (HRP). defined 6-bit high resolution prescale factor (hr) which user defined, giving prescale factors with linear increment codes. Therefore, minimum output pulse width HRP(min) hr(min)/SYSCLK 1/SYSCLK example, SYSCLK MHz, minimum output pulse width 1/30 33.33ns minimum input pulses capture: input pulse width must greater equal resolution clock period (LRP), i.e., loop (the program must within LRP). defined 3-bit loop-resolution prescale factor (lr), which user defined, with power increment codes. That value Therefore, minimum input pulse width LRP(min) hr(min) lr(min)/SYSCLK 1/SYSCLK example, with SYSCLK MHz, minimum input pulse width 1/30 33.33 NOTE Once input pulse width greater than LRP, resolution measurement still HRP. (That captured value gives number clocks inside pulse.) Abbreviations: High resolution clock period hr/SYSCLK Loop resolution clock period hr*lr/SYSCLK high resolution divide rate 3,.63, resolution divide rate
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
multi-buffered A-to-D converter (MibADC)
multi-buffered A-to-D converter (MibADC) separate power analog circuitry that enhances A-to-D performance preventing digital switching noise logic circuitry which could present from coupling into A-to-D analog stage. A-to-D specifications given with respect ADREFLO unless otherwise noted. Resolution bits (1024 values) Monotonic .Assured Output conversion code 3FFh ADREFLO; ADREFHI]
MibADC recommended operating conditions(1)
ADREFHI ADREFLO IAIC A-to-D high -voltage reference source A-to-D low-voltage reference source Analog input voltage Analog input clamp current(2) (VAI VSSAD VCCAD 0.3) VSSAD VSSAD VSSAD VCCAD VCCAD VCCAD UNIT
VCCAD VSSAD recommended operating conditions, "device recommended operating conditions" table. Input currents into input channel outside specified limits could affect conversion results other channels.
operating characteristics over full ranges recommended operating conditions(1)(2)
PARAMETER IAIL IADREFHI EDNL Analog input resistance Analog input capacitance Analog input leakage current ADREFHI input current Conversion range over which specified accuracy maintained Differential nonlinearity error DESCRIPTION/CONDITIONS Figure Figure Figure ADREFHI ADREFLO VSSAD ADREFHI ADREFLO Difference between actual step width ideal value. (See Figure Maximum deviation from best straight line through MibADC. MibADC transfer characteristics, excluding quantization error. (See Figure Maximum value difference between analog value ideal midstep value. (See Figure Conversion Sampling UNIT
EINL
Integral nonlinearity error
ETOT
Total error/Absolute accuracy
VCCAD ADREFHI (ADREFHI ADREFLO)/210 MibADC
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
multi-buffered A-to-D converter (MibADC) (continued)
External MibADC Input Sample Switch
Vsrc
Parasitic Capacitance
Sample Capacitor
Rleak
Figure MibADC Input Equivalent Circuit
PRODUCT PREVIEW
multi-buffer timing requirements
tc(ADCLK) td(SH) td(C) td(SHC)(1) Cycle time, MibADC clock Delay time, sample hold time Delay time, conversion time Delay time, total sample/hold conversion time 0.05
UNIT
0.55 1.55
This minimum sample/hold conversion time that achieved. These parameters dependent many factors; more details, TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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multi-buffered A-to-D converter (MibADC) (continued)
differential nonlinearity error shown Figure (sometimes referred differential linearity) difference between actual step width ideal value LSB.
Digital Output Code
Analog Input Value (LSB) Differential Linearity Error (-1/2 LSB)
Differential Linearity Error (1/2 LSB)
NOTE (ADREFHI ADREFLO)/210
Figure Differential Nonlinearity (DNL) integral nonlinearity error shown Figure (sometimes referred linearity error) deviation values actual transfer function from straight line.
Digital Output Code Actual Transition Analog Input Value (LSB) NOTE (ADREFHI ADREFLO)/210 Transition 011/100 LSB) End-Point Lin. Error Transition 001/010 LSB)
Ideal Transition
Figure Integral Nonlinearity (INL) Error
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
multi-buffer A-to-D converter (MibADC) (continued)
absolute accuracy total error MibADC shown Figure maximum value difference between analog value ideal midstep value.
Digital Output Code Analog Input Value (LSB) NOTE (ADREFHI ADREFLO)/210 Total Error Step (1/2 LSB) Total Error Step LSB)
PRODUCT PREVIEW
Figure Absolute Accuracy (Total) Error
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
MECHANICAL DATA (S-PQFP-G144)
PLASTIC QUAD FLATPACK
0,27 0,17 0,08
0,50
0,13
17,50 20,20 19,80 22,20 21,80
Gage Plane
0,05
0,25 0°-7°
1,45 1,35
0,75 0,45
Seating Plane 1,60 0,08
4040147/C NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026 Thermal Resistance Characteristics PARAMETER °C/W
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
MECHANICAL DATA (S-PQFP-G100) PLASTIC QUAD FLATPACK
0,50
0,27 0,17
0,08
PRODUCT PREVIEW
0,13
12,00 14,20 13,80 16,20 15,80 1,45 1,35
Gage Plane
0,05
0,25 0°-7°
0,75 0,45 Seating Plane
1,60
0,08
4040149/B 11/96 NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026 Thermal Resistance Characteristics PARAMETER °C/W
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
List Figures TMS470R1VF288 144-Pin Package (TOP VIEW) (without Expansion Bus) TMS470R1VF288 144-Pin Package (TOP VIEW) (with Expansion Bus) TMS470R1VF288 100-Pin Package (TOP VIEW) Functional Block Diagram Figure TMS470R1VF288 Memory Figure JTAG Interface Figure TMS470R1x Family Nomenclature Figure Test Load Circuit Figure Crystal/Clock Connection Figure CLKOUT Timing Diagram Figure ECLK Timing Diagram Figure PORRST Timing Diagram Figure JTAG Scan Timings Figure CMOS-Level Outputs Figure CMOS-Level Inputs Figure SPIn Master Mode External Timing (CLOCK PHASE Figure SPIn Master Mode External Timing (CLOCK PHASE Figure SPIn Slave Mode External Timing (CLOCK PHASE Figure SPIn Slave Mode External Timing (CLOCK PHASE Figure SCIn Isosynchronous Mode Timing Diagram Internal Clock Figure SCIn Isosynchronous Mode Timing Diagram External Clock Figure Timings Figure Expansion Memory Signal Timing Reads Figure Expansion Memory Signal Timing Writes Figure MibADC Input Equivalent Circuit Figure Differential Nonlinearity (DNL) Figure Integral Nonlinearity (INL) Error Figure Absolute Accuracy (Total) Error Mechanical Data Mechanical Data
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER
List Tables Table Table Table Table Table Table Table Table Table Table Table Device Characteristics TMS470R1VF288 Memory Selection Assignment VF288 Peripherals, System Module, Flash Base Addresses Request Lines Connections Interrupt Priority (IEM CIM) Expansion Mapping Expansion Pins MibADC Event Hookup Configuration TMS470 Device Allocation Register Device Part Number Signals (SDA SCL) Switching Characteristics
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TMS470R1VF288 16/32-BIT RISC FLASH MICROCONTROLLER REVISION HISTORY
REVISION HISTORY
DATE NOTES Updates: Page temperature condition removed from twec parameter. Page note revised. Page expansion timing parameters updated.
12/05
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