high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-b
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Blackfin Embedded Processor ADSP-BF538/ADSP-BF538F
high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease programming compiler friendly support Advanced debug, trace, performance monitoring 0.85 1.25 core with on-chip voltage regulation tolerant with specific tolerant pins 316-ball Pb-free CSP_BGA package Memory management unit providing memory protection External memory controller with glueless support SDRAM, SRAM, flash, Flexible memory booting options from external memory
PERIPHERALS
Parallel peripheral interface (PPI) supporting ITU-R video data formats dual-channel, full-duplex synchronous serial ports, supporting stereo channels controllers supporting peripheral DMAs memory-to-memory DMAs Controller area network (CAN) 2.0B controller SPI-compatible ports Three 32-bit timer/counters with support UARTs with support IrDA controllers compatible with industry standard general-purpose pins (GPIO) Real-time clock, watchdog timer, 32-bit core timer On-chip capable frequency multiplication Debug/JTAG interface
MEMORY
148K bytes on-chip memory: bytes instruction SRAM/cache bytes instruction SRAM bytes data SRAM bytes data SRAM/cache bytes scratchpad SRAM 512K 16-bit 256K 16-bit flash memory (ADSP-BF538F only)
I0-1 2.0B
ACCESS
PERIPHERAL ACCESS
I1-2 TION DATA
ACCESS
T1-2
ORT2-3
CORE
EXTERNAL
512kB F538F
Figure Functional Block Diagram
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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ADSP-BF538/ADSP-BF538F
TABLE CONTENTS
General Description Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface Controller Area Network (CAN) Interface Dynamic Power Management Voltage Regulation Booting Modes Instruction Description Development Tools Designing Emulator Compatible Processor Board Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information Sensitivity Timing Specifications Clock Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Request Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports-Master Timing Serial Peripheral Interface Ports-Slave Timing General-Purpose Port Timing Timer Cycle Timing JTAG Test Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Thermal Characteristics 316-Ball CSP_BGA Ball Assignments Outline Dimensions Surface-Mount Design Ordering Guide
REVISION HISTORY
1/08-Rev. Rev. Identifying pins CANRX V-tolerant when configured input open-drain when configured output.
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GENERAL DESCRIPTION
ADSP-BF538/ADSP-BF538F processors members Blackfin® family products, incorporating Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction architecture. ADSP-BF538/ADSP-BF538F processors completely code compatible with other Blackfin processors, differing only with respect performance, peripherals, on-chip memory. Specific performance, peripherals, memory configurations shown Table Table Processor Features
Feature SPORTs UARTs Instruction SRAM Data SRAM/Cache Data SRAM Scratchpad Flash Maximum Speed Grade ADSPBF538 bytes bytes bytes bytes ADSPBF538F4 bytes bytes bytes bytes bytes 16ADSPBF538F8 bytes bytes bytes bytes bytes 512K
SYSTEM INTEGRATION
ADSP-BF538/ADSP-BF538F processors highly integrated system-on-a-chip solutions next generation consumer industrial applications including audio video signal processing. combining advanced memory configurations, such on-chip flash memory, industry-standard interfaces, high performance signal processing core, costeffective solutions quickly developed, without need costly external components. system peripherals include three UART ports, three ports, four serial ports (SPORTs), interface, 2-wire interfaces (TWI), four generalpurpose timers (three with capability), real-time clock, watchdog timer, parallel peripheral interface (PPI), general-purpose pins.
ADSP-BF538/ADSP-BF538F PROCESSOR PERIPHERALS
ADSP-BF538/ADSP-BF538F processors contain rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see block diagram Page general-purpose peripherals include functions such UART, timers with (pulse-width modulation) pulse measurement capability, general-purpose pins, real-time clock, watchdog timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities device. addition these general-purpose peripherals, processors contain high speed serial parallel ports interfacing variety audio, video, modem codec functions. 2.0B controller provided automotive industrial control networks. interrupt controller manages interrupts from on-chip peripherals from external sources. Power management control functions tailor performance power characteristics processors system many application scenarios. peripherals, except general-purpose I/O, CAN, TWI, real-time clock, timers, supported flexible structure. There also four separate memory channels dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running with activity on-chip external peripherals. ADSP-BF538/ADSP-BF538F processors include on-chip voltage regulator support processor's dynamic power management capability. voltage regulator provides range core voltage levels from single 2.25 input. voltage regulator bypassed needed.
Instruction SRAM/Cache bytes
256K Applicable 1066 MMACS BC-316
1066 MMACS BC-316
1066 MMACS BC-316
Package Option
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next generation applications that require RISC-like programmability, multimedia support, leading edge signal processing integrated package.
POWER ARCHITECTURE
Blackfin processors provide world class power management performance. They designed using power voltage methodology feature dynamic power management, which ability vary both voltage frequency operation significantly lower overall power consumption. Varying voltage frequency result substantial reduction power consumption, compared with just varying frequency operation. This translates into longer battery life lower heat dissipation.
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BLACKFIN PROCESSOR CORE
shown Figure Page Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. computation units process 8-bit, 16-bit, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. compare/select vector search instructions also provided. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). Quad 16-bit operations possible using second ALU. 40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies.
ADDRESS ARITHMETIC UNIT
DAG1 DAG0
MEMORY
PREG
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER DECODE ALIGN
LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
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address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify, length, base registers (for circular buffering), eight additional 32-bit pointer registers (for style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. Memory Management Unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: User mode, Supervisor mode, Emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations.
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (64K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM/CACHE (16K BYTE) 0xFF90 4000 DATA BANK SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM/CACHE (16K BYTE) 0xFF80 4000 DATA BANK SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK BYTE) ON-CHIP FLASH (ADSP-BF538F ONLY) 0x2030 0000 0x2020 0000 ASYNC MEMORY BANK BYTE) ON-CHIP FLASH (ADSP-BF538F ONLY) ASYNC MEMORY BANK BYTE) ON-CHIP FLASH (ADSP-BF538F ONLY) 0x2010 0000 0x2000 0000 0x0800 0000 SDRAM MEMORY (16M BYTE 512M BYTE) 0x0000 0000 ASYNC MEMORY BANK BYTE) -CHIP FLASH (ADSP-BF538F ONLY) RESERVED
EXTERNAL MEMORY INTERNAL MEMORY
0xFFB0 0000
RESERVED
Figure ADSP-BF538/ADSP-BF538F Internal/External Memory
memory controllers provide high bandwidth data movement capability. They perform block transfers code data between internal memory external memory spaces.
Internal (On-Chip) Memory
ADSP-BF538/ADSP-BF538F processors have three blocks on-chip memory providing high bandwidth access core. first instruction memory, consisting bytes SRAM, which bytes configured four setassociative cache. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each memory bank configurable, offering both two-way set-associative cache SRAM functionality. This memory block accessed full processor speed. third memory block byte scratchpad SRAM, which runs same speed memories, only accessible data SRAM cannot configured cache memory.
MEMORY ARCHITECTURE
ADSP-BF538/ADSP-BF538F processors view memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, latency on-chip memory cache SRAM, larger, lower cost performance off-chip memory systems. Figure memory system primary highest performance memory available Blackfin processor. off-chip memory system, accessed through External Interface Unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 516M bytes physical memory.
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External (Off-Chip) Memory
External memory accessed external interface unit (EBIU). This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface 512M bytes SDRAM. SDRAM controller allows open each internal SDRAM bank, four internal SDRAM banks, improving overall system performance. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used, that these banks will only contiguous each fully populated with byte memory. million write cycles sector year data retention Blackfin processor connects flash memory with address, data, chip enable, write enable, output enable controls were external memory device. flash chip enable must connected AMS0 AMS3-1 through printed circuit board trace. When connected AMS0 Blackfin processor boot from flash die. When connected AMS3-1 flash memory appears nonvolatile memory processor memory shown Figure Page Flash Memory Programming ADSP-BF538F4 ADSP-BF538F8 flash memory programmed before after mounting printed circuit board. program flash prior mounting printed circuit board, hardware programming tool that provide data, address, control stimuli flash through external pins package. During this programming, VDDEXT must provided package Blackfin processor must held reset with request (BR) asserted CLKIN provided. VisualDSP++® tools used program flash memory after device mounted printed circuit board. Flash Memory Sector Protection
A18-0 RY/BY DQ15-0 BYTE RESET
Flash Memory
ADSP-BF538F4 ADSP-BF538F8 processors contain separate flash die, connected EBIU bus, within package processors. Figure Page shows flash memory Blackfin processor connected.
ADDR19-1 ARDY DATA15-0 VDDEXT
BLACKFIN
FLASH
ADDR19-1 ARDY DATA15-0 VDDEXT AMS3-0 RESET
sector protection feature, high voltage (+12 nominal) must applied flash FRESET pin. Refer flash data sheet details.
Memory Space
Blackfin processors define separate space. resources mapped through flat 32-bit address space. Onchip devices have their control registers mapped into memory mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
ADSP-BF538Fx PACKAGE
RESET AMS3-0 FRESET
Figure Internal Connection Flash Memory (ADSP-BF538Fx)
Booting
ADSP-BF538/ADSP-BF538F processors contain small boot kernel, which configures appropriate peripheral booting. processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
ADSP-BF538F4 contains (256K 16-bit) bottom boot sector Spansion S29AL004D known good flash memory. ADSP-BF538F8 contains (512K 16-bit) bottom boot sector Spansion S29AL008D known good flash memory. following features also included: access times fast (EBIU registers must appropriately) sector protection
Event Handling
event controller ADSP-BF538/ADSP-BF538F processors handle asynchronous synchronous events processors. processor provides event handling that supports both nesting prioritization. Nesting allows multiple
Refer Spansion website appropriate data sheets.
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event service routines active simultaneously. Prioritization ensures that servicing higher priority event takes precedence over servicing lower priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Nonmaskable interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow (the exception taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input pins, timers, other peripherals, well explicit software instruction. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processors saved supervisor stack. ADSP-BF538/ADSP-BF538F processors' event controllers consist stages, core event controller (CEC), system interrupt controllers (SIC). core event controller works with system interrupt controllers prioritize control system events. Conceptually, interrupts from peripherals enter into SICs, then routed directly into general-purpose interrupts CEC. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals processor. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities.
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System Interrupt Controllers (SIC)
system interrupt controllers (SIC0, SIC1) provide mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although ADSP-BF538/ADSP-BF538F processors provide default mapping, user alter mappings priorities interrupt events writing appropriate values into interrupt assignment registers (SIC_IARx). Table describes inputs into SICs default mappings into CEC. Table System Core Event Mapping
Event Source Wake-up Interrupt Controller Error Controller Error Error Interrupt SPORT0 Error Interrupt SPORT1 Error Interrupt SPORT2 Error Interrupt SPORT3 Error Interrupt SPI0 Error Interrupt SPI1 Error Interrupt SPI2 Error Interrupt UART0 Error Interrupt UART1 Error Interrupt UART2 Error Interrupt Error Interrupt Real-Time Clock Interrupts DMA0 Interrupt (PPI) DMA1 Interrupt (SPORT0 DMA2 Interrupt (SPORT0 DMA3 Interrupt (SPORT1 DMA4 Interrupt (SPORT1 DMA8 Interrupt (SPORT2 DMA9 Interrupt (SPORT2 DMA10 Interrupt (SPORT3 DMA11 Interrupt (SPORT3 DMA5 Interrupt (SPI0) DMA14 Interrupt (SPI1) DMA15 Interrupt (SPI2) DMA6 Interrupt (UART0 DMA7 Interrupt (UART0 DMA16 Interrupt (UART1 DMA17 Interrupt (UART1 DMA18 Interrupt (UART2 DMA19 Interrupt (UART2 Core Event Name IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10
Table System Core Event Mapping (Continued)
Event Source Timer0, Timer1, Timer2 Interrupts TWI0 Interrupt TWI1 Interrupt Receive Interrupt Transmit Interrupt Port GPIO Interrupts MDMA0 Stream Interrupt MDMA0 Stream Interrupt MDMA1 Stream Interrupt MDMA1 Stream Interrupt Software Watchdog Timer Core Event Name IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13
Event Control
ADSP-BF538/ADSP-BF538F processors provide user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: interrupt latch register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, also written clear (cancel) latched events. This register read while supervisor mode only written while supervisor mode when corresponding IMASK cleared. interrupt mask register (IMASK) IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked will processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) interrupt pending register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. Each allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page
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interrupt mask registers (SIC_IMASKx) These registers control masking unmasking each peripheral interrupt event. When these registers, that peripheral event unmasked will processed system when asserted. cleared these registers masks peripheral event, preventing processor from servicing event. interrupt status registers (SIC_ISRx) multiple peripherals mapped single event, these registers allow software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. interrupt wake-up enable registers (SIC_IWRx) enabling corresponding these registers, peripheral configured wake processor, should core idled when event generated. (For more information, Dynamic Power Management Page 13.) Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored SICs interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor. implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported processor controller include: single, linear buffer that stops upon completion circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page addition dedicated peripheral channels, there four memory channels provided transfers between various memories ADSP-BF538/ADSP-BF538F processor's systems. This enables transfers blocks data between memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention. Memory transfers controlled very flexible descriptor based methodology standard register based autobuffer mechanism.
REAL-TIME CLOCK
ADSP-BF538/ADSP-BF538F processors' real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external processor. peripheral dedicated power supply pins that remain powered clocked even when rest processors power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: second counter, minute counter, hour counter, 32,768 counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake ADSP-BF538/ADSP-BF538F processors from sleep mode upon generation wake-up event. Additionally, wake-up event wake processor from deep sleep mode wake on-chip internal voltage regulator from powered down hibernate state. Connect pins RTXI RTXO with external components shown Figure
CONTROLLERS
ADSP-BF538/ADSP-BF538F processors have two, independent controllers that support automated data transfers with minimal overhead processor core. transfers occur between processor internal memories capable peripherals. Additionally, transfers accomplished between capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory controller. capable peripherals include SPORTs, ports, UARTs, PPI. Each individual capable peripheral least dedicated channel. controllers support both 1-dimensional (1-D) 2dimensional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing
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RTXI RTXO
addition three general-purpose programmable timers, fourth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
SERIAL PORTS (SPORTs)
ADSP-BF538/ADSP-BF538F processors incorporate four dual-channel synchronous serial ports serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits bits length, transferred most significant first least significant first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync. Companding hardware Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability Each SPORT supports channels 1024 channel window compatible with H.100, H.110, MVIP-90, HMVIP standards.
SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 LOAD (SURFACE-MOUNT PACKAGE) NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE
Figure External Components
WATCHDOG TIMER
ADSP-BF538/ADSP-BF538F processors include 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
TIMERS
There four general-purpose programmable timer units ADSP-BF538/ADSP-BF538F processors. Three timers have external that configured either pulse width modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input (TACLK), external clock input PPI_CLK (TMRCLK), internal SCLK. timer units used conjunction with UART0 measure width pulses data stream provide auto-baud detect function serial channel. timers generate interrupts processor core providing periodic events synchronization, either system clock count external signals.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
ADSP-BF538/ADSP-BF538F processors incorporate three SPI-compatible ports that enable processor communicate with multiple compatible devices. interface uses three pins transferring data: data pins (master output-slave input, MOSIx, master input-slave output, MISOx) clock (serial clock, SCKx). chip select input (SPIxSS) lets other devices select
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processor. SPI0, seven chip select output pins (SPI0SEL7-1) processor select other devices. SPI1 SPI2 each have single chip select output (SPI1SEL1 SPI2SEL1) point-to-point communication. Each select pins reconfigured GPIO pins. Using these pins, ports provide full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. ports' baud rate clock phase/polarities programmable, they each have integrated controller, configurable support transmit receive data streams. Each SPI's controller only service unidirectional accesses given time. port's clock rate calculated SCLK Clock Rate SPIx_BAUD where 16-bit SPIx_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines. channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. Each UART port's baud rate, serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/1,048,576) (fSCLK/16) bits second. Supporting data formats from to12 bits frame. Both transmit receive operations configured generate maskable interrupts processor. Each UART port's clock rate calculated SCLK UART Clock Rate UART_Divisor where 16-bit UART_Divisor comes from UARTx_DLH register (most significant bits) UARTx_DLL register (least significant bits). conjunction with general-purpose timer functions, autobaud detection supported UART0. capabilities UARTs further extended with support Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.
2-WIRE INTERFACE
ADSP-BF538/ADSP-BF538F processors have 2-wire interface (TWI) modules that compatible with Philips Inter-IC standard. modules offer capabilities simultaneous master slave operation, support 7-bit addressing multimedia data arbitration. also includes master clock synchronization support clock extension. interface uses pins transferring clock (SCLx) data (SDAx) supports protocol speeds kbps. interface pins compatible with logic levels.
GENERAL-PURPOSE PORTS
ADSP-BF538/ADSP-BF538F processors have general-purpose pins that multiplexed with other peripherals. They arranged into ports shown Table general-purpose pins individually controlled manipulation control status registers. These pins polled determine their status. GPIO direction control register Specifies direction each individual GPIO input output. GPIO control status registers processor employs "write modify" mechanism that allows combination individual GPIO modified single instruction, without affecting level other GPIO. Four control registers data register provided each GPIO port. register written order GPIO values, register written order clear GPIO values, register written order toggle GPIO values, register written order specify GPIO input output. Reading GPIO data allows software determine state input GPIO pins. addition GPIO function described above, port pins individually configured generate interrupts. GPIO interrupt mask registers GPIO interrupt mask registers allow each individual function interrupt processor. Similar GPIO control registers that used clear individual GPIO values, GPIO interrupt mask register sets bits enable interrupt function, other GPIO interrupt mask register clears bits disable
UART PORTs
ADSP-BF538/ADSP-BF538F processors incorporate three full-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which fully compatible with standard UARTs. UART ports provide simplified UART interface other peripherals hosts, supporting full-duplex, supported, asynchronous transfers serial data. UART ports include support data bits data bits, stop stop bits, none, even, parity. UART ports support modes operation: (programmed I/O) processor sends receives data writing reading mapped UART registers. data double buffered both transmit receive. (direct memory access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. Each UART dedicated
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interrupt function. pins defined inputs configured generate hardware interrupts, while output pins triggered software interrupts. GPIO interrupt sensitivity registers GPIO interrupt sensitivity registers specify whether individual pins level- edge-sensitive specify-if edge-sensitive-whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity. Table GPIO Ports
Peripheral SPORT2 SPORT3 SPI0 SPI1 SPI2 UART1 UART2 GPIO
General-Purpose Mode Descriptions
general-purpose modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input mode frame syncs data inputs into PPI. Frame capture mode frame syncs outputs from PPI, data inputs. Output mode frame syncs data outputs from PPI.
Input Mode
Input mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples user programmable defined contents PPI_COUNT register. supports 8-bit, 10-bit through 16-bit data, programmable PPI_CONTROL register.
Alternate GPIO Port Function GPIO Port F15-3 GPIO Port E7-0 GPIO Port E15-8 GPIO Port F7-0 GPIO Port D4-0 GPIO Port D9-5 GPIO Port D11-10 GPIO Port D13-12 GPIO Port C1-0 GPIO Port C9-41
Frame Capture Mode
Frame capture mode allows video source(s) slave (e.g., frame capture). ADSP-BF538/ADSP-BF538F processors control when read from video source(s). PPI_FS1 HSYNC output PPI_FS2 VSYNC output.
These pins GPIO only cannot reconfigured through software. open-drain when configured GPIO outputs.
PARALLEL PERIPHERAL INTERFACE
ADSP-BF538/ADSP-BF538F processors provide parallel peripheral interface (PPI) that connect directly parallel converters, video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, frame synchronization pins, data pins. input clock supports parallel data rates fSCLK/2 MHz, synchronization signals configured either inputs outputs. supports variety general-purpose ITU-R modes operation. general-purpose mode, provides half-duplex, bi-directional data transfer with bits data. frame synchronization signals also provided. ITU-R mode, provides half-duplex, bi-directional transfer 10-bit video data. Additionally, on-chip decode embedded start-of-line (SOL) start-of-field (SOF) preamble packets supported.
Output Mode
Output mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hardware signaling. ITU-R Mode Descriptions ITU-R modes intended suit wide variety video capture, processing, transmission applications. Three distinct submodes supported: Active video only mode Vertical blanking only mode Entire field mode
Active Video Only Mode
Active video only mode used when only active video portion field interest blanking intervals. does read data between active video (EAV) start active video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field ignores incoming samples until sees code. user specifies number active video lines frame PPI_COUNT register).
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Vertical Blanking Interval Mode
this mode, only transfers vertical blanking interval (VBI) data. further reducing power dissipation. Control clocking each processor peripherals also reduces power consumption. Table summary power settings each mode.
Entire Field Mode
this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Data transfer starts immediately after synchronization Field
Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
CONTROLLER AREA NETWORK (CAN) INTERFACE
ADSP-BF538/ADSP-BF538F processors provide controller that communication controller implementing Controller Area Network (CAN) V2.0B protocol. This protocol asynchronous communications protocol used both industrial automotive control systems. well suited control applications capability communicate reliably over network since protocol incorporates checking, message error tracking, fault node confinement. controller based 32-entry mailbox supports both standard extended identifier (ID) message formats specified protocol specification, revision 2.0, part Each mailbox consists eight 16-bit data words. data divided into fields, which includes message identifier, time stamp, byte count, bytes data, several control bits. Each node monitors messages being passed network. identifier transmitted message matches identifier mailboxes, then module knows that message meant passes data into appropriate mailbox, signals processor message arrival with interrupt. controller wake processor from sleep mode upon generation wake-up event, such that processor maintained power mode during idle conditions. Additionally, wake-up event wake on-chip internal voltage regulator from powered-down hibernate state. electrical characteristics each network connection very stringent, therefore interface typically divided into parts: controller transceiver. This allows single controller support different drivers networks. ADSP-BF538/ADSP-BF538F module represents controller part interface. This module's network single transmit output single receive input, which connect line transceiver. clock derived from processor system clock (SCLK) through programmable divider therefore does require additional crystal.
Active Operating Mode-Moderate Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. this mode, CLKIN CCLK multiplier ratio changed, although changes realized until full-on mode entered. access available appropriately configured memories. active mode, possible disable through Control register (PLL_CTL). disabled, must re-enabled before transitioning Full-On Sleep modes. Table Power Settings
Mode/State Bypassed
System Clock (SCLK)
Core Clock (CCLK)
Full-On Active Sleep Hibernate
Enabled Enabled Disabled
Enabled Enabled Enabled Enabled Disabled Enabled Disabled Disabled Disabled Disabled
Enabled/ Disabled
Deep Sleep Disabled
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity will wake processor. When Sleep mode, assertion wake-up causes processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, processor transitions full mode. BYPASS enabled, processor will transition Active mode. When sleep mode, system access memory supported.
Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals such still running, will able access internal resources external memory. This powered down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated
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DYNAMIC POWER MANAGEMENT
ADSP-BF538/ADSP-BF538F processors provide four operating modes, each with different performance/power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage,
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ADSP-BF538/ADSP-BF538F
RTC. When deep sleep mode, asynchronous interrupt causes processor transition active mode. Assertion RESET while deep sleep mode causes processor transition full mode after processor reset. dynamic power management feature processor allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. savings power dissipation modeled using power savings factor power savings calculations. power savings factor calculated
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator processor shut writing b#00 FREQ bits VR_CTL register. This disables both CCLK SCLK. Furthermore, sets internal power supply voltage (VDDINT) provide lowest static power dissipation. critical information stored internally (memory contents, register contents, etc.) must written nonvolatile storage device prior removing power processor state preserved. Since VDDEXT still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor still have power applied without drawing unwanted current. internal supply regulator woken either realtime clock wake-up, traffic, asserting RESET pin, external source.
Power Savings Factor DDINTRED CCLKRED CCLKNOM DDINTNOM where fCCLKNOM nominal core clock frequency. fCCLKRED reduced core clock frequency. VDDINTNOM nominal internal supply voltage. VDDINTRED reduced internal supply voltage. TNOM duration running fCCLKNOM. TRED duration running fCCLKRED. power savings factor calculated Power Savings Power Savings Factor 100%
Power Savings
shown Table ADSP-BF538/ADSP-BF538F processors support three different power domains. multiple power domains maximizes flexibility, while maintaining compliance with industry standards conventions. VDDRTC power domain supplies logic that remain functional when rest chip powered off. 1.25 VDDINT power domain supplies internal logic except logic. VDDEXT power domain supplies except crystal. There sequencing requirements various power domains. Table Power Domains
Power Domain Crystal Logic Internal Logic Except Except Range VDDRTC VDDINT VDDEXT
VOLTAGE REGULATION
Blackfin processor provides on-chip voltage regulator that generate processor core voltage levels (-5%/+10%) (-5%/+10%) 1.25 (-4% +10%) from external supply. Figure shows typical external components required complete power management system.
2.25V 3.6V INPUT VOLTAGE RANGE
VDDEXT (LOW-INDUCTANCE)
DECOUPLING CAPACITORS
100µF 100nF 100µF FDS9431A 10µF 100µF ZHCS1000 10µH
VDDEXT
VDDRTC should either connected battery operate while rest chip powered down) should connected VDDEXT plane board. VDDRTC should remain powered when processor hibernate state, should also powered even functionality being used application. power dissipated processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction dynamic power dissipation, while reducing voltage reduces dynamic power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic.
VDDINT
VROUT
SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A.
VROUT
Figure Voltage Regulator Circuit
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regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments reduce standby power consumption, internal voltage regulator programmed remove power processor core while power (VDDRTC, VDDEXT) still supplied. While hibernate state, power still being applied, eliminating need external buffers. voltage regulator activated from this power-down state either through wake-up, wake-up, general-purpose wake-up, asserting RESET, which will then initiate boot sequence. regulator also disabled bypassed user's discretion. third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone, adding tuned inductor circuit shown Figure
BLACKFIN CLKOUT CIRCUITRY
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, bypass capacitors have significant effect noise injected into other analog circuits on-chip. VROUT1-0 traces voltage regulator external components should considered noise sources when doing board layout should routed placed near sensitive circuits components board. internal power supplies should well bypassed with bypass capacitors placed close ADSPBF538/ADSP-BF538F processors possible. further details on-chip voltage regulator related board design guidelines, Switching Regulator Design Considerations ADSP-BF533 Blackfin Processor (EE-228) applications note Analog Devices website (www.analog.com)-use site search "EE-228".
CLKIN XTAL OVERTONE OPERATION ONLY
18pF*
18pF*
NOTE: VALUES MARKED WITH MUST CUSTOMIZED DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY.
Figure External Crystal Connections
CLOCK SIGNALS
ADSP-BF538/ADSP-BF538F processors clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should TTL-compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because ADSP-BF538/ADSP-BF538F processors include on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessor-grade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Further parallel resistors typically recommended. capacitors series resistor, shown Figure fine tune phase amplitude sine frequency. capacitor resistor values, shown Figure typical values only. capacitor values dependent upon crystal manufacturer's load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. System designs should verify customized values based careful investigation multiple devices over allowed temperature range.
shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal user programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence. On-the-fly frequency changes effected simply writing PLL_DIV register.
"FINE" ADJUSTMENT REQUIRES SEQUENCING
"COARSE" ADJUSTMENT ON-THE-FLY
CLKIN 1:15
CCLK
SCLK
SCLK CCLK SCLK
Figure Frequency Modification Methods
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through
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Table illustrates typical system clock ratios: Table Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz) SSEL3-0 VCO/SCLK SCLK 0001 0110 1010 10:1
BMODE pins reset configuration register, sampled during power-on resets software initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000 0000 with 16-bit packing. boot bypassed this mode. configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from 8-bit 16-bit external flash memory 8-bit flash boot routine located boot memory space using asynchronous memory bank ADSP-BF538F processors, on-chip flash booted connected AMS0. configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from serial EEPROM/flash (8-, 16-, 24-bit addressable, Atmel AT45DB041, AT45DB081, AT45DB161) connected SPI0- SPI0 uses output select single EEPROM/flash device, submits read command successive address bytes (0x00) until valid 16-, 24-bit, Atmel addressable device detected, begins clocking data into processor beginning instruction memory. Boot from host device connected SPI0 Blackfin processor operates slave mode configured receive bytes file from host (master) agent. hold host device from transmitting while boot busy, Blackfin processor asserts GPIO pin, called host wait (HWAIT), signal host device send more bytes until flag deasserted. flag chosen user this information transferred Blackfin processor bits 10:5 FLAG header image. each boot modes, 10-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from start instruction SRAM. addition, reset configuration register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory. augment boot modes, secondary software loader provided that adds additional booting mechanisms. This secondary loader provides capability boot from 16-bit flash memory, fast flash, variable baud rate, other sources. boot modes except bypass, program execution starts from on-chip memory address 0xFFA0 0000.
maximum frequency system clock fSCLK. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). Note that when SSEL value changed, will affect peripherals that derive their clock signals from SCLK signal. core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications. Table Core Clock Ratios
Signal Name CSEL1-0 Divider Ratio VCO/CCLK Example Frequency Ratios CCLK
BOOTING MODES
ADSP-BF538/ADSP-BF538F processors have three mechanisms (listed Table automatically loading internal instruction memory after reset. fourth mode provided execute from external memory, bypassing boot sequence. Table Booting Modes
BMODE1-0 Description Execute from 16-Bit External Memory (Bypass Boot ROM) Boot from 8-Bit 16-Bit Flash, Boot from On-Chip Flash (ADSP-BF538F Only) Boot from Serial Master Connected SPI0 Boot from Serial Slave EEPROM /Flash (8-,16-, 24-Bit Address Range, Atmel AT45DB041, AT45DB081, AT45DB161 Serial Flash) Connected SPI0
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides
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fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. multi-issue load/store modified Harvard architecture, which supports 16-bit four 8-bit plus load/store plus pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits. plexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processors they running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information). Insert breakpoints. conditional breakpoints registers, memory, stacks. Trace instruction execution. Perform linear statistical profiling program execution. Fill, dump, graphically plot contents memory. Perform source level debugging. Create custom debugger windows. VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage Blackfin development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, preemptive, cooperative, time-sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK.
DEVELOPMENT TOOLS
ADSP-BF538/ADSP-BF538F processors supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Blackfin processors also fully emulates ADSP-BF538/ADSP-BF538F processors. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code processor assembly. processors have architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow com-
CROSSCORE registered trademark Analog Devices, Inc. VisualDSP++ registered trademark Analog Devices, Inc.
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Expert Linker visually manipulate placement code data embedded system. View memory utilization color coded graphical form, easily move code data different areas processor external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG Test Access Port ADSP-BF538/ADSP-BF538F processors monitor control target board processor during emulation. emulator provides full speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin processor family. Hardware tools include Blackfin processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools. must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, Analog Devices JTAG Emulation Technical Reference (EE-68) Analog Devices site (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
Evaluation
Analog Devices offers range EZ-KIT Lite® evaluation platforms cost effective method learn more about developing prototyping applications with Analog Devices processors, platforms, software tools. Each EZ-KIT Lite includes evaluation board along with evaluation suite VisualDSP++ development debugging environment with C/C++ compiler, assembler, linker. Also included sample application programs, power supply, cable. evaluation versions software tools limited only with EZ-KIT Lite product. controller EZ-KIT Lite board connects board port user's enabling VisualDSP++ evaluation suite emulate on-board processor in-circuit. This permits customer download, execute, debug programs EZ-KIT Lite system. also allows in-circuit programming on-board flash device store user-specific boot code, enabling board standalone unit without being connected With full version VisualDSP++ installed (sold separately), engineers develop software EZ-KIT Lite custom defined system. Connecting Analog Devices JTAG emulators EZ-KIT Lite board enables high speed, nonintrusive emulation.
DESIGNING EMULATOR COMPATIBLE PROCESSOR BOARD
Analog Devices family emulators tools that every system developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. procesRev. Page January 2008
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DESCRIPTIONS
ADSP-BF538/ADSP-BF538F processors definitions listed Table pins three-stated during immediately after reset, except memory interface, asynchronous memory control, synchronous memory control pins, which driven high. active, then memory pins also three-stated. unused pins have their input buffers disabled with exception pins that need pull-ups pull-downs, noted table. order maintain maximum functionality reduce package size count, some pins have dual, multiplexed functionality. cases where functionality reconfigurable, default state shown plain text, while alternate functionality shown italics.
Table Descriptions
Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 Asynchronous Memory Control AMS3-0 ARDY Flash Control FRESET Synchronous Memory Control SRAS SCAS SCKE CLKOUT SA10 Timers TMR0 TMR1/PPI_FS1 TMR2/PPI_FS2 Timer Timer 1/PPI Frame Sync1 Timer 2/PPI Frame Sync2 Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Bank Select Flash Enable (This should left unconnected pulled ADSP-BF538.) Flash Reset (This should left unconnected pulled ADSP-BF538.) Bank Select Hardware Ready Control (This should always pulled when used.) Output Enable Read Enable Write Enable Address Async/Sync Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request (This should pulled high when used.) Grant Grant Hang Function Driver Type1
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Table Descriptions (Continued)
Name 2-Wire Interface Port SDA0 SCL0 SDA1 SCL1 Serial Port0 RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC Serial Port1 RSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC SPI0 Port MOSI0 MISO0 SCK0 UART0 Port Port PPI3-0 PPI_CLK/TMRCLK Port Controller Area Network/GPIO CANTX/PC0 CANRX/PC1 PC[9-5] Transmit/GPIO I/OD Receive/GPIO GPIO I/OD GPIO PPI3-0 Clock/External Timer Reference UART0 Receive UART0 Transmit SPI0 Master Slave SPI0 Master Slave (This should always pulled high through resistor booting port.) SPI0 Clock SPORT1 Receive Serial Clock SPORT1 Receive Frame Sync SPORT1 Receive Data Primary SPORT1 Receive Data Secondary SPORT1 Transmit Serial Clock SPORT1 Transmit Frame Sync SPORT1 Transmit Data Primary SPORT1 Transmit Data Secondary SPORT0 Receive Serial Clock SPORT0 Receive Frame Sync SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Serial Clock SPORT0 Transmit Frame Sync SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary Function These pins open-drain require pull-up resistor. version specification proper resistor values. TWI0 Serial Data TWI0 Serial Clock TWI1 Serial Data TWI1 Serial Clock Driver Type1
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Table Descriptions (Continued)
Name Port SPI1/SPI2/UART1/UART2/GPIO MOSI1/PD0 MISO1/PD1 SCK1/PD2 SPI1SS/PD3 SPI1SEL1/PD4 MOSI2/PD5 MISO2/PD6 SCK2/PD7 SPI2SS/PD8 SPI2SEL1/PD9 RX1/PD10 TX1/PD11 RX2/PD12 TX2/PD13 Port SPORT2/SPORT3/GPIO RSCLK2/PE0 RFS2/PE1 DR2PRI/PE2 DR2SEC/PE3 TSCLK2/PE4 TFS2/PE5 DT2PRI/PE6 DT2SEC/PE7 RSCLK3/PE8 RFS3/PE9 DR3PRI/PE10 DR3SEC/PE11 TSCLK3/PE12 TFS3/PE13 DT3PRI /PE14 DT3SEC/PE15 Port GPIO/PPI/SPI0/Timers PF0/SPI0SS PF1/SPI0SEL1/TACLK PF2/SPI0SEL2 PF3/PPI_FS3/SPI0SEL3 PF4/PPI15/SPI0SEL4 PF5/PPI14/SPI0SEL5 PF6/PPI13/SPI0SEL6 PF7/PPI12/SPI0SEL7 GPIO/SPI0 Slave Select Input GPIO/SPI0 Slave Select Enable 1/Timer Alternate Clock Input GPIO/SPI0 Slave Select Enable GPIO/PPI Frame Sync 3/SPI0 Slave Select Enable GPIO/PPI15/SPI0 Slave Select Enable GPIO/PPI14/SPI0 Slave Select Enable GPIO/PPI13/SPI0 Slave Select Enable GPIO/PPI12/SPI0 Slave Select Enable SPORT2 Receive Serial Clock/GPIO SPORT2 Receive Frame Sync/GPIO SPORT2 Receive Data Primary/GPIO SPORT2 Receive Data Secondary/GPIO SPORT2 Transmit Serial Clock/GPIO SPORT2 Transmit Frame Sync/GPIO SPORT2 Transmit Data Primary/GPIO SPORT2 Transmit Data Secondary/GPIO SPORT3 Receive Serial Clock/GPIO SPORT3 Receive Frame Sync/GPIO SPORT3 Receive Data Primary/GPIO SPORT3 Receive Data Secondary/GPIO SPORT3 Transmit Serial Clock/GPIO SPORT3 Transmit Frame Sync/GPIO SPORT3 Transmit Data Primary/GPIO SPORT3 Transmit Data Secondary/GPIO SPI1 Master Slave In/GPIO SPI1 Master Slave Out/GPIO SPI1 Clock/GPIO SPI1 Slave Select Input/GPIO SPI1 Slave Select Enable/GPIO SPI2 Master Slave In/GPIO SPI2 Master Slave Out/GPIO SPI2 Clock/GPIO SPI2 Slave Select Input/GPIO SPI2 Slave Select Enable/GPIO UART1 Receive/GPIO UART1 Transmit/GPIO UART2 Receive/GPIO UART2 Transmit/GPIO Function Driver Type1
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Table Descriptions (Continued)
Name PF8/PPI11 PF9/PPI10 PF10/PPI9 PF11/PPI8 PF12/PPI7 PF13/PPI6 PF14/PPI5 PF15/PPI4 Real-Time Clock RTXI RTXO JTAG Port TRST Clock CLKIN XTAL Mode Controls RESET BMODE1-0 Voltage Regulator VROUT0 VROUT1 Supplies VDDEXT VDDINT VDDRTC
Function GPIO/PPI11 GPIO/PPI10 GPIO/PPI9 GPIO/PPI8 GPIO/PPI7 GPIO/PPI6 GPIO/PPI5 GPIO/PPI4 Crystal Input (This should pulled when used.) Crystal Output JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This should pulled JTAG port will used.) Emulation Output Clock/Crystal Input Crystal Output Reset Nonmaskable Interrupt (This should pulled high when used.) Boot Mode Strap External Drive (This should left unconnected when used.) External Drive (This should left unconnected when used.) General-Purpose Regulator Wake-up (This should pulled high when used.) Power Supply Internal Power Supply Real-Time Clock Power Supply Ground
Driver Type1
Refer Figure Page Figure Page This V-tolerant when configured input open-drain when configured output; therefore, only curves Figure Page Figure Page Fall Time curves Figure Page Figure Page apply when configured output.
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SPECIFICATIONS
Note that component specifications subject change without notice.
OPERATING CONDITIONS
Parameter VDDINT VDDINT VDDEXT VDDEXT VDDRTC VIH5V VIL5V
Conditions Speed Grade Models Speed Grade Models1, Model with on-chip flash2 Models without on-chip flash
2.25 2.25
1.25
1.375 1.32 +0.6 +0.8 +105
Unit
Internal Supply Voltage Internal Supply Voltage External Supply Voltage External Supply Voltage Real-Time Clock Power Supply Voltage High Level Input Voltage3 High Level Input Voltage4
VDDEXT Maximum VDDEXT Maximum VDDEXT Maximum VDDEXT Minimum VDDEXT Minimum 316-Ball Chip Scale Ball Grid Array (CSP_BGA) TAMBIENT -40°C +85°C
-0.3 -0.3
VIHCLKIN High Level Input Voltage Level Input Voltage Junction Temperature
Level Input Voltage3,
regulator generate VDDINT levels 0.85 with +10% tolerance 1.25 with +10% tolerance Ordering Guide Page tolerant pins capable accepting maximum following bidirectional pins tolerant: DATA15-0, SCK2-0, MISO2-0, MOSI2-0, PF15-0, PPI3-0, SPI1SS, SPI1SEL1, PC[9-5], SPI2SS, SPI2SEL1, RX2-1, TX2-1, TSCLK3-0, RSCLK3-0, TFS3-0, RFS3-0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, TMR2-0. following input-only pins tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE1-0, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI. tolerant pins capable accepting maximum VIH. following bi-directional pins tolerant: SCL0, SCL1, SDA0, SDA1, CANTX, CANRX, PC4. following input-only tolerant: GPW. Parameter value applies CLKIN input pin. Parameter value applies input bidirectional pins.
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ELECTRICAL CHARACTERISTICS
Parameter1 IIHP IOZH IOZL IDDHIBERNATE IDDDEEPSLEEP IDDSLEEP IDD_TYP IDD_TYP IDD_TYP IDDRTC
Test Conditions High Level Output Voltage High Level Input Current3 High Level Input Current JTAG Level Input Current
10.0 50.0 10.0 10.0 10.0
Unit
VDDEXT +3.0 -0.5 VDDEXT VDDEXT Maximum, Maximum VDDEXT Maximum, Maximum VDDEXT Maximum, VDDEXT Maximum, Maximum VDDEXT Maximum, fCCLK MHz, TAMBIENT 25°C, VDDEXT with Voltage Regulator (VDDINT VDDINT 0.80 TJUNCTION 25°C fSCLK
Level Output Voltage2
Three-State Leakage Current Input Capacitance6,
Three-State Leakage Current5 VDDINT Current Hibernate State
VDDINT Current Deep Sleep Mode VDDINT 0.80 TJUNCTION 25°C VDDINT Current Sleep Mode VDDINT Current Dissipation (Typical) VDDINT 0.80 fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT 1.14 fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT fCCLK MHz, TJUNCTION 25°C VDDRTC Current VDDRTC TJUNCTION 25°C
Specifications subject change without notice. Applies output bidirectional pins. Applies input pins except JTAG inputs. Applies JTAG input pins (TCK, TDI, TMS, TRST). Applies three-statable pins. Applies signal pins. Guaranteed, tested. Power Dissipation Page Processor executing dual MAC, with moderate data activity.
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage2 Input Voltage1, Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Under bias
PACKAGE INFORMATION
information presented Figure Table provides information about read package brand relate specific product features. complete listing product offerings, Ordering Guide Page
Rating -0.3 +1.4 -0.3 +3.8 -0.5 +3.6 -0.5 +5.5 -0.5 VDDEXT +0.5 -65°C +150°C +125°C
ADSP-BF538 tppZccc vvvvvv.x yyww country_of_origin
Figure Product Information Package
tolerant pins capable accepting maximum VIH. following bidirectional pins tolerant: SCL0, SCL1, SDA0, SDA1, CANTX, CANRX, PC4. following input-only tolerant: GPW. other duty cycles, Table Applies only when VDDEXT within specifications. When VDDEXT outside specifications, range VDDEXT
Table Package Brand Information
Brand vvvvvv.x yyww Field Description Temperature Range Package Type RoHS Compliant Part Ordering Guide Assembly Code Silicon Revision Date Code
Table Maximum Duty Cycle Input Transient Voltage1
-0.50 -0.70 -0.80 -0.90 -1.00
(V)2 +3.80 +4.00 +4.10 +4.20 +4.30
Maximum Duty Cycle 100%
Applies signal pins with exception CLKIN, XTAL, VROUT1-0. Only listed options apply particular design.
SENSITIVITY
(electrostatic discharge) sensitive device. Charged devices circuit boards discharge without detection. Although this product features patented proprietary circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should take avoid performance degradation loss functionality.
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TIMING SPECIFICATIONS
Table Table describe timing requirements ADSP-BF538/ADSP-BF538F processors' clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock, system clock, voltage controlled Table Core Clock (CCLK) Requirements Models
Parameter fCCLK Frequency (VDDINT 1.14 Minimum) fCCLK Frequency (VDDINT 1.045 Minimum) fCCLK Frequency (VDDINT 0.95 Minimum) fCCLK Frequency (VDDINT 0.85 Minimum) fCCLK Frequency (VDDINT Minimum) Internal Regulator Setting 1.20 1.10 1.00 0.90 0.85 Unit
oscillator (VCO) operating frequencies, described Absolute Maximum Ratings Page Table describes phaselocked loop operating conditions. Table lists System Clock Requirements.
Table Core Clock (CCLK) Requirements Models
Parameter fCCLK Core Clock Frequency (VDDINT Minimum) fCCLK Core Clock Frequency (VDDINT 1.14 Minimum) fCCLK Core Clock Frequency (VDDINT 1.045 Minimum) fCCLK Core Clock Frequency (VDDINT 0.95 Minimum) fCCLK Core Clock Frequency (VDDINT 0.85 Minimum) fCCLK Core Clock Frequency (VDDINT Minimum) Internal Regulator Setting 1.25 1.20 1.10 1.00 0.95 0.85 Unit
Table Phase-Locked Loop Operating Conditions
Parameter fVCO Voltage Controlled Oscillator (VCO) Frequency fCCLK Unit
Table System Clock (SCLK) Requirements
Parameter1 fSCLK CLKOUT/SCLK Frequency (VDDINT 1.14 fSCLK CLKOUT/SCLK Frequency (VDDINT 1.14
1332
Unit
tSCLK 1/fSCLK) must greater than equal tCCLK. Guaranteed tSCLK Table page
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Clock Reset Timing
Table Figure describe clock reset operations. Absolute Maximum Ratings Page combinations CLKIN clock multipliers must select core/peripheral clocks that exceed maximum operating conditions. Table Clock Reset Timing
Parameter Timing Requirements tCKIN tCKINL tCKINH tWRST
CLKIN Period1, CLKIN Pulse CLKIN High Pulse RESET Asserted Pulse Width Low4 20.0 tCKIN
100.0
Unit
Applies bypass mode non-bypass mode. PLL_CTL register set, then maximum tCKIN period CLKIN frequency must change fly. Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including startup time external clock oscillator).
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
Figure Clock Reset Timing
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ADSP-BF538/ADSP-BF538F
Asynchronous Memory Read Cycle Timing
Table Table Page Figure Figure Page describe asynchronous memory read cycle operations synchronous asynchronous ARDY. Table Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter Timing Requirements tSDAT tHDAT tSARDY tHARDY
DATA15-0 Setup Before CLKOUT DATA15-0 Hold After CLKOUT ARDY Setup Before Falling Edge CLKOUT ARDY Hold After Falling Edge CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tSARDY
ARDY
tHARDY
tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing with Synchronous ARDY
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ADSP-BF538/ADSP-BF538F
Table Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter Timing Requirements tSDAT tHDAT tDANR tHAA
DATA15-0 Setup Before CLKOUT DATA15-0 Hold After CLKOUT ARDY Negated Delay from AMSx Asserted1 ARDY Asserted Hold After Negated Output Delay After CLKOUT Output Hold After CLKOUT2
Unit
tSCLK
number programmed setup cycles, number programmed read access cycles. Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
HOLD CYCLE ACCESS EXTENDED
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tHAA tDANR
ARDY
tSDAT tHDAT
DATA15-0 READ
Figure Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
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ADSP-BF538/ADSP-BF538F
Asynchronous Memory Write Cycle Timing
Table Table Page Figure Figure Page describe asynchronous memory write cycle operations synchronous asynchronous ARDY. Table Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter Timing Requirements tSARDY tHARDY tDDAT tENDAT
ARDY Setup Before Falling Edge CLKOUT ARDY Hold After Falling Edge CLKOUT DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT Output Hold After CLKOUT1
Unit
Switching Characteristics
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
ACCESS EXTENDED CYCLE
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
SARDY
ARDY
SARDY ENDAT
DATA15-0 WRITE DATA
HARD
HARDY
DDAT
Figure Asynchronous Memory Write Cycle Timing with Synchronous ARDY
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Table Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter Timing Requirements tDANR tHAA tDDAT tENDAT
ARDY Negated Delay from AMSx Asserted1 ARDY Asserted Hold After Negated DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT2 Output Hold After CLKOUT2
tSCLK
Unit
Switching Characteristics
number programmed setup cycles, number programmed write access cycles. Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
ACCESS EXTENDED
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tDANW
tHAA
ARDY
ENDAT
DATA15-0 WRITE DATA
tDDAT
Figure Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
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ADSP-BF538/ADSP-BF538F
SDRAM Interface Timing
Table SDRAM Interface Timing
Parameter Timing Requirements tSSDAT tHSDAT tSCLK tSCLKH tSCLKL tDCAD tHCAD tDSDAT tENSDAT
DATA Setup Before CLKOUT DATA Hold After CLKOUT CLKOUT Period CLKOUT Width High CLKOUT Width Command, ADDR, Data Delay After CLKOUT1 Command, ADDR, Data Hold After CLKOUT1 Data Disable After CLKOUT Data Enable After CLKOUT
Unit
Switching Characteristics
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
SCLK
CLKOUT
tSCLKH
tSSDAT HSDAT
DATA (IN)
tSCLKL
tDCAD tENSDAT
DATA(OUT)
tHCAD
DCAD
CMND ADDR (OUT)
HCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
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External Port Request Grant Cycle Timing
Table Table Page Figure Figure Page describe external port request grant cycle operations synchronous asynchronous Table External Port Request Grant Cycle Timing with Synchronous
Parameter Timing Requirements tDBG tEBG tDBH tEBH Setup Falling Edge CLKOUT Falling Edge CLKOUT Deasserted Hold Time CLKOUT AMSx, Address, ARE/AWE Disable CLKOUT AMSx, Address, ARE/AWE Enable CLKOUT High High Setup CLKOUT High Deasserted Hold Time CLKOUT High High Setup CLKOUT High Deasserted Hold Time Unit
Switching Characteristics
CLKOUT
AMSx
ADDR19-1 ABE1-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing with Synchronous
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Table External Port Request Grant Cycle Timing with Asynchronous
Parameter Timing Requirement tWBR tDBG tEBG tDBH tEBH Pulse Width CLKOUT AMSx, Address, ARE/AWE Disable CLKOUT AMSx, Address, ARE/AWE Enable CLKOUT High High Setup CLKOUT High Deasserted Hold Time CLKOUT High High Setup CLKOUT High Deasserted Hold Time tSCLK Switching Characteristics Unit
CLKOUT
tWBR
AMSx
ADDR19-1 ABE1-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing with Asynchronous
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ADSP-BF538/ADSP-BF538F
Parallel Peripheral Interface Timing
Table Figure Figure Figure Figure describe Parallel Peripheral Interface operations. Table Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW tPCLK tSFSPE tHRSPE tSDRPE tHDRPE tDFSPE tHOFSPE tDDTPE tHDTPE
PPI_CLK Width PPI_CLK Period
Unit
15.0 10.0 10.0
External Frame Sync Setup Before PPI_CLK External Frame Sync Hold After PPI_CLK Receive Data Setup Before PPI_CLK Receive Data Hold After PPI_CLK Internal Frame Sync Delay After PPI_CLK Internal Frame Sync Hold After PPI_CLK Transmit Data Delay After PPI_CLK Transmit Data Hold After PPI_CLK
Switching Characteristics-GP Output Frame Capture Modes
PPI_CLK frequency cannot exceed fSCLK/2.
FRAME SYNC DRIVEN POLC PPI_CLK
DATA0 SAMPLED
PPI_CLK POLC tDFSPE POLS PPI_FS1 POLS
HOFSPE
POLS PPI_FS2 POLS tSDRPE tHDRPE
PPI_DATA
Figure Mode with Internal Frame Sync Timing
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FRAME SYNC SAMPLED DATA0
DATA0 SAMPLED PPI_CLK POLC PPI_CLK POLC
DATA1 SAMPLED
tSFSPE POLS PPI_FS1 POLS
HFSPE
POLS PPI_FS2 POLS
SDRPE
HDRPE
PPI_DATA
Figure Mode with External Frame Sync Timing
FRAME SYNC SAMPLED PPI_CLK POLC PPI_CLK POLC tHFSPE POLS PPI_FS1 POLS
SFSPE
DATA0 DRIVEN
POLS PPI_FS2 POLS tHDTPE
PPI_DATA
DATA0
DDTPE
Figure Mode with External Frame Sync Timing
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FRAME SYNC REFERENCED THIS CLOCK EDGE PPI_CLK POLC PPI_CLK POLC tHOFSPE POLS PPI_FS1 POLS
DFSPE
DATA0 DRIVEN
POLS PPI_FS2 POLS
DDTPE
HDTPE
PPI_DATA
DATA0
Figure Mode with Internal Frame Sync Timing
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ADSP-BF538/ADSP-BF538F
Serial Port Timing
Table through Table Page Figure Page through Figure Page describe Serial Port operations. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE tHRSE tSDRE tHDRE tSCLEW tSCLKE tDFSE tHOFSE tDDTE tHDTE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) Receive Data Setup Before RSCLKx1 Receive Data Hold After RSCLKx TSCLKx/RSCLKx Width TSCLKx/RSCLKx Period TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 Transmit Data Delay After TSCLKx Transmit Data Hold After TSCLKx2
Unit
15.0 10.0 10.0
Switching Characteristics
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
Parameter Timing Requirements tSFSI tHFSI tSDRI tHDRI tSCLKEW tSCLKE tDFSI tHOFSI tDDTI tHDTI tSCLKIW
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 Receive Data Setup Before RSCLKx1 Receive Data Hold After RSCLKx1 TSCLKx/RSCLKx Width TSCLKx/RSCLKx Period TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx) Transmit Data Delay After TSCLKx2 Transmit Data Hold After TSCLKx TSCLKx/RSCLKx Width
Unit
-1.5 -1.5 15.0 -1.0 -2.0
Switching Characteristics
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Enable Three-State
Parameter Switching Characteristics tDTENE tDDTTE tDTENI tDDTTI
Data Enable Delay from External TSCLKx1 Data Disable Delay from External TSCLKx Data Enable Delay from Internal TSCLKx1 Data Disable Delay from Internal TSCLKx1
Unit
10.0 -2.0
Referenced drive edge.
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Table External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE tDTENLFS
Data Delay from Late External TFSx External RFSx with Data Enable from late
10.0
Unit
TFSx enable TFSx valid follow tDTENLFS tDDTLFSE. external RFSx/TFSx setup RSCLKx/TSCLKx tSCLKE/2, then tDDTTE/I tDTENE/I apply; otherwise tDDTLFSE tDTENLFS apply.
DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE.
Figure Serial Ports
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EXTERNAL RFSx WITH DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
LATE EXTERNAL TFSx DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
Figure External Late Frame Sync
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Serial Peripheral Interface Ports-Master Timing
Table Figure describe ports master operations. Table Serial Peripheral Interface (SPI) Ports-Master Timing
Parameter Timing Requirements tSSPIDM tHSPIDM tSDSCSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tDDSPIDM tHDSPIDM Data Input Valid SCKx Edge (Data Input Setup) SCKx Sampling Edge Data Input Invalid SPIxSELy First Edge Serial Clock High Period Serial Clock Period Serial Clock Period Last SCKx Edge SPIxSELy High Sequential Transfer Delay SCKx Edge Data Valid (Data Delay) SCKx Edge Data Invalid (Data Hold) -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 -1.0 +4.0 Unit
Switching Characteristics
SPIxSELy (OUTPUT)
tSDSCIM
SCKx (CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCKx (CPOL (OUTPUT)
tSPICHM
tDDSPIDM
MOSIx (OUTPUT) CPHA MISOx (INPUT)
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
tSSPIDM
VALID
tHSPIDM
tDDSPIDM
MOSIx (OUTPUT) CPHA
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
VALID
MISOx (INPUT)
Figure Serial Peripheral Interface (SPI) Ports-Master Timing
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Serial Peripheral Interface Ports-Slave Timing
Table Figure describe port's slave operations. Table Serial Peripheral Interface (SPI) Ports-Slave Timing
Parameter Timing Requirements tSPICHS tSPICLS tSPICLK tHDS tSPITDS tSDSCI tSSPID tHSPID tDSOE tDSDHI tDDSPID tHDSPID Serial Clock High Period Serial Clock Period Serial Clock Period Last SCKx Edge SPIxSS Asserted Sequential Transfer Delay SPIxSS Assertion First SCKx Edge Data Input Valid SCKx Edge (Data Input Setup) SCKx Sampling Edge Data Input Invalid SPIxSS Assertion Data Active SPIxSS Deassertion Data High impedance SCKx Edge Data Valid (Data Delay) SCKx Edge Data Invalid (Data Hold) 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 Unit
Switching Characteristics
SPIxSS (INPUT)
tSPICHS
SCKx (CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCKx (CPOL (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
MISOx (OUTPUT) CPHA MOSIx (INPUT)
tSSPID
VALID
tHSPID
tSSPID
tHSPID
VALID
tDSOE
MISOx (OUTPUT) CPHA MOSIx (INPUT)
tDDSPID
tDSDHI
tHSPID tSSPID
VALID VALID
Figure Serial Peripheral Interface (SPI) Ports-Slave Timing
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General-Purpose Port Timing
Table Figure describe general-purpose operations. Table General-Purpose Port Timing
Parameter Timing Requirement tWFI tGPOD Port Input Pulse Width Port Output Delay From CLKOUT tSCLK Switching Characteristic Unit
CLKOUT
tGPOD
OUTPUT
tGPOD
OUTPUT
tWFI
INPUT
Figure General-Purpose Port Cycle Timing
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ADSP-BF538/ADSP-BF538F
Timer Cycle Timing
Table Figure describe timer expired operations. input signal asynchronous "width capture mode" "external clock mode" absolute maximum input frequency fSCLK/2 MHz. Table Timer Cycle Timing
Parameter Timing Characteristics tHTO
Timer Pulse Width Input Low1 (Measured SCLK Cycles) Timer Pulse Width Input High1 (Measured SCLK Cycles) Timer Pulse Width Output (measured SCLK Cycles)
Unit SCLK SCLK
Switching Characteristic (232 SCLK
minimum pulse widths apply TMRx input pins width capture external clock modes. They also apply (TACLK) PPI_CLK (TMRCLK) input pins output mode.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE EXTERNAL CLOCK MODES)
Figure Timer PWM_OUT Cycle Timing
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ADSP-BF538/ADSP-BF538F
JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations. Table JTAG Port Timing
Parameter Timing Requirements tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW tDTDO tDSYS
Period TDI, Setup Before High TDI, Hold After High System Inputs Setup Before High1 System Inputs Hold After High
Unit
TRST Pulse Width2 (Measured Cycles) Delay from System Outputs Delay After Low3,4
Switching Characteristics
System Inputs=ARDY, BMODE1-0, DATA15-0, DR0PRI, DR0SEC, NMI, PF15-0, PPI_CLK, PPI3-0, SCL1-0, SDA1-0, SCK2-0, MISO2-0, MOSI2-0, SPI1SS, SPI1SEL1, SPI2SS, SPI2SEL1, RX2-0, TX2-1, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, TSCLK3-0, DR3PRI, DR3SEC, RSCLK3-0, RFS3-0, TFS3-0, CANTX, CANRX, RESET, PC9-4, GPW, TMR2-0. Maximum System Outputs AMS, AOE, ARE, AWE, ABE, DATA15-0, PF15-0, PC9-5, PPI3-0, SPI1SS, SPI1SEL1, SCK2-0, MISO2-0, MOSI2-0, SPI2SS, SPI2SEL1, RX2-1, TX2-0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3-0, RFS3-0, TSCLK3-0, TFS3-0, CANTX, CLKOUT, SA10, SCAS, SCKE, SMS, SRAS, SWE, TMR2-0. System Open-Drain Outputs: CANRX (when configured PC1) PC4.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Port Timing
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ADSP-BF538/ADSP-BF538F
OUTPUT DRIVE CURRENTS
Figure through Figure Page show typical currentvoltage characteristics output drivers ADSPBF538/ADSP-BF538F processors. curves represent current drive capability output drivers function output voltage.
SOURCE CURRENT (mA)
2.25V
SOURCE CURRENT (mA)
2.50V 2.75V
2.25V 2.50V 2.75V
-100
-100
-150
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
3.0V 3.3V 3.6V
SOURCE CURRENT (mA)
SOURCE TAGE
Figure Drive Current (Low VDDEXT)
3.0V
SOURCE CURRENT (mA)
-100
3.3V
-150 -200
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
-100
2.25V 2.50V 2.75V
SOURCE CURRENT (mA)
-150
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
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ADSP-BF538/ADSP-BF538F
SOURCE CURRENT (mA)
3.0V 3.3V 3.6V
SOURCE CURRENT (mA)
2.25V 2.50V 2.75V
SOURCE VOLTAGE
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
Figure Drive Current (Low VDDEXT)
SOURCE CURRENT (mA)
2.25V 2.50V 2.75V
SOURCE CURRENT (mA)
3.0V 3.3V 3.6V
SOURCE VOLTAGE
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
Figure Drive Current (High VDDEXT)
3.0V 3.3V 3.6V
SOURCE CURRENT (mA)
-100
-150
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
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ADSP-BF538/ADSP-BF538F
POWER DISSIPATION
Many operating conditions affect power dissipation. System designers should refer Estimating Power ADSP-BF538/ADSP-BF538F Blackfin Processors (EE-298) Analog Devices website (www.analog.com)-use site search "EE-298." This document provides detailed information optimizing your design lowest power. ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Reference Manual definitions various operating modes instructions minimize system power. DECAY time tDECAY calculated with test loads with equal VDDEXT (nominal) V/3.3 time tDIS+_MEASURED interval from when reference signal switches, when output voltage decays from measured output high output voltage.
Example System Hold Time Calculation
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-BF538/ADSP-BF538F processor's output voltage input threshold device requiring hold time. total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY plus various output disable times specified Timing Specifications Page (for example tDSDAT SDRAM write cycle shown Table Page 32).
TEST CONDITIONS
timing parameters appearing this data sheet were measured under conditions described this section. Figure shows measurement point measurements (except output enable/disable). measurement point VMEAS VDDEXT (nominal) V/3.3
INPUT OUTPUT
1.5V
1.5V
REFERENCE SIGNAL
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
tDIS_MEASURED tDIS
(MEASURED) (MEASURED)
tENA-MEASURED tENA
Output Enable Time Measurement
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when reference signal reaches high voltage level point when output starts driving shown right side Figure "Output Enable/Disable," Page time tENA_MEASURED interval, from when reference signal switches, when output voltage reaches VTRIP(high) VTRIP(low). VTRIP(high) VTRIP(low) VDDEXT (nominal) V/3.3 Time tTRIP interval from when output starts driving when output reaches VTRIP(high) VTRIP(low) trip voltage. Time tENA calculated shown equation: ENA_MEASURED TRIP multiple pins (such data bus) enabled, measurement value that first start driving.
(MEASURED)
2.0V (MEASURED) 1.0V (MEASURED)
(MEASURED)
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE APPROXIMATELY 1.5V.
Figure Output Enable/Disable
OUTPUT 30pF
1.5V
Figure Equivalent Device Loading Measurements (Includes Fixtures)
Output Disable Time Measurement
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. output disable time tDIS difference between tDIS_MEASURED tDECAY shown left side Figure DIS_MEASURED DECAY time voltage decay dependent capacitive load load current This decay time approximated equation:
Rev. Page January 2008
ADSP-BF538/ADSP-BF538F
Capacitive Loading
RISE FALL TIME (10% 90%)
Output delays holds based standard capacitive loads: pins (see Figure 41). VLOAD VDDEXT (nominal) V/3.3 Figure through Figure Page show output rise fall times vary with capacitance. delay hold specifications given should derated factor derived from these figures. graphs these figures linear outside ranges shown.
RISE TIME
FALL TIME
RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Min)
RISE FALL TIME (10% 90%)
LOAD CAPACITANCE (pF)
RISE TIME
FALL TIME
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Min)
RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Max)
LOAD CAPACITANCE (pF)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Max)
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January 2008
ADSP-BF538/ADSP-BF538F
RISE FALL TIME (10% 90%) RISE FALL TIME (10% 90%) FALL TIME
RISE TIME
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Min)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Min)
RISE FALL TIME (10% 90%) RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME LOAD CAPACITANCE (pF)
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Max)
Figure Typical Output Rise Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Max)
Rev.
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January 2008
ADSP-BF538/ADSP-BF538F
Values provided package comparison printed circuit board design considerations. used first order approximation equation where:
FALL TIME
FALL TIME (10% 90%)
Ambient temperature Values provided package comparison printed circuit board design considerations when external heatsink required. Values provided package comparison printed circuit board design considerations.
LOAD CAPACITANCE (pF)
Figure Typical Output Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Min)
Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6, junction-to-board measurement complies with JESD51-8. junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). measurements 2S2P JEDEC test board. Table Thermal Characteristics BC-316 Without Flash
Parameter
FALL TIME
Condition linear flow linear flow linear flow linear flow linear flow linear flow
Typical 21.6 18.8 18.1 5.36 0.13 0.25 0.25
Unit
FALL TIME (10% 90%)
Table Thermal Characteristics BC-316 With Flash
Parameter Condition linear flow linear flow linear flow linear flow linear flow linear flow Typical 20.9 18.1 17.4 5.01 0.12 0.24 0.24 Unit
LOAD CAPACITANCE (pF)
Figure Typical Output Fall Times (10% 90%) Load Capacitance Driver VDDEXT (Max)
THERMAL CHARACTERISTICS
determine junction temperature application printed circuit board CASE where Junction temperature TCASE Case temperature measured customer center package.
From Table
Power dissipation (see Power Dissipation Page method calculate
Rev.
Page
January 2008
ADSP-BF538/ADSP-BF538F
316-BALL CSP_BGA BALL ASSIGNMENTS
Table Page lists CSP_BGA ball assignment ball number. Table Page lists CSP_BGA ball assignment signal.
BALL
BALL VDDINT VDDEXT VDDRTC VROUTx
VDDINT VDDRTC VDDEXT VROUTx
FLASH CONTROL
FLASH CONTROL
Note: ADSP-BF538 (FCE RESET) ADSP-538F.
Note: ADSP-BF538 (FCE RESET) ADSP-538F.
Figure 316-Ball CSP_BGA Ball Configuration (Bottom View) Figure 316-Ball CSP_BGA Ball Configuration (Top View)
Rev.
Page
January 2008
ADSP-BF538/ADSP-BF538F
Table 316-Ball CSP_BGA Ball Assignment (Numerically Ball Number)
Ball Signal PF10 PF11 PPI_CLK PPI0 PPI2 PF15 PF13 VDDRTC RTXO RTXI CLKIN XTAL VROUT1 PPI1 PPI3 PF14 PF12 SCL0 SDA0 CANRX CANTX RESET VDDEXT VROUT0 Ball Signal SPI2SEL1 SPI2SS MOSI2 MISO2 SCK2 VDDINT SPI1SEL1 MISO1 SPI1SS MOSI1 SCK1 SCKE DT1SEC ARDY MISO0 Ball Signal DT3PRI SCK0 MOSI0 DT0SEC CLKOUT SRAS DT1PRI TSCLK1 DR1SEC SCAS TFS1 DR1PRI DR0SEC Ball Signal AMS0 AMS2 SA10 RFS1 TMR2 VDDEXT AMS3 AMS1 RSCLK1 TMR1 TSCLK3 DT0PRI TMR0 VDDEXT VDDINT TFS3 Ball Signal ABE0 ABE1 TFS0 DR0PRI VDDEXT VDDINT DT3SEC ADDR1 ADDR2 TSCLK0 RFS0 VDDEXT VDDINT DR3SEC ADDR3 ADDR4 RSCLK0 VDDEXT VDDINT DR3PRI ADDR5 ADDR6 Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT RFS3 ADDR7 ADDR8 TRST VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT RSCLK3 ADDR9 ADDR10 BMODE1 BMODE0 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT DR2SEC DT2SEC ADDR11 ADDR12 Ball Signal DATA15 DATA13 DATA11 DATA9 DATA7 DATA5 DATA3 DATA1 RSCLK2 DR2PRI DT2PRI ADDR18 ADDR15 ADDR13 ADDR14 DATA14 DATA12 DATA10 DATA8 DATA6 DATA4 DATA2 DATA0 RFS2 TSCLK2 TFS2 FRESET SCL1 SDA1 ADDR19 ADDR17 ADDR16
Rev.
Page
January 2008
ADSP-BF538/ADSP-BF538F
Table 316-Ball CSP_BGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 CANRX CANTX CLKIN CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Ball Signal DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DR0PRI DR0SEC DR1PRI DR1SEC DR2PRI DR2SEC DR3PRI DR3SEC DT0PRI DT0SEC DT1PRI DT1SEC DT2PRI DT2SEC DT3PRI DT3SEC FRESET Ball Signal Ball Signal Ball Signal MISO0 MISO1 MISO2 MOSI0 MOSI1 MOSI2 PF10 PF11 PF12 PF13 PF14 PF15 PPI_CLK PPI0 PPI1 PPI2 PPI3 RESET Ball Signal RFS0 RFS1 RFS2 RFS3 RSCLK0 RSCLK1 RSCLK2 RSCLK3 RTXI RTXO SA10 SCAS SCK0 SCK1 SCK2 SCKE SCL0 SCL1 SDA0 SDA1 SPI1SEL1 SPI1SS SPI2SEL1 SPI2SS SRAS TFS0 TFS1 TFS2 TFS3 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 TSCLK2 TSCLK3 Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball
Rev.
Page
January 2008
ADSP-BF538/ADSP-BF538F
OUTLINE DIMENSIONS
Dimensions outline dimensions figures shown millimeters.
17.00 BALL INDICATOR
15.20 0.80 BALL PITCH BALL
VIEW
BOTTOM VIEW
0.30
0.12 COPLANARITY 1.70 SIDE VIEW DETAIL 0.50 BALL DIAMETER 0.45 0.40 SEATING PLANE DETAIL
NOTES: DIMENSIONS MILLIMETERS. COMPLIANT JEDEC REGISTERED OUTLINE MO-205, VARIATION WITH EXCEPTION BALL DIAMETER. CENTER DIMENSIONS NOMINAL.
Figure 316-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-316)
Rev.
Page
January 2008
ADSP-BF538/ADSP-BF538F
SURFACE-MOUNT DESIGN
Table provided design. industrystandard design recommendations, refer IPC-7351, Generic Requirements Surface-Mount Design Land Pattern Standard. Table Data with Surface-Mount Design
Package 316-Ball CSP_BGA (BC-316) Solder Mask Ball Attach Type Opening Ball Size Solder Mask Defined 0.40 diameter 0.50 diameter
ORDERING GUIDE
Model ADSP-BF538BBCZ-4A ADSP-BF538BBCZ-5A ADSP-BF538BBCZ-4F4 ADSP-BF538BBCZ-4F8 ADSP-BF538BBCZ-5F4 ADSP-BF538BBCZ-5F8
Temperature Range2
Instruction Flash Rate (Max) Memory 512K byte byte 512K byte byte
Operating Voltage (Nominal)
Package Description
Package Option BC-316 BC-316 BC-316 BC-316 BC-316 BC-316
internal/ 316-Ball CSP_BGA 1.25 internal/ 316-Ball CSP_BGA internal/ 316-Ball CSP_BGA internal/ 316-Ball CSP_BGA 1.25 internal/ 316-Ball CSP_BGA 1.25 internal/ 316-Ball CSP_BGA
RoHS Compliant Part. Referenced temperature ambient temperature.
©2008 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D06700-0-1/08(A)
Rev.
Page
January 2008
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