EBE51FD8AGFD EBE51FD8AGFN Density: 512MB Organization words bits,

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EBE51FD8AGFD EBE51FD8AGFN Density: 512MB Organization words bits,

Datasheet Thumbnail

Top Searches for this datasheet

512MB Fully Buffered DIMM
EBE51FD8AGFD EBE51FD8AGFN
Density: 512MB Organization words bits, rank Mounting pieces 512M bits DDR2 SDRAM sealed FBGA Package 240-pin fully buffered, socket type dual line memory module (FB-DIMM) height: 30.35mm Lead pitch: 1.00mm Advanced Memory Buffer (AMB): 655-ball FCBGA Lead-free (RoHS compliant) Power supply DDR2 SDRAM: 1.8V 0.1V AMB: 1.5V 0.075V/-0.045 Data rate: 667Mbps/533Mbps (max.) Four internal banks concurrent operation (components) Interface: SSTL_18 Burst lengths (BL): /CAS Latency (CL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
JEDEC standard Card Design Industry Standard Advanced Memory Buffer (AMB) High-speed differential point-to-point link interface 1.5V (JEDEC draft spec) north-bound (NB) high speed serial lanes south-bound (SB) high speed serial lanes Various features/modes: MemBIST IBIST test functions Transparent mode direct access mode DRAM testing Interface thermal sensor status indicator Channel error detection reporting Automatic DDR2 SDRAM channel calibration (serial presence detect) with 1piece byte serial EEPROM Note: Warranty void removed DIMM heat spreader.
Performance
FB-DIMM System clock frequency 167MHz 133MHz Speed grade PC2-5300F PC2-4200F Peak channel throughput 8.0GByte/s 6.4GByte/s FB-DIMM link data rate 4.0Gbps 3.2Gbps DDR2 SDRAM Speed Grade DDR2-667 (5-5-5) DDR2-533 (4-4-4) data rate 667Mbps 533Mbps
Document E0869E30 (Ver. 3.0) Date Published August 2006 Japan Printed Japan URL: http://www.elpida.com Elpida Memory, Inc. 2006
EBE51FD8AGFD, EBE51FD8AGFN
Ordering Information
Part number EBE51FD8AGFD-6E-E EBE51FD8AGFD-5C-E EBE51FD8AGFN-6E-E EBE51FD8AGFN-5C-E DIMM speed grade PC2-5300F PC2-4200F PC2-5300F PC2-4200F Component JEDEC speed (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-667 (5-5-5) DDR2-533 (4-4-4) Package Mounted devices* EDE5108AGSE-6E-E EDE5108AGSE-5C-E 240-pin FB-DIMM EDE5108AGSE-6E-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E
240-pin FB-DIMM EDE5108AGSE-6E-E
Note: Please refer EDE5104AGSE, EDE5108AGSE datasheet (E0715E) detailed operation part timing waveforms
Part Number
Elpida Memory
Type Module
Environment code Lead Free (RoHS compliant)
Product Family DDR2
DRAM Speed Grade DDR2-667 (5-5-5) DDR2-533 (4-4-4)
Device Information Integrated Device Technology, Inc. Intel Corporation
Density Rank 512MB/1-rank Module Type Fully Buffered Mono Density 512Mbit
Mono Organization
Module Outline 240-pin DIMM
Rev. (Mono)
Power Supply, Interface 1.8V, SSTL_1.8
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Advanced Memory Buffer Overview
Advanced Memory Buffer (AMB) reference design complies with FB-DIMM Architecture Protocol Specification. supports DDR2 SDRAM main memory. allows buffering memory traffic support large memory capacities. memory control DRAM resides host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, power management. interface responsible handling FB-DIMM channel memory requests from local DIMM forwarding requests other DIMMs FB-DIMM channel. FB-DIMM provides high memory bandwidth, large capacity channel solution that narrow host interface. FB-DIMMs commodity DRAMs isolated from channel behind buffer DIMM. memory capacity devices channel total memory capacity scales with DRAM density. buffer that isolates DRAMs from channel.
Advanced Memory Buffer Functionality will perform following FB-DIMM channel functions. Supports channel initialization procedures defined initialization chapter FB-DIMM Architecture Protocol Specification align clocks frame boundaries, verify channel connectivity, identify DIMM position. Supports forwarding southbound northbound frames, servicing requests directed specific DIMM, defined protocol chapter, merging return data into northbound frames. resides last DIMM channel, initializes northbound frames. Detects errors channel reports them host memory controller. Support FB-DIMM configuration register defined register chapters. Acts DRAM memory buffer read, write, configuration accesses addressed DIMM. Provides read buffer FIFO write buffer FIFO. Supports SMBus protocol interface access configuration registers. Provides logic support MemBIST IBIST design test functions. Provides register interface thermal sensor status indicator. Functions repeater extend maximum length FB-DIMM links.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Advanced Memory Buffer Block Diagram
Southbound Data Southbound Data
Reference clock
Data merge RE-time Re-synch
Demux
PISO
/RESET
Reset control Thermal sensor failover Command decoder check Link init control CSRs
IBIST-RX
Init patterns
IBIST-TX
DRAM clock DRAM clock Command DRAM interface Data DRAM address command copy1 DRAM address command copy2 DRAM data strobes
logic DRAM Command state controller CSRs
Core controller CSRs
Write data FIFO External MemBIST calibration Sync idle pattern generator
IBIST-TX IBIST-RX
Data
Data generator Read FIFO controller
Buffer
Link init control CSRs
SMBus
SMBus controller
failover PISO
Demux
Re-synch RE-time Data merge
Northbound Data
Northbound Data
Note: This figure conceptual block diagram AMB's data flow clock domains.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Interfaces Figure Block Diagram Interfaces shows interfaces. They consist FB-DIMM links, DDR2 channel SMBus interface. Each FB-DIMM link connects host memory controller adjacent FB-DIMM. DDR2 channel supports direct connection DDR2 SDRAMs FB-DIMM.
Memory Interface
Link Link
Link Link
Block Diagram Interfaces
Interface Topology FB-DIMM channel uses daisy-chain topology provide expansion from single DIMM channel DIMMs channel. host sends data southbound link first DIMM where received redriven second DIMM. southbound data path each DIMM receives data again re-drives data next DIMM until last DIMM receives data. last DIMM chain initiates transmission data direction host (a.k.a. northbound). northbound data path each DIMM receives data re-drives data next DIMM until host reached.
Host Southbound Nourthbound
Block Diagram FB-DIMM Channel Southbound Northbound Paths
Preliminary Data Sheet E0869E30 (Ver. 3.0)
Secondary optional next
Primary Host Direction
EBE51FD8AGFD, EBE51FD8AGFN
High-Speed Differential Point-to-Point Link Interfaces supports FB-DIMM channel consisting bidirectional link interfaces using high-speed differential point-to-point electrical signaling. southbound input link lanes wide carries commands write data from host memory controller adjacent DIMM host direction. southbound output link forwards this same data next FB-DIMM. northbound input link lanes wide carries read return data status information from next FB-DIMM chain back towards host. northbound output link forwards this information back towards host multiplexes read return data status information that generated internally. Data commands sent DRAMs travel southbound primary differential signal line pairs. Data received from DRAMs status information travel northbound primary differential pairs. Data commands sent adjacent DIMM upstream repeated travel further southbound secondary differential pairs. Data status information received from adjacent DIMM upstream travel further northbound secondary differential pairs.
DDR2 Channel DDR2 channel supports direct connection DDR2 SDRAMs. DDR2 channel supports ranks eight banks with row/column request, data, eight check-bit signals. There copies address command signals support DIMM routing electrical requirements. Four transfer bursts driven data check-bit lines 800MHz. Propagation delays between read data/check-bit strobe lanes given channel differ. Each strobe calibrated hardware state machines using write/read trial error. Hardware aligns read data check-bits single core clock. provides four copies command clock phase references (CLK [3:0]) write data/check-bit strobes (DQSs) each DRAM nibble.
SMBus Slave interface supports SMBus interface allow system access configuration register independent FB-DIMM link. will never master SMBus, only slave. Serial SMBus data transfer supported 100kHz. SMBus access requirement boot link strength, frequency other parameters needed insure robust configurations. also required diagnostic support when link down. SMBus address straps located DIMM connector used unique
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Block Diagram
/CS0 /DQS0 DQS0
/RDQS /DQS
/DQS4 DQS4
/RDQS /DQS
DQS9 /DQS1 DQS1 DQS10 DQ15 /DQS2 DQS2
RDQS
DQS13 DQ32 DQ39 /DQS5 DQS5
RDQS
/RDQS RDQS
/DQS
DQS14 DQ40 DQ47 /DQS6 DQS6
/RDQS RDQS
/DQS
/RDQS
/DQS
/RDQS
/DQS
DQS11 DQ16 DQ23 /DQS3 DQS3 DQS12 DQ24 DQ31
RDQS
DQS15 DQ48 DQ55 /DQS7 DQS7
RDQS
/RDQS RDQS
/DQS
DQS16 DQ56 DQ63 /DQS8
/DQS /RDQS RDQS
PN13 /PN0 /PN13 /PS0 /PS9 DQ63 DQS0 DQS17 /DQS0 /DQS8 /RESET SCK/ /SCK
SN13 /SN0 /SN13 /SS0 /SS9
DQS8 DQS17
/RDQS RDQS /DQS
/CS0 (all SDRAMs) CKE0 (all SDRAMs)
(all SDRAMs) BA0, (all SDRAMs) (all SDRAMs) /RAS (all SDRAMs) /CAS (all SDRAMs) (all SDRAMs)
Serial
VDDSPD VREF
Teminators SPD, SPD,
address/command/control/clock
512M bits DDR2 SDRAM
Notes: bytes EEPROM wiring changed within byte. There physical copies each address/command/control/clock
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Configurations
Front side
Back side
Front side Name VID1 Name /PN5 PN13 /PN13 PN12 /PN12 /PN6 /PN7 /PN8 /PN9 PN10 /PN10 PN11 /PN11 Name /PS0 /PS1 /PS2 /PS3 /PS4 /PS9 /PS5 /PS6 /PS7 /PS8 Name
Back side Name VID0 Name /SN5 SN13 /SN13 SN12 /SN12 /SN6 /SN7 /SN8 /SN9 SN10 /SN10 SN11 /SN11 Name /SS0 /SS1 /SS2 /SS3 /SS4 /SS9 /SS5 /SS6 /SS7 /SS8 Name /SCK VDDSPD
/RESET /PN0 /PN1 /PN2 /PN3 /PN4
M_TEST /SN0 /SN1 /SN2 /SN3 /SN4
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Description
name SCK, /SCK PN13, /PN0 /PN13 PS9, /PS0 /PS9 SN13, /SN0 /SN13 SS9, /SS0 /SS9 SA2*
Type Input Output Input Input Output Input Input Output Input Input Input
Function System clock input Primary northbound data Primary southbound data Secondary northbound data Secondary southbound data Serial presence detect (SPD) clock input data SMBus address/data address inputs Voltage reset signal VREF margin test input connection core power channel interface power (1.5V) DRAM power DRAM power (1.8V) DRAM address, Command clock termination voltage (VDD/2) power (3.3V) Ground
VID0 VID1* /RESET M_TEST* VDDSPD
Input Power supply Power supply Power supply Power supply
Notes: They also used select DIMM number AMB. These pins must unconnected. Don't connect system.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative core power voltage relative DRAM interface power voltage relative Termination voltage relative Storage temperature Symbol VIN/VOUT Tstg Value -0.3 +1.75 -0.3 +1.75 -0.5 +2.30 -0.5 +2.30 +100 Unit Note
Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Temperature Conditions
Parameter SDRAM component case temperature component case temperature Symbol TC_DRAM TC_AMB Value Unit Note
Note: Supporting +85°C being able extend +95°C with doubling auto-refresh commands frequency 32ms period (tREFI 3.9µs) higher temperature self-refresh entry control EMRS required. Operating Conditions
Parameter supply voltage DDR2 SDRAM supply voltage Input termination voltage EEPROM supply voltage input high voltage input voltage RESET input high voltage RESET input voltage Leakage current (RESET) Leakage current (link) Symbol VDDSPD (DC) (DC) (DC) (DC) min. 1.455 0.48 typ. 1.50 0.50 max. 1.575 0.52 VDDSPD Unit Note
Notes: Applies signals. Applies CMOS signal /RESET. other related parameters, please refer high-speed differential link interface specification.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Component Timing purposes testing, following parameters utilized.
Parameter Assertion pass-thru timing deassertion pass-thru timing assertion duration Resample pass-thru time Resynch pass-thru Time lock Interval Frame lock Interval tBitLock tFrameLock Symbol propagate tEID min. typ. max. lock Units clks clks clks frames frames Note
Note: stands Electrical Idle. Power Specification Parameter Test Conditions
Frequency (Mbps) Parameter Symbol Power Supply @1.5V Idle Current, single last DIMM Idd_Idle_0 @1.8V Total @1.5V Idle Current, first DIMM Idd_Idle_1 @1.8V Total @1.5V Active Power Idd_Active_1 @1.8V Total @1.5V Active Power, Idd_Active_2 data pass through @1.8V Total @1.5V Training Idd_Training (for spec. @1.8V SPD) Total max. 2.60 1.02 5.37 3.40 1.02 6.63 3.90 2.65 10.52 3.70 1.02 7.11 4.00 0.99 7.53 max. 2.20 0.95 4.62 3.00 0.95 5.88 3.40 2.71 9.85 3.20 0.95 6.19 3.50 0.91 6.58 Unit state DRAM downstream DIMM, read, write. Primary secondary channels enabled. high. Command address lines stable. DRAM clock active. Primary secondary channels enabled. 100% toggle channel lanes DRAMs idle. high, Command address lines stable. DRAM clock active. state DRAM read, write. Primary secondary channels enabled. DRAM clock active, high. Conditions state, idle Primary channel enabled, Secondary channel disabled high. Command address lines stable. DRAM clock active. state, idle Primary secondary channels enabled high. Command address lines stable. DRAM clock active. Note
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Reference Clock Input Specifications*1
Parameter Reference clock frequency@ 3.2Gb/s (nominal 133.33MHz) Reference clock frequency@ Gb/s (nominal 166.67MHz) Single-ended maximum voltage Single-ended minimum voltage Differential voltage high Differential voltage Absolute crossing point VCross variation common mode Rising falling edge rates Mismatch between rise fall edge rates Duty cycle reference clock Ringback voltage threshold Allowed time before ringback Clock leakage current Clock input capacitance Clock input capacitance delta Transport delay Symbol fRefclk-3.2 fRefclk-4.0 Vmax Vmin VRefclk-diff-ih VRefclk-diff-il VCross VCross-delta VSCK-cm-acp-p ERRefclk-diff-Rise, ERRefclk-diff-Fall ERRefclk-Match TRefclk-Dutycycle VRB-diff TStable II_CK CI_CK CI_CK NSAMPLE Reference clock jitter (rms), filtered min. 126.67 158.33 -0.3 -100 -0.25
max. 133.40 166.75 1.15 -150 0.25
Units V/ns periods
Notes Difference between RefClk RefClk# input capacitance
TREF-JITTER-RMS
Reference clock jitter (peak-to-peak) TREF-SSCp-p spectrum clocking effects Reference clock jitter difference between TREF-JITTERadjacent DELTA
Notes: details, refer JEDEC specification "FB-DIMM High Speed Differential Link 1.5V". nominal reference clock frequency determined data frequency link divided times fixed multiplication factor FB-DIMM channel (6:1). fdata 2000MHz 4.0Gbps FBDIMM channel Measured with disabled. Enabling will reduce reference clock frequency. FB-DIMM agents will support frequencies; compliance frequency specifications only required those data rates that supported device under test. Measurement taken from single-ended waveform. Measurement taken from differential waveform. Defined maximum instantaneous voltage including overshoot. Defined minimum instantaneous voltage including undershoot. Measured crossing point where instantaneous voltage value rising edge REFCLK+ equals falling edge REFCLK-. Refers total variation from lowest crossing point highest, regardless which edge crossing. Refers crossing points this measurement. Defined total variation crossing voltages rising REFCLK+ falling REFCLK-. This maximum allowed variance particular system. majority reference clock common mode occurs high frequency (i.e., reference clock frequency).
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Measured from -150mV 150mV differential waveform. signal must monotonic through measurement region rise fall time. 300mV measurement window centered differential crossing. Edge rate matching applies rising edge rate REFCLK+ falling edge rate REFCLK-. measured using 75mV window centered median cross point where REFCLK+ rising meets REFCLK- falling. median crosspoint used calculate voltage thresholds oscilloscope uses edge rate calculations. rising edge rate REFCLK+ should compared falling edge rate REFCLK-. maximum allowed difference should exceed slowest edge Tstable time differential clock must maintain minimum ±150mV differential voltage after rising /falling edges before allowed droop back into ±100mV differential range. 16.Measured with single-ended input voltage Applies RefClk RefClk#. This parameter direct clock output parameter indirectly determines clock output parameter TREF-JITTER. transport delay difference time flight between associated data clock paths. data path defined from reference clock source, through data arrival data sampling point clock path defined from reference clock source clock arrival same sampling point. path delays caused copper trace routes, on-chip routing, on-chip buffering, etc. They include time-of-flight interpolators other clock adjustment mechanisms. They include phase delays caused finite loop bandwidth because these delays modeled transfer functions. Direct measurement phase jitter records over NSAMPLE periods impractical. expected that jitter will measured over smaller, statistically significant, sample size total jitter NSAMPLE samples extrapolated from estimate sigma random jitter components. Measured with enabled reference clock generator. "measured" after phase jitter filter. This number separate from receiver jitter budget that defined TRX-Total-MIN parameters.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Differential Transmitter Output Specifications*1
Parameter Differential peak-to-peak output voltage large voltage swing Differential peak-to-peak output voltage regular voltage swing Differential peak-to-peak output voltage small voltage swing common code output voltage large voltage swing common code output voltage small voltage swing De-emphasized differential output voltage ratio -3.5dB de-emphasis De-emphasized differential output voltage ratio -6dB de-emphasis Symbol VTX-DIFFp-p_L min. max. 1300 Unit Comments VTX-DIFFp-p VTX-D+ VTX-D- Measured note VTX-DIFFp-p VTX-D+ VTX-D- Measured note VTX-DIFFp-p VTX-D+ VTX-D- Measured note Defined VTX-CM (avg) |VTX-D+ VTX-D-|/2 Measured note Defined VTX-CM (avg) |VTX-D+ VTX-D-|/2 Measured note also note
VTX-DIFFp-p_R
VTX-DIFFp-p_S
VTX-CM_L
VTX-CM_S
VTX-DE-3.5-Ratio
-3.0 -5.0
-4.0 -7.0
VTX-DE-6.0-Ratio
VTX-CM-AC |VTX-D+ VTX-D-|/2 |VTX-D+ VTX-D-|/2 Measured note also note VTX-CM-AC |VTX-D+ VTX-D-|/2 |VTX-D+ VTX-D-|/2 Measured note also note VTX-CM-AC |VTX-D+ VTX-D-|/2 |VTX-D+ VTX-D-|/2 Measured note also note
peak-to-peak common mode output voltage large VTX-CM-ACp-p swing peak-to-peak common mode output voltage regular swing
VTX-CM-ACp-p
peak-to-peak common mode output voltage small VTX-CM-ACp-p swing Maximum single-ended voltage condition, Maximum single-ended voltage condition, only Maximum peak-to-peak differential voltage condition Single-ended voltage (w.r.t.VSS) D+/DMinimum width Maximum deterministic jitter Instantaneous pulse width
VTX-IDLE-SE
VTX-IDLE-SE-DC
VTX-IDLE-DIFFp-p VTX-SE TTX-Eye-MIN TTX-DJ-DD TTX-PULSE
0.85
Given 20%-80% voltage levels. Measured note
Differential output rise/fall TTX-RISE, time TTX-FALL Mismatch between rise TTX-RF-MISMATCH fall times Differential return loss Common mode return loss RLTX-DIFF RLTX-CM
Measured over 0.1GHz 2.4GHz. also note Measured over 0.1GHz 2.4GHz. also note
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Parameter Transmitter termination resistance Symbol min. max. Unit Comments RTX-Match-DC RTX-D-| (RTX-D+ RTX-D-) Bounds applied separately high output voltage states
D+/D- resistance difference
RTX-Match-DC
Lane-to-lane skew Lane-to-lane skew Maximum Drift (resync mode) Maximum Drift (resample mode only) Error Ratio
LTX-SKEW LTX-SKEW
TTX-DRIFT-RESYNC TTX-DRIFTRESAMPLE
Notes: details, refer JEDEC specification "FB-DIMM High Speed Differential Link 1.5V". Specified package pins into timing voltage compliance test load. Common-mode measurements performed using 101010 pattern. transmitter designer should artificially elevate common mode order meet this specification. This ratio VTX-DIFFp-p second following bits after transition divided VTX-DIFFp-p first after transition. De-emphasis shall disabled calibration state. Includes sources common mode noise. Single-ended voltages below that value that simultaneously detected interpreted Electrical Idle condition. Specified package pins into voltage compliance test load. Transmitters must meet both singleended differential output specifications. This specification, considered with VRX-IDLE-SE-DC, implies maximum 15mV single-ended offset between pins during electrical idle condition. This turn allows ground offset between adjacent FB-DIMM agents 26mV when worst case termination resistance matching considered. maximum value specified least (VTX-DIFFp-p VTX-CM (VTX-CM-ACp-p This number does include effects reference clock jitter. These timing specifications apply resync mode only. Defined dual-dirac deterministic jitter. Pulse width measured differential. components that contribute deterioration return loss structure which needs carefully designed. termination small signal resistance; tolerance across voltages from 100mV 400mV shall exceed with regard average values measured 100mV 400mV that pin. Lane Lane skew Transmitter pins component. Lane Lane skew Transmitter pins intermediate component (assuming zero Lane Lane skew Receiver pins incoming PORT). This static skew. FB-DIMM component allowed change lane lane phase relationship after initialization. Measured from reference clock edge center output eye. This specification must across specified voltage temperature ranges single component. Drift rate change significantly below tracking capability receiver. differential lane.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Differential Receiver Input Specifications*1
Parameter Differential peak-to-peak input voltage Maximum single-ended voltage condition Maximum single-ended voltage condition only) Maximum peak-to-peak differential voltage condition Single-ended voltage (w.r.t. VSS) D+/DSingle-pulse peak differential input voltage Amplitude ratio between adjacent symbols, 1100mV VRX-DIFFp-p 1300mV Amplitude ratio between adjacent symbols, VRX-DIFFp-p 1100mV Maximum inherent deterministic timing error Single-pulse width zero-voltage crossing Single-pulse width minimumlevel crossing Differential input rise/fall time Symbol VRX-DIFFp-p VRX-IDLE-SE VRX-IDLE-SE-DC VRX-IDLE-DIFFp-p VRX-SE VRX-DIFF-PULSE VRX-DIFF-ADJ RATIO- VRX-DIFF-ADJ RATIO min. -300 max. 1300 Unit Comments VRX-DIFFp-p -VRX-D-| Measured note
0.55
Given 20%-80% voltage levels. Defined VRX-CM (avg) |VRX-D+ VRX-D-|/2 Measured note also note VRX-CM-AC |VRX-D+ VRX-D-|/2 |VRX-D+ VRX-D-|/2 Measured note Measured over 0.1GHz 2.4GHz. also note Measured over 0.1GHz 2.4GHz. also note RRX-Match-DC RRX-D-| (RRX-D+ RRX-D-) Lane-to-lane skew receiver that must tolerated. also note
Maximum inherent timing error TRX-TJ-MAX TRX-DJ-DD TRX-PW-ZC TRX-PW-ML TRX-RISE, TRX-FALL
Common mode input voltage VRX-CM
peak-to-peak common mode VRX-CM-ACp-p input voltage Ratio VRX-CM-ACp-p minimum VRX-DIFFp-p Differential return loss Common mode return loss termination resistance D+/D- resistance difference VRX-CM-EH-Ratio RLRX-DIFF RLRX-CM RRX-Match-DC
Lane-to-lane skew Minimum Drift Tolerance Minimum data tracking bandwidth Electrical idle entry detect time Electrical idle exit detect time Error Ratio
LRX-PCB-SKEW TRX-DRIFT FTRK TEI-ENTRY DETECT TEI-EXIT -DETECT
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Notes: details, refer JEDEC specification "FB-DIMM High Speed Differential Link 1.5V". Specified package pins into timing voltage compliant test setup. Note that signal levels will lower than pin. Single-ended voltages below that value that simultaneously detected interpreted Electrical Idle condition. Worst-case margins determined comparing levels with common mode levels during normal operation case with transmitter using small voltage swing. Multiple lanes need detect condition before device upon detection. Specified package pins into timing voltage compliance test setup. Receiver designers implement either single-ended differential detection. Receivers must meet specification that corresponds implemented detection circuit. This specification, considered with VTX-IDLE-SE-DC, implies maximum 15mV single-ended offset between pins during electrical idle condition. This turn allows ground offset between adjacent FB-DIMM agents 26mV when worst case termination resistance matching considered. single-pulse mask provides sufficient symbol energy reliable reception. Each symbol must comply with both single-pulse mask cumulative mask. relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference Each symbol must comply with peak amplitude ratio with regard both preceding subsequent symbols. This number does include effects reference clock jitter. This number includes setup hold sampling flop. Defined dual-dirac deterministic timing error. Allows 15mV offset between transmit receive devices. received differential signal must satisfy both this ratio well absolute maximum peak-topeak common mode specification. example, VRX-DIFFp-p 200mV, maximum peak-topeak common mode lesser (200mV 0.45 90mV) VRX-CM-ACp-p. components that contribute deterioration return loss structure which needs carefully designed. termination small signal resistance; tolerance across voltages from 100mV 400mV shall exceed with regard average values measured 100mV 400mV that pin. This number represents lane-to-lane skew between pins does include transmitter output skew from component driving signal receiver. This component end-to-end channel skew specification. Measured from reference clock edge center input eye. This specification must across specified voltage temperature ranges single component. Drift rate change significantly below tracking capability receiver. This bandwidth number assumes specified minimum data transition density. Maximum jitter 0.2MHz 0.05UI. specified time includes time required forward entry condition. differential lane.
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Serial Matrix FB-DIMM
Byte Function described Number serial bytes written device size coverage revision byte DRAM device type Voltage levels this assembly SDRAM addressing Module physical attributes Module Type Thickness Module organization Fine timebase (FTB) dividend divisor Medium timebase dividend Medium timebase divisor SDRAM minimum cycle time (tCK (min.)) SDRAM maximum cycle time (tCK (max.)) SDRAM /CAS latencies supported SDRAM minimum /CAS latencies time (tCAS) SDRAM write recovery times supported SDRAM write recovery time (tWR) SDRAM write latencies supported SDRAM additive latencies supported SDRAM minimum /RAS /CAS delay (tRCD) SDRAM minimum active active delay (tRRD) SDRAM minimum precharge time (tRP) SDRAM upper nibbles tRAS SDRAM minimum active precharge time (tRAS) SDRAM minimum auto-refresh active /auto-refresh time (tRC) SDRAM minimum refresh recovery time delay (tRFC), SDRAM minimum refresh recovery time delay (tRFC), SDRAM Internal write read command delay (tWTR) SDRAM Internal read precharge command delay (tRTP) SDRAM burst lengths supported SDRAM terminations supported SDRAM drivers supported SDRAM average refresh interval (tREFI) double refresh mode high temperature self-refresh rate support indication Tcasemax (max.)) delta DT4R4W delta SDRAM still 45ns 60ns 105ns 105ns 7.5ns 7.5ns Supported 7.8µs Double/HT refresh 95°C/ 0.75°C
Byte value Revision DDR2 SDRAM FB-DIMM 1.8V, 1.5V 14-row, 10-column 8.2mm FB-DIMM rank 8bits
value
3.00ns 3.75ns 15ns 15ns 15ns 7.5ns 15ns
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Byte Function described SDRAM SDRAM DT2Q SDRAM DT2P SDRAM DT3N SDRAM DT4R mode SDRAM DT5B SDRAM Reserved FB-DIMM values Reserved personality bytes Reserved junction temperature maximum (max.)) Category byte Reserved Planar/FDHS Byte value
value
personality bytes Module manufacturer's JEDEC code Module manufacturer's JEDEC code Module manufacturing location Module manufacturing date Module manufacturing date Year code (BCD) Date code (BCD) Elpida Memory Elpida Memory
Module module serial number Cyclical redundancy code Module part number Module revision code Module revision code SDRAM manufacturer's JEDEC code SDRAM manufacturer's JEDEC code Informal content revision (MSB) Informal content revision (LSB) EBE51FD8AGFD/N Initial (Space) Elpida Memory Elpida Memory
Manufacturer's specific data Open customer
Remark IDD: DRAM current, ICC: current Notes: Based DDR2 SDRAM component specification. Refer JESD51-3 "Low effective thermal conductivity Test board leaded surface mount packages" under JESD51-2 standard. parameter derived following: IDDx T-A, where IDDx definition based JEDEC DDR2 SDRAM component specification VDD=1.9V, datasheet (worst case) value, programmed value (value Byte 33).
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
Physical Outline
Unit:
8.20 max.
Front side
74.675
(DATUM -A-)
Full DIMM heat spreader
5.20 max.
3.00 max.
3.90
4.00 min.
1.25
R0.75
51.00
1.27 0.10
67.00
5.175
133.35
Back side
9.50
17.30
3.00
FULL
2.50
Detail
2.50 0.20
Detail
(DATUM -A-)
0.20 0.15
1.00
2.50
FULL
0.80 0.05
keep zone
3.80
0.40 min.
5.00
1.50 0.10
ECA-TS2-0170-01
Preliminary Data Sheet E0869E30 (Ver. 3.0)
30.35
EBE51FD8AGFD, EBE51FD8AGFN
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0869E30 (Ver. 3.0)
EBE51FD8AGFD, EBE51FD8AGFN
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0869E30 (Ver. 3.0)

EBE51FD8AGFD EBE51FD8AGFN Density: 512MB Organization words bits,

Top Searches for this datasheet

Other recent searches