iP2004 SYNCHRONOUS BUCK POWER BLOCK iP2004 fully optimized s
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Data Sheet PD60322
iP2004
SYNCHRONOUS BUCK POWER BLOCK
iP2004 fully optimized solution high current synchronous buck multiphase applications. Board space design time greatly reduced because most components required each phase typical discrete-based multiphase circuit integrated into single 7.7mm 7.7mm 2.2mm power block. only additional components required complete multiphase converter controller, output inductors, input output capacitors.
Package Description iP2004 iP2004TR Interface Connection Standard Quantity 2000 Orientation Figure
Features
Multiphase building block derating TPCB Optimized power loss Bias supply range 4.5V 6.0V Operation 1.5MHz Over temperature protection Bi-directional Current flow Under Voltage Lockout interface 7.7mm 7.7mm 2.2mm package
Applications
High frequency, Multi-phase Converters Duty-Ratio, High Current Microprocessor Power Supplies High Frequency Profile DC-DC Converters
Typical Application
Enable Sync Track1 Track2 Vref VOUT Comp1 Comp2 PGOOD1 PGOOD2
5V_sns Ph_En1 PWM1 OCSet1 ENABLE PGND PGND VSWS1 VSWS2
VOUT
Ph_En2 PWM2 OCSet1
iP2004
IR3623
ENABLE PGND PGND VSWS1 VSWS2 VSW2
iP2004
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Data Sheet PD60322
iP2004
Absolute Maximum Ratings
PGND -0.5V PGND -0.5V 6.5V PGND -0.5V 0.5V (Note ENABLE PGND -0.5V 0.5V (Note Storage Temperature Block Temperature (Note Rating. Class (500V) Class (200V) Rating. CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those listed "Recommended Operating Conditions" section this specification implied.
Recommended Operating Conditions
PARAMETER
Supply Voltage (VDD) Input Voltage (VIN) Output Voltage (VOUT) Output Current (IOUT) Switching Frequency (FSW) Time Duty Cycle Minimum Time Block Temperature
13.2 1500
Units
Conditions
5.0V,
Electrical Specifications
These specifications apply TBLK 5.0V, unless otherwise specified.
PARAMETER
Ploss
Units
Conditions
12V, 5.0V, VOUT 1.3V, IOUT 40A, 1MHz, LOUT 0.3uH, (Note
Power Block Losses
Quiescent Current 12V, ENABLE
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Data Sheet PD60322
iP2004
PARAMETER
Supply Current (Stand Supply Current (Operating) 5.0V, ENABLE 12V, VDD= ABLE 5.0V, 1MHz,
Units
Conditions
Power-On Reset (POR)
Rising Hysterisis Rising Falling
ENABLE INPUT
Logic Level Threshold (VIL) Logic Level High Threshold (VIH) Threshold Hysterisis Weak pull-down current Rising Propagation Delay (TPDH) Falling Propagation Delay (TPDL) Schmitt Trigger Input 6.0V
INPUT
Logic Level Threshold (VIL) Logic Level High Threshold (VIH) Threshold Hysterisis Weak pull-down current Rising Propagation Delay (TPDH) Falling Propagation Delay (TPDL) Schmitt Trigger Input 6.0V (Note
Notes:
Must exceed 6.5V. Guaranteed design, tested production. Measurement made with 10µF (TDK C3225X5R1C106KT equivalent) ceramic capacitors across PGND pins (see Figure TPDH TPDL associated with rise fall times. Does affect Power Loss (see Figure 10). Block Temperature defined temperature within package.
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Data Sheet PD60322
iP2004
Power Loss Curve
Power Loss(W)
5.0V 1.3V 1MHz 300nH
Maximum
Output Current(A)
Typical
Figure 1Power Loss versus Output Current
Curve
Case Temperature
Output Current
Safe Operating Area
5.0V 1.3V 1MHz 300nH
Temperature
Figure Safe Operating Area (SOA) versus CASE temperatures (See page details)
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Data Sheet PD60322
iP2004
Typical Performance Curves
1.40 5.0V 1.35 1.3V 1.30 1MHz 300nH 1.20 1.25 12.0V 5.0V IOUT 1MHz 300nH 1.15 1.30
Temp Adjustment
Power Loss (Normalized)
1.20
1.15
Power Loss (Normalized)
1.25
Temp Adjustment
1.10
1.10
1.05
1.05
1.00 1.00 0.95
0.95
-1.2
-1.2
0.90
-2.4
0.90
-2.4
Input Voltage
Output Voltage
Figure Normalized Power Loss Input Voltage
1.06
12.0V 1.3V 1MHz 300nH
Figure Normalized Power Loss Output Voltage
1.12
12.0V 5.0V
1.04
1.10
1.3V IOUT 1MHz
1.08
Temperature Adjustment
Power Loss (Normalized)
Power Loss (Normalized)
1.02
Temp Adjustment
1.06
1.00
1.04
0.98
-0.5
1.02
0.96
-1.0
1.00
0.94
-1.5
0.98
-0.5
0.92 4.50
4.75
5.00
5.25
5.50
5.75
-2.0 6.00
0.96 0.10
0.20
0.30
0.40
0.50
0.60
0.70
-0.9 0.80
Drive Voltage
Output Inductor (µH)
Figure Normalized Power Loss versus Drive Voltage
1.30 1.25 1.20 1.15
12.0V 5.0V 1.3V IOUT 300nH
Figure Normalized Power Loss Inductance
12.0V 5.0V 1.3V IOUT 300nH
Average Supply Current (mA)
Temp Adjustment
Power Loss (Normalized)
1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 1000 1125 1250 1375
-1.2 -2.4 -3.6
-4.7 -5.9 -7.1 1500
1000 1100 1200 1300 1400 1500
Switching Frequency (kHz)
Switching Frequency (kHz)
Figure Normalized Power Loss Switching Frequency
Figure supply current Frequency
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Data Sheet PD60322
iP2004
Average Average Average Average POUT VOUT Average IOUT Average PLOSS (PIN PDD) POUT
Average Current Average Voltage
Average Input Current
Average Input Voltage
VSWS1 VSWS2 ENABLE PGND PGND
Average Output Current
Averaging Circuit
iP2004
Average Output Voltage
tPDH
tPDL
Figure Power Loss Test Circuit
Figure Timing Diagram
Applying Safe Operating Area (SOA) Curve
graph incorporates power loss thermal resistance information that allows solve maximum current capability simplified graphical manner. incorporates ability solve thermal problems where heat drawn through printed circuit board case. Please refer International Rectifier Application Note AN1047 further details using this curve your thermal environment.
Procedure
Calculate (based estimated Power Loss) measure Case temperature device Board temperature near device (1mm from edge). Draw line from Case Temperature axis Temperature axis. Draw vertical line from axis intercept curve. Draw horizontal line from intersection vertical line with curve Y-axis (Output Current). point which horizontal line meets Y-axis continuous current.
Case Temperature
Output Current
Safe Operating Area
5.0V 1.3V 1MHz 300nH
Temperature
Figure Example, Continuous current TPCB TCASE
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Data Sheet PD60322
iP2004
Calculating Power Loss Different Operating Conditions
calculate Power Loss given operation conditions, following procedure should followed:
Power Loss Procedure
Determine maximum current each iP2004 obtain maximum power loss from Figure Normalized curves page obtain power loss values that match operating conditions Application maximum power loss under Application conditions then product power loss from Figure normalized values. calculate Safe Operating Area (SOA) given operating conditions, following procedure should followed:
Procedure
Determine maximum CASE temperature maximum operating current each iP2004 Normalized curves page obtain temperature adjustments that match operating conditions Application Then, temperature adjustments axis intercept Figure
Design Example
Operating Conditions: Output Current Switching Freq 750kHz Input Voltage Inductor 0.2µH Output Voltage 3.3V Drive Voltage (VDD) 5.5V
Calculating Maximum Power Loss: (Figure (Figure (Figure (Figure (Figure (Figure Maximum power loss 8.0W Normalized power loss input voltage 0.98 Normalized power loss output voltage 1.23 Normalized power loss drive voltage (VDD) 0.96 Normalized power loss output inductor 1.03 Normalized power loss switch frequency 0.91
Calculated Maximum Power Loss 8.0W 0.98 1.23 0.96 1.03 0.91 8.68W
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Data Sheet PD60322
iP2004
Calculating Temperature: (Figure (Figure (Figure (Figure (Figure temperature adjustment input voltage temperature adjustment output voltage temperature adjustment drive voltage (VDD) -0.8 temperature adjustment output inductor temperature adjustment switch frequency -1.9
axis intercept adjustment -0.5 Assuming TPCB TCASE following example shows current adjusted increase
Case Temperature
Output Current
Safe Operating Area
5.0V 1.3V 1MHz 300nH
Temperature
Draw line from Case Temperature axis Temperature axis. Draw vertical line from axis intercept curve. Draw horizontal line from intersection vertical line with curve Y-axis (Output Current). point which horizontal line meets Y-axis continuous current. Draw vertical line from axis adding subtracting adjustment temperature from original intercept point. Draw horizontal line from intersection vertical line with curve Y-axis (Output Current). point which horizontal line meets Y-axis continuous current. adjustment indicates part still allowed continuous current 30A.
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Data Sheet PD60322
iP2004
Internal Block Diagram
VSWS1 VSWS2
ENABLE PGND
MOSFET Driver with dead time control
PGND
Figure Internal Block Diagram
Number
Name
ENABLE
Connect. This electrical connection When logic level high, internal circuitry device enabled. When logic level low, Control Synchronous FETs turned off. level input MOSFET drivers. When HIGH, Control Sync off. When LOW, Sync Control off. Supply voltage internal circuitry. Voltage Switching Node connection output inductor. Power Ground Input voltage pin. Connect input capacitors close this pin. Floating pin. Externally connect VSWS2 only. Floating pin. Externally short VSWS1 only.
PGND VSWS1 VSWS2
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Data Sheet PD60322
iP2004
Package Pinout Diagram
VSWS1
VSWS2
ENABLE
PGND
PGND
Figure Side Transparent View
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Data Sheet PD60322
iP2004
Recommended Layout
Figure copper Solder-mask layer layout
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Data Sheet PD60322
iP2004
Figure Bottom Component Placement (Topside, Transparent view down)
Layout Guidelines
following guidelines recommended reduce parasitic values optimize overall performance. pads iP2004 footprint design need Solder-mask defined (see Figure 14). Also refer International Rectifier application notes AN1028 AN1029 further footprint design guidance. Place many vias around Power pads (VIN, VSW, PGND) both electrical optimal thermal performance. Vias between different power pads overlap opening solder mask edge without need plug hole. Vias with 13mil drill hole 25mil capture were used this example. minimum 10µF, X5R, ceramic capacitors iP2004 needed greater than operation. This will result lowest loss input capacitor ESR. Placement ceramic input capacitors critical optimize switching performance. cases where there heatsink case iP2004, place ceramic capacitors right underneath iP2004 footprint (see Bottom Component Layer). cases where there heatsink, bottom layer moved locations (respectively) component layer (see Component Layer). both cases, need placed right underneath iP2004 footprint. Dedicate least layer PGND only Duplicate Power Nodes multiple layers (refer AN1029).
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Data Sheet PD60322
iP2004
Mechanical Outline Drawing
0.15 [.006]
7.65 [0.301]
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M-1994. DIMENSIONS SHOWN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETER
7.65 [0.301]
CORNER
PRIMARY DATUM (SEATING PLANE) DEFINED SOLDER RESIST OPENING
DRAWING SCALE.
0.15 [.006]
VIEW
7.319 6.303 5.795 0.334 4.779 4.132 0.322 1.858
0.07 [.0027]
2.21 [.087]
CORNER
2.379
2.010 3.459
3.865 6.583
5.821 7.345
5.300
5.021
2.54
0.762
1.016
BOTTOM VIEW
SIDE VIEW
VSWS1 VSWS2
PGND PGND
ENABLE
BOTTOM VIEW ELECTRICAL
Figure Mechanical Outline Drawing
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Data Sheet PD60322
iP2004
Recommended Solder Paste Stencil Design
Figure Solder Paste Stencil Design
Tape Reel Information
Figure Tape Reel Information
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Data Sheet PD60322
iP2004
Part Marking
Figure Part Marking
Data specifications subject change without notice. WORLD HEADQUARTERS: Kansas St., Segundo, California 90245, Tel: (310) 252-7105 Fax: (310) 252-7903 Visit www.irf.com sales contact information
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