Express-to-PCI Reversible Bridge Revision 3545 North Street,
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PI7C9X110
Express-to-PCI Reversible Bridge
Revision
3545 North Street, Jose, 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com
PI7C9X110
PCIe-to-PCI Reversible Bridge
LIFE SUPPORT POLICY
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other trademarks their respective companies.
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
REVISION HISTORY
DATE
09/08/2006 11/21/2006 03/06/2007 05/02/2007
REVISION
DESCRIPTION
First release 9X110 datasheet without revision suffix Removed references PI7C9X110A Revised ratings Specifications" section 16.2 Revised table section Address bit[5] corrected equal Address bit[4] corrected equal GPIO[3] Revised logos font types added Industrial Temp Compliancy
11/02/2007
PREFACE
datasheet PI7C9X110 will enhanced periodically when updated information available. technical information this datasheet subject change without notice. This document describes functionalities PI7C9X110 (PCI Express Bridge) provides technical information designers design their hardware using PI7C9X110.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
TABLE CONTENTS
INTRODUCTION
EXPRESS FEATURES PCI-X FEATURES. GENERAL FEATURES
DEFINITIONS
SIGNAL TYPES EXPRESS SIGNALS. SIGNALS. MODE SELECT STRAPPING SIGNALS JTAG BOUNDARY SCAN SIGNALS MISCELLANEOUS SIGNALS. POWER GROUND PINS. ASSIGNMENTS
MODE SELECTION STRAPPING.
FUNCTIONAL MODE SELECTION PCI-X SELECTION STRAPPING.
FORWARD REVERSE BRIDGING TRANSPARENT NON-TRANSPARENT BRIDGING.
TRANSPARENT MODE NON-TRANSPARENT MODE.
EXPRESS FUNCTIONAL OVERVIEW.
STRUCTURE VIRTUAL ISOCHRONOUS OPERATION.
CONFIGURATION REGISTERS.
CONFIGURATION REGISTER MAP. EXPRESS EXTENDED CAPABILITY REGISTER CONTROL STATUS REGISTER MAP. CONFIGURATION REGISTERS TRANSPARENT BRIDGE MODE 7.4.1 VENDOR OFFSET 7.4.2 DEVICE OFFSET 00h. 7.4.3 COMMAND REGISTER OFFSET 7.4.4 PRIMARY STATUS REGISTER OFFSET 04h. 7.4.5 REVISION REGISTER OFFSET 7.4.6 CLASS CODE REGISTER OFFSET 7.4.7 CACHE LINE SIZE REGISTER OFFSET 0Ch. 7.4.8 PRIMARY LATENCY TIMER REGISTER OFFSET 7.4.9 PRIMARY HEADER TYPE REGISTER OFFSET 7.4.10 RESERVED REGISTERS OFFSET 17h. 7.4.11 PRIMARY NUMBER REGISTER OFFSET 7.4.12 SECONDARY NUMBER REGISTER OFFSET 7.4.13 SUBORDINATE NUMBER REGISTER OFFSET 7.4.14 SECONDARY LATENCY TIME REGISTER OFFSET 18h.
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PCIe-to-PCI Reversible Bridge
7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24 7.4.25 7.4.26 7.4.27 7.4.28 7.4.29 7.4.30 7.4.31 7.4.32 7.4.33 7.4.34 7.4.35 7.4.36 7.4.37 7.4.38 7.4.39 7.4.40 7.4.41 7.4.42 7.4.43 7.4.44 7.4.45 7.4.46 7.4.47 7.4.48 7.4.49 7.4.50 7.4.51 7.4.52 7.4.53 7.4.54 7.4.55 7.4.56 7.4.57 7.4.58 7.4.59 7.4.60 7.4.61 7.4.62 7.4.63 7.4.64 7.4.65 7.4.66
BASE REGISTER OFFSET 1Ch. LIMIT REGISTER OFFSET 1Ch. SECONDARY STATUS REGISTER OFFSET MEMORY BASE REGISTER OFFSET MEMORY LIMIT REGISTER OFFSET PREFETCHABLE MEMORY BASE REGISTER OFFSET 24h. PREFETCHABLE MEMORY LIMIT REGISTER OFFSET 24h. PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET 28h. PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET 2Ch. BASE UPPER 16-BIT REGISTER OFFSET 30h. LIMIT UPPER 16-BIT REGISTER OFFSET 30h. CAPABILITY POINTER OFFSET EXPANSION BASE ADDRESS REGISTER OFFSET INTERRUPT LINE REGISTER OFFSET 3Ch. INTERRUPT REGISTER OFFSET BRIDGE CONTROL REGISTER OFFSET DATA BUFFERING CONTROL REGISTER OFFSET CHIP CONTROL REGISTER OFFSET 40h. RESERVED REGISTER OFFSET 44h. ARBITER ENABLE REGISTER OFFSET 48h. ARBITER MODE REGISTER OFFSET 48h. ARBITER PRIORITY REGISTER OFFSET RESERVED REGISTERS OFFSET EXPRESS TRANSMITTER/RECEIVER REGISTER OFFSET 68h. UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET RESERVED REGISTER OFFSET EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET 70h. RESERVED REGISTER OFFSET 74h. GPIO DATA CONTROL REGISTER OFFSET 78h. RESERVED REGISTER OFFSET PCI-X CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET PCI-X SECONDARY STATUS REGISTER OFFSET 80h. PCI-X BRIDGE STATUS REGISTER OFFSET 84h. UPSTREAM SPLIT TRANSACTION REGISTER OFFSET DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET POWER MANAGEMENT REGISTER OFFSET 90h. NEXT CAPABILITY POINTER REGISTER OFFSET POWER MANAGEMENT CAPABILITY REGISTER OFFSET POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET PCI-TO-PCI SUPPORT EXTENSION REGISTER OFFSET RESERVED REGISTERS OFFSET CAPABILITY REGISTER OFFSET A0h. NEXT POINTER REGISTER OFFSET A0h. SLOT NUMBER REGISTER OFFSET CHASSIS NUMBER REGISTER OFFSET SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET A4h. CAPABILITY REGISTER OFFSET A8h. NEXT POINTER REGISTER OFFSET A8h. RESERVED REGISTER OFFSET SUBSYSTEM VENDOR REGISTER OFFSET ACh. SUBSYSTEM REGISTER OFFSET
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PCIe-to-PCI Reversible Bridge
7.4.67 7.4.68 7.4.69 7.4.70 7.4.71 7.4.72 7.4.73 7.4.74 7.4.75 7.4.76 7.4.77 7.4.78 7.4.79 7.4.80 7.4.81 7.4.82 7.4.83 7.4.84 7.4.85 7.4.86 7.4.87 7.4.88 7.4.89 7.4.90 7.4.91 7.4.92 7.4.93 7.4.94 7.4.95 7.4.96 7.4.97 7.4.98 7.4.99 7.4.100 7.4.101 7.4.102 7.4.103 7.4.104 7.4.105 7.4.106 7.4.107 7.4.108 7.4.109 7.4.110 7.4.111 7.4.112 7.4.113 7.4.114 7.4.115 7.4.116 7.4.117 7.4.118
EXPRESS CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET EXPRESS CAPABILITY REGISTER OFFSET DEVICE CAPABILITY REGISTER OFFSET B4h. DEVICE CONTROL REGISTER OFFSET B8h. DEVICE STATUS REGISTER OFFSET B8h. LINK CAPABILITY REGISTER OFFSET LINK CONTROL REGISTER OFFSET C0h. LINK STATUS REGISTER OFFSET C0h. SLOT CAPABILITY REGISTER OFFSET SLOT CONTROL REGISTER OFFSET SLOT STATUS REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET CCh. XPIP CONFIGURATION REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET SWAP SWITCH DEBOUNCE COUNTER OFFSET D4h. CAPABILITY REGISTER OFFSET NEXT POINTER REGISTER OFFSET REGISTER OFFSET DATA REGISTER OFFSET DCh. RESERVED REGISTERS OFFSET MESSAGE SIGNALED INTERRUPTS REGISTER F0h. NEXT CAPABILITIES POINTER REGISTER F0h. MESSAGE CONTROL REGISTER OFFSET MESSAGE ADDRESS REGISTER OFFSET MESSAGE UPPER ADDRESS REGISTER OFFSET F8h. MESSAGE DATA REGISTER OFFSET FCh. ADVANCE ERROR REPORTING CAPABILITY REGISTER OFFSET 100h ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER OFFSET 100h NEXT CAPABILITY OFFSET REGISTER OFFSET 100h UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch. CORRECTABLE ERROR STATUS REGISTER OFFSET 110h. CORRECTABLE ERROR MASK REGISTER OFFSET 114h ADVANCED ERROR CAPABILITIES CONTROL REGISTER OFFSET 118h. HEADER REGISTER OFFSET 11Ch HEADER REGISTER OFFSET 120h. HEADER REGISTER OFFSET 124h. HEADER REGISTER OFFSET 128h. SECONDARY UNCORRECTABLE ERROR STATUS REGISTER OFFSET 12Ch SECONDARY UNCORRECTABLE ERROR MASK REGISTER OFFSET 130h SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 134h SECONDARY ERROR CAPABILITY CONTROL REGISTER OFFSET 138h. SECONDARY HEADER REGISTER OFFSET 13Ch 148h. RESERVED REGISTER OFFSET 14Ch CAPABILITY REGISTER OFFSET 150h CAPABILITY VERSION REGISTER OFFSET 150h NEXT CAPABILITY OFFSET REGISTER OFFSET 150h PORT CAPABILITY REGISTER OFFSET 154h PORT CAPABILITY REGISTER OFFSET 158h PORT CONTROL REGISTER OFFSET 15Ch.
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PCIe-to-PCI Reversible Bridge
7.4.119 7.4.120 7.4.121 7.4.122 7.4.123 7.4.124 7.4.125 7.4.126 7.4.127
PORT STATUS REGISTER OFFSET 15Ch. RESOURCE CAPABILITY REGISTER OFFSET 160h RESOURCE CONTROL REGISTER OFFSET 164h RESOURCE STATUS REGISTER OFFSET 168h RESERVED REGISTERS OFFSET 16Ch 300h EXTRA GPI/GPO DATA CONTROL REGISTER OFFSET 304h. RESERVED REGISTERS OFFSET 308h 30Ch REPLAY ACKNOWLEDGE LATENCY TIMERS OFFSET 310h RESERVED REGISTERS OFFSET 314h FFCh VENDOR OFFSET DEVICE OFFSET 00h. COMMAND REGISTER OFFSET PRIMARY STATUS REGISTER OFFSET 04h. REVISION REGISTER OFFSET CLASS CODE REGISTER OFFSET CACHE LINE SIZE REGISTER OFFSET 0Ch. PRIMARY LATENCY TIMER REGISTER OFFSET PRIMARY HEADER TYPE REGISTER OFFSET PRIMARY MEMORY BASE ADDRESS REGISTER OFFSET 10h. PRIMARY BASE ADDRESS REGISTER OFFSET DOWNSTREAM MEMORY BASE ADDRESS REGISTER OFFSET DONWSTREAM MEMORY BASE ADDRESS REGISTER OFFSET DOWNSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 20h. DOWNSTREAM MEMORY UPPER BASE ADDRESS REGISTER OFFSET RESERVED REGISTER OFFSET 28h. SUBSYTEM SUBSYSTEM VENDOR REGISTER OFFSET 2Ch. RESERVED REGISTER OFFSET 30h. CAPABILITY POINTER OFFSET EXPANSION BASE ADDRESS REGISTER OFFSET PRIMARY INTERRUPT LINE REGISTER OFFSET PRIMARY INTERRUPT REGISTER OFFSET 3Ch. PRIMARY MINIMUM GRANT REGISTER OFFSET PRIMARY MAXIMUM LATENCY TIME REGISTER OFFSET 3Ch. DATA BUFFERING CONTROL REGISTER OFFSET CHIP CONTROL REGISTER OFFSET 40h. SECONDARY COMMAND REGISTER OFFSET SECONDARY STATUS REGISTER OFFSET 44h. ARBITER ENABLE REGISTER OFFSET 48h. ARBITER MODE REGISTER OFFSET 48h. ARBITER PRIORITY REGISTER OFFSET SECONDARY CACHE LINE SIZE REGISTER OFFSET SECONDARY LATENCY TIME REGISTER OFFSET 4Ch. SECONDARY HEADER TYPE REGISTER OFFSET SECONDARY MEMORY BASE ADDRESS REGISTER OFFSET 50h. SECONDARY BASE ADDRESS REGISTER OFFSET UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 58h. UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 5Ch. UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET UPSTREAM MEMORY UPPER BASE ADDRESS REGISTER OFFSET 64h. EXPRESS TRANSMITTER/RECEIVER REGISTER OFFSET 68h. MEMORY ADDRESS FORWARDING CONTROL REGISTER OFFSET
CONFIGURATION REGISTERS NON-TRANSPARENT BRIDGE MODE.
7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 7.5.15 7.5.16 7.5.17 7.5.18 7.5.19 7.5.20 7.5.21 7.5.22 7.5.23 7.5.24 7.5.25 7.5.26 7.5.27 7.5.28 7.5.29 7.5.30 7.5.31 7.5.32 7.5.33 7.5.34 7.5.35 7.5.36 7.5.37 7.5.38 7.5.39 7.5.40 7.5.41 7.5.42
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7.5.43 7.5.44 7.5.45 7.5.46 7.5.47 7.5.48 7.5.49 7.5.50 7.5.51 7.5.52 7.5.53 7.5.54 7.5.55 7.5.56 7.5.57 7.5.58 7.5.59 7.5.60 7.5.61 7.5.62 7.5.63 7.5.64 7.5.65 7.5.66 7.5.67 7.5.68 7.5.69 7.5.70 7.5.71 7.5.72 7.5.73 7.5.74 7.5.75 7.5.76 7.5.77 7.5.78 7.5.79 7.5.80 7.5.81 7.5.82 7.5.83 7.5.84 7.5.85 7.5.86 7.5.87 7.5.88 7.5.89 7.5.90 7.5.91 7.5.92 7.5.93 7.5.94
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET SUBSYSTEM VENDOR REGISTER OFFSET SUBSYSTEM REGISTER OFFSET 6Ch. EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET 70h. RESERVED REGISTER OFFSET 74h. BRIDGE CONTROL STATUS REGISTER OFFSET GPIO DATA CONTROL REGISTER OFFSET 78h. SECONDARY INTERRUPT LINE REGISTER OFFSET SECONDARY INTERRUPT REGISTER OFFSET 7Ch. SECONDARY MINIMUM GRANT REGISTER OFFSET SECONDARY MAXIMUM LATENCY TIMER REGISTER OFFSET 7Ch. PCI-X CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET PCI-X SECONDARY STATUS REGISTER OFFSET 80h. PCI-X BRIDGE STATUS REGISTER OFFSET 84h. UPSTREAM SPLIT TRANSACTION REGISTER OFFSET DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET POWER MANAGEMENT REGISTER OFFSET 90h. NEXT CAPABILITY POINTER REGISTER OFFSET POWER MANAGEMENT CAPABILITY REGISTER OFFSET POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET PCI-TO-PCI SUPPORT EXTENSION REGISTER OFFSET DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET DOWNSTREAM MEMORY SETUP REGISTER OFFSET CAPABILITY REGISTER OFFSET A0h. NEXT POINTER REGISTER OFFSET A0h. SLOT NUMBER REGISTER OFFSET CHASSIS NUMBER REGISTER OFFSET SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET A4h. DONWSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET DOWSTREAM MEMORY SETUP REGISTER OFFSET EXPRESS CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET EXPRESS CAPABILITY REGISTER OFFSET DEVICE CAPABILITY REGISTER OFFSET B4h. DEVICE CONTROL REGISTER OFFSET B8h. DEVICE STATUS REGISTER OFFSET B8h. LINK CAPABILITY REGISTER OFFSET LINK CONTROL REGISTER OFFSET C0h. LINK STATUS REGISTER OFFSET C0h. SLOT CAPABILITY REGISTER OFFSET SLOT CONTROL REGISTER OFFSET SLOT STATUS REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET CCh. XPIP CONFIGURATION REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET CAPABILITY REGISTER OFFSET NEXT POINTER REGISTER OFFSET REGISTER OFFSET DATA REGISTER OFFSET DCh. UPSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET UPSTREAM MEMORY SETUP REGISTER OFFSET
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PCIe-to-PCI Reversible Bridge
7.5.95 7.5.96 7.5.97 7.5.98 7.5.99 7.5.100 7.5.101 7.5.102 7.5.103 7.5.104 7.5.105 7.5.106 7.5.107 7.5.108 7.5.109 7.5.110 7.5.111 7.5.112 7.5.113 7.5.114 7.5.115 7.5.116 7.5.117 7.5.118 7.5.119 7.5.120 7.5.121 7.5.122 7.5.123 7.5.124 7.5.125 7.5.126 7.5.127 7.5.128 7.5.129 7.5.130 7.5.131 7.5.132 7.5.133 7.5.134 7.5.135 7.5.136
UPSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET UPSTREAM MEMORY SETUP REGISTER OFFSET ECh. MESSAGE SIGNALED INTERRUPTS REGISTER F0h. NEXT CAPABILITIES POINTER REGISTER F0h. MESSAGE CONTROL REGISTER OFFSET MESSAGE ADDRESS REGISTER OFFSET MESSAGE UPPER ADDRESS REGISTER OFFSET F8h. MESSAGE DATA REGISTER OFFSET FCh. ADVANCE ERROR REPORTING CAPABILITY REGISTER OFFSET 100h ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER OFFSET 100h NEXT CAPABILITY OFFSET REGISTER OFFSET 100h UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch. CORRECTABLE ERROR STATUS REGISTER OFFSET 110h. CORRECTABLE ERROR MASK REGISTER OFFSET 114h ADVANCED ERROR CAPABILITIES CONTROL REGISTER OFFSET 118h. HEADER REGISTER OFFSET 11Ch HEADER REGISTER OFFSET 120h. HEADER REGISTER OFFSET 124h. HEADER REGISTER OFFSET 128h. SECONDARY UNCORRECTABLE ERROR STATUS REGISTER OFFSET 12Ch SECONDARY UNCORRECTABLE ERROR MASK REGISTER OFFSET 130h SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 134h SECONDARY ERROR CAPABILITY CONTROL REGISTER OFFSET 138h. SECONDARY HEADER REGISTER OFFSET 13Ch 148h. RESERVED REGISTER OFFSET 14Ch CAPABILITY REGISTER OFFSET 150h CAPABILITY VERSION REGISTER OFFSET 150h NEXT CAPABILITY OFFSET REGISTER OFFSET 150h PORT CAPABILITY REGISTER OFFSET 154h PORT CAPABILITY REGISTER OFFSET 158h PORT CONTROL REGISTER OFFSET 15Ch. PORT STATUS REGISTER OFFSET 15Ch. RESOURCE CAPABILITY REGISTER OFFSET 160h RESOURCE CONTROL REGISTER OFFSET 164h RESOURCE STATUS REGISTER OFFSET 168h RESERVED REGISTERS OFFSET 16Ch 300h EXTRA GPI/GPO DATA CONTROL REGISTER OFFSET 304h. RESERVED REGISTERS OFFSET 308h 30Ch REPLAY ACKNOWLEDGE LATENCY TIMERS OFFSET 310h RESERVED REGISTERS OFFSET 314h FFCh
7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8
CONTROL STATUS REGISTERS NON-TRANSPARENT BRIDGE MODE
RESERVED REGISTERS OFFSET 000h 004h. DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET 008h DOWNSTREAM MEMORY SETUP REGISTER OFFSET 00Ch. DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET 010h DOWNSTREAM MEMORY SETUP REGISTER OFFSET 014h DOWNSTREAM MEMORY UPPER 32-BIT SETUP REGISTER OFFSET 018h RESERVED REGISTERS OFFSET 01Ch 030h UPSTREAM MEMORY SETUP REGISTER OFFSET 34h.
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PCIe-to-PCI Reversible Bridge
7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.6.14 7.6.15 7.6.16 7.6.17 7.6.18 7.6.19 7.6.20 7.6.21 7.6.22 7.6.23 7.6.24 7.6.25 7.6.26 7.6.27 7.6.28 7.6.29 7.6.30 7.6.31 7.6.32 7.6.33 7.6.34 7.6.35 7.6.36 7.6.37
UPSTREAM MEMORY UPPER 32-BIT SETUP REGISTER OFFSET 038h. RESERVED REGISTERS OFFSET 03Ch 04Ch LOOKUP TABLE OFFSET OFFSET 050h LOOKUP TABLE DATA OFFSET 054h. UPSTREAM PAGE BOUNDARY REQUEST REGISTER OFFSET 058h UPSTREAM PAGE BOUNDARY REQUEST REGISTER OFFSET 05Ch. UPSTREAM PAGE BOUNDARY MASK REGISTER OFFSET 060h UPSTREAM PAGE BOUNDARY MASK REGISTER OFFSET 064h RESERVED REGISTER OFFSET 068C PRIMARY CLEAR REGISTER OFFSET 070h. SECONDARY CLEAR REGISTER OFFSET 070h. PRIMARY REGISTER OFFSET 074h SECONDARY REGISTER OFFSET 074h PRIMARY CLEAR MASK REGISTER OFFSET 078h SECONDARY CLEAR MASK REGISTER OFFSET 078h PRIMARY MASK REGISTER OFFSET 07Ch SECONDARY MASK REGISTER OFFSET 07Ch RESERVED REGISTERS OFFSET 080h 09Ch SCRATCHPAD REGISTER OFFSET 0A0h. SCRATCHPAD REGISTER OFFSET 0A4h. SCRATCHPAD REGISTER OFFSET 0A8h. SCRATCHPAD REGISTER OFFSET 0ACh SCRATCHPAD REGISTER OFFSET 0B0h. SCRATCHPAD REGISTER OFFSET 0B4h. SCRATCHPAD REGISTER OFFSET 0B8h. SCRATCHPAD REGISTER OFFSET 0BCh RESERVED REGISTERS OFFSET 0C0h 0FCh. LOOKUP TABLE REGISTERS OFFSET 100h 1FCh RESERVED REGISTERS OFFSET 200h FFCh
GPIO PINS ADDRESS. CLOCK SCHEME INTERRUPTS. EEPROM (I2C) INTERFACE SYSTEM MANAGEMENT
11.1 11.2 EEPROM (I2C) INTERFACE SYSTEM MANAGEMENT BUS.
14.1 14.2 14.3 14.4 14.5
PLUG OPERATION RESET SCHEME. IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
INSTRUCTION REGISTER BYPASS REGISTER. DEVICE REGISTER. BOUNDARY SCAN REGISTER. JTAG BOUNDARY SCAN REGISTER ORDER.
POWER MANAGEMENT ELECTRICAL TIMING SPECIFICATIONS.
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PCIe-to-PCI Reversible Bridge
16.1 16.2 16.3
ABSOLUTE MAXIMUM RATINGS SPECIFICATIONS. SPECIFICATIONS.
PACKAGE INFORMATION. ORDERING INFORMATION.
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PCIe-to-PCI Reversible Bridge
TABLE FIGURES
FIGURE PI7C9X110 TOPOLOGY FIGURE PCI-X SELECTION FIGURE FORWARD NON-TRANSPARENT BRIDGE MODE FIGURE REVERSE TRANSPARENT BRIDGE MODE FIGURE 16-1 SIGNAL TIMING CONDITIONS FIGURE 17-1 VIEW DRAWING FIGURE 17-2 BOTTOM VIEW DRAWING. FIGURE 17-3 PACKAGE OUTLINE DRAWING.
LIST TABLES
TABLE ASSIGNMENTS TABLE MODE SELECTION TABLE STRAPPING TABLE NON-TRANSPARENT REGISTERS TABLE FORMAT TABLE CONFIGURATION REGISTER (00H FFH) TABLE EXPRESS EXTENDED CAPABILITY REGISTER (100H FFFH) TABLE CONTROL STATUS REGISTER (CSR) (000H FFFH) TABLE DEVICE STRAPPING TABLE 10-1 PCIE INTERRUPT MESSAGE INTERRUPT MAPPING REVERSE BRIDGE MODE. TABLE 10-2 INTERRUPT PCIE INTERRUPT MESSAGE MAPPING FORWARD BRIDGE MODE TABLE 14-1 INSTRUCTION REGISTER CODES TABLE 14-2 JTAG DEVICE REGISTER TABLE 14-3 JTAG BOUNDARY SCAR REGISTER DEFINITION TABLE 16-1 ABSOLUTE MAXIMUM RATINGS TABLE 16-2 ELECTRICAL CHARACTERISTICS TABLE 16-3 TIMING PARAMETERS
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PCIe-to-PCI Reversible Bridge
INTRODUCTION
PI7C9X110 PCIe-to-PCI/PCI-X bridge. PI7C9X110 compliant with Express Base Specification, Revision 1.0a, Express Card Electromechanical Specification, Revision 1.0a, Local Specification, Revision Express PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X110 supports transparent non-transparent mode operations. Also, PI7C9X110B supports forward reverse bridging. forward bridge mode, PI7C9X110 Express upstream port 32-bit PCI/PCI-X downstream port. 32-bit downstream port 66MHz capable (see figure 1-1). reverse bridge mode, PI7C9X110 32-bit upstream port Express downstream port. PI7C9X110 configuration registers backward compatible with existing bridge software firmware. modification bridge software firmware needed original operation. Figure PI7C9X110 Topology
Express Port
PI7C9X110
32bit 66MHz
Device
Device
Device
Device
Device
Device
Device
Device
EXPRESS FEATURES
Compliant with Express Base Specification, Revision 1.0a Compliant with Express Card Electromechanical Specification, Revision 1.0a Compliant with Express PCI/PCI-X Bridge Specification, Revision Physical Layer interface link with 2.5Gb/s data rate) Lane polarity toggle Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) ASPM support Beacon support (16-bit), LCRC (32-bit) ECRC advanced error reporting PRBS (Pseudo Random Sequencing) generator/checker chip testing
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PCIe-to-PCI Reversible Bridge
Maximum payload size bytes
PCI-X FEATURES
Compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision Compliant with Interface Specification, Revision Compliant with Hot-Plug Specification, Revision Compliant with Mobile Design Guide, Version Compliant with PCI-X Protocol Addendum Local Specification, Revision 2.0a support 3.3V signaling with tolerance Provides level arbitration support eight masters 16-bit address decode Subsystem Vendor Subsystem Device support interrupt Function support
GENERAL FEATURES
Compliant with Advanced Configuration Power Interface Specification (ACPI), Revision 2.0b Compliant with System Management (SM) Bus, Version Forward bridging (PCI Express primary bus, secondary bus) Reverse bridging (PCI primary bus, Express secondary bus) Transparent mode support Non-transparent mode Support GPIO support bi-directional pins) Power Management (including ACPI, CLKRUN_L, PCI_PM) Masquerade Mode (pre-loadable vendor, device, revision IDs) EEPROM (I2C) Interface Interface Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption about Watt typical condition Extended commercial temperature range 85C)
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PCIe-to-PCI Reversible Bridge
DEFINITIONS
SIGNAL TYPES
TYPE SIGNAL DESCRIPTIONS Bi-directional Input Input with pull-up Input with pull-down Bi-directional with open drain output Open drain output Output Power Ground
EXPRESS SIGNALS
NAME REFCLKP REFCLKN RREF PERST_L ASSIGNMENT TYPE DESCRIPTION Reference Clock Inputs: Connect external 100MHz differential clock. Express data inputs: Differential data receiver input signals Express data outputs: Differential data transmitter output signals Resistor Reference: used connect external resistor (2.4K provide reference current driver equalization circuit. Express Fundamental Reset: PI7C9X110B uses this reset initialize internal state machines.
SIGNALS
NAME [31:0] ASSIGNMENT C12, D14, D12, D11, E13, F14, F13, F11, G12, G11, H13, H12, J14, J13, J11, A10, C14, TYPE DESCRIPTION Address Data: Multiplexed address data bus. Address phase aligned with first clock FRAME_L assertion. Data phase aligned with IRDY_L TRDY_L assertion. Data transferred rising edges FBCLKIN when both IRDY_L TRDY_L asserted. During idle (both FRAME_L IRDY_L deasserted), PI7C9X110B drives valid logic level when arbiter parking PI7C9X110B bus.
[3:0]
FRAME_L
Command Byte Enables (Active LOW): Multiplexed command address phase byte enable data phase. During address phase, initiator drives commands [3:0] signals start transaction. command write transaction, initiator will drive byte enables during data phase. Otherwise, target will drive byte enables during data phase. During idle, PI7C9X110B drives [3:0] signals valid logic level when arbiter parking PI7C9X110B bus. Parity Bit: Parity even parity (i.e. even number 1's), which generates based values [31:0], [3:0]. PI7C9X110B initiator with write transaction, PI7C9X110B will tri-state PAR. PI7C9X110B target write transaction, PI7C9X110B will drive clock after address data phase. PI7C9X110B target read transaction, PI7C9X110B will drive clock after address phase tri-state during data phases. tri-stated cycle after lines tri-stated. During idle, PI7C9X110B drives valid logic level when arbiter parking PI7C9X110B bus. FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. de-assertion FRAME_L indicates final data phase signaled initiator burst transfers. Before being tri-stated, driven de-asserted state cycle.
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PCIe-to-PCI Reversible Bridge
NAME IRDY_L
ASSIGNMENT
TYPE
TRDY_L
DEVSEL_L
STOP_L
LOCK_L IDSEL PERR_L
SERR_L
REQ_L [7:0]
GNT_L [7:0]
CLKOUT [8:0] RESET_L INTA_L INTB_L INTC_L INTD_L FBCLKIN CLKIN
N12, P12, N11, L10, M10, P10,
DESCRIPTION IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven deasserted state cycle. TRDY (Active LOW): Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven deasserted state cycle. Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C9X110 waits assertion this signal within cycles FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven deasserted state cycle. LOCK (Active LOW): Asserted initiator multiple transactions complete. PI7C9X110B does support upstream LOCK transaction. Initialization Device Select: Used chip select line Type configuration access bridge's configuration space. Parity Error (Active LOW): Asserted when data parity error detected data received interface. Before being tri-stated, driven de-asserted state cycle. System Error (Active LOW): driven device indicate system error condition. SERR control enabled, PI7C9X110B will drive this Address parity error Posted write data parity error target Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout Errors reported from Express port (advanced error reporting) transparent mode. This signal open drain buffer that requires external pull-up resistor proper operation. Request (Active LOW): REQ_L's asserted master devices request transactions bus. master devices de-assert REQ_Ls least clock cycles before asserting them again. external arbiter selected (CFN_L=1), REQ_L will grant input PI7C9X110. Also, REQ_L [5:2] will become [3:0]. Grant (Active LOW): PI7C9X110 asserts GNT_Ls release control master devices. During idle GNT_Ls de-asserted arbiter parking PI7C9X110, PI7C9X110 will drive CBE, valid logic levels. external arbiter selected (CFN_L=1), GNT_L will request from PI7C9X110 external arbiter. Also, GNT_L [5:2] will become [3:0]. Clock Outputs: clock outputs derived from CLKIN provide clocking signals external Devices. RESET_L (Active LOW): When RESET_L active, signals should asynchronously tri-stated. Interrupt: Signals asserted request interrupt. After asserted, cleared device driver. INTA_L, INTB_L, INTC_L, INTD_L signals inputs asynchronous clock forward mode. reverse mode, INTA_L, INTB_L, INTC_L, INTD_L open drain buffers sending interrupts host interrupt controller. Feedback Clock Input: connects CLKOUT [8:0] Output Signals provides internal clocking PI7C9X110 interface. Clock Input: Clock Input Signal connects external clock source. Clock Outputs CLKOUT [8:0] pins derived from CLKIN Input.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
MODE SELECT STRAPPING SIGNALS
NAME ASSIGNMENT TYPE DESCRIPTION Mode Select strapping pin. When strapped normal operations strapped high testing functions. table mode selection strapping control details. Mode Select Mode Selection select EEPROM Bus. TM1=0 EEPROM (I2C) support TM1=1 support. also strapping pin. table mode selection strapping control. Mode Select Mode Selection select transparent non-transparent mode. TM0=0 transparent bridge function mode TM0=1 non-transparent bridge function mode. also strapping pin. table mode selection strapping control. Mask Input CLKOUT: MSK_IN used PI7C9X110 enable disable clock outputs. MSK_IN also strapping pin. When strapped high, hot-plug enabled. table strapping control. Forward Reverse Bridging Pin: REVRSB controls Forward (REVRSB=0) Reverse (REVRSB=1) Bridge Mode PI7C9X110. This also strapping pin. table mode selection. Central Function Control (Active Low): enable internal arbiter, CFN_L should tied low. When it's tied high, external arbiter required arbitrate bus. external arbiter mode, REQ_L re-configured secondary grant input, GNT_L reconfigured secondary request output. Also, REQ_L [5:2] GNT_L [5:2] become [3:0] [3:0] respectively external arbiter selected. CFN_L weak internal pull-down resistor. table mode selection.
MSK_IN
REVRSB
CFN_L
JTAG BOUNDARY SCAN SIGNALS
NAME ASSIGNMENT TYPE DESCRIPTION Test Clock: test clock synchronize state information data side PI7C9X110 during boundary scan operation. Test Mode Select: controls state Test Access Port (TAP) controller. Test Data Output: test data output connects JTAG scan chain. Test Data Input: test data input connects beginning JTAG scan chain. allows test instructions data serially shifted into side PI7C9X110. Test Reset (Active LOW): TRST_L test reset initialize Test Access Port (TAP) controller.
TRST_L
MISCELLANEOUS SIGNALS
NAME GPIO [3:0] ASSIGNMENT TYPE DESCRIPTION General Purpose Data Pins: general-purpose signals programmable either input-only bi-directional signals writing GPIO output enable control register configuration space. Chapter more information. SMBUS EEPROM Clock Pin: When EEPROM (I2C) interface selected (TM1=0), this output clock connected EEPROM clock input. When SMBUS interface selected (TM1=1), this input clock SMBUS. SMBUS EEPROM Data Pin: Data Interface EERPOM SMBUS. When EEPROM (I2C) interface selected (TM1=0), this bi-directional signal. When SMBUS interface selected (TM1=1), this open drain signal. Power Management Event Pin: Power Management Event Signal asserted request change device link power state. Clock (Active LOW): Clock signal, mobile environment, asserted de-asserted indicate status Clock.
SMBCLK
SMBDATA PME_L CLKRUN_L
B/IOD
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PI7C9X110
PCIe-to-PCI Reversible Bridge
NAME PCIXCAP
ASSIGNMENT
TYPE
PCIXUP
DESCRIPTION PCI-X Capability Pin: PI7C9X110 forced mode PCIXCAP tied ground with capacitor (0.1uF) parallel. PCIXCAP connected ground through capacitor (0.1uF), PI7C9X110 will 133MHz PCI-X mode. PCIXCAP connected ground through resistor (10K Ohm) with capacitor (0.1uF) parallel, PI7C9X110 will 66MHz PCI-X mode. PCIXCAP Pull-up driver: PI7C9X110 drives this PCI-X mode detection.
POWER GROUND PINS
NAME VDDA VDDP VDDAUX VDDA_PLL VDDC VDDCAUX VD33 ASSIGNMENT L11, L12, B12, C10, N10, M11, K12, J12, H14, F12, E11, D13, P11, K13, H11, G13, E12, E14, C13, C11, TYPE DESCRIPTION Analog Voltage Supply Express Interface: Connect 1.8V Power Supply. Digital Voltage Supply Express Interface: Connect 1.8V Power Supply. Auxiliary Voltage Supply Express Interface: Connect 1.8V Power Supply. Termination Supply Voltage Express Interface: Connect 1.8V Power Supply. Analog Voltage Supply Interface: Connect 1.8V Power Supply. Core Supply Voltage: Connect 1.8V Power Supply. Auxiliary Core Supply Voltage: Connect 1.8V Power Supply. Supply Voltage Interface: Connect 3.3V Power Supply Buffers. Auxiliary Supply Voltage interface: Connect 3.3V Power Supply. Ground: Connect Ground.
VAUX
VDDA
Analog Voltage Supply Express Interface: Connect 1.8V Power Supply.
ASSIGNMENTS
Table Assignments
NAME SMBDAT SMBCLK PME_L [30] [27] VD33 [23] [20] VD33 TRDY_L STOP_L LOCK_L PERR_L PCIXCAP VAUX [31] [29] NAME PCIXUP CLKRUN_L [28] [25] [21] [18] IRDY_L [12] [13] VD33 [14] REFCLKN REFCLKP NAME RREF VD33 VDDA VDDA_PLL VD33 VDDP NAME REQ_L[2]/GPI[0] GNT_L GNT_L[3]/GPO[1] INTB_L CFN_L GPIO CLKOUT VD33 REVRSB REQ_L[3] GPI[1] REQ_L[4] GPI[2] REQ_L[5] GPI[3] GNT_L GNT_L[4]/GPO[2] GNT_L RESET_L
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PI7C9X110
PCIe-to-PCI Reversible Bridge
NAME [24] [22] [17] FRAME_L DEVSEL_L VDDC SERR_L FBCLKIN VD33 [26] VD33 [19] [16] VDDC [15]
NAME VDDC VD33 [11] VDDAUX VDDP VDDP VD33 [10] VDDA
NAME TRST_L VD33 VDDC VDDCAUX PERST_L VD33 GNT_L[2]/GPO[0] GPIO GPIO CLKOUT CLKOUT VDDC VDDC REQ_L REQ_L
NAME VDDC CLKOUT VD33 CLKOUT CLKOUT INTD_L IDSEL REQ_L REQ_L INTA_L GNT_L[5]/GPO[3] GNT_L CLKIN GPIO CLKOUT CLKOUT CLKKOUT INTC_L MSK_IN
MODE SELECTION STRAPPING
FUNCTIONAL MODE SELECTION
strapped low, PI7C9X110 uses TM1, TM0, CFN_L, REVRSB pins select different modes operations. These four input signals required stable during normal operation. sixteen combinations normal operation selected setting logic values four mode select pins. example, logic values four (TM1, TM0, CFN_L, REVRSB) pins, normal operation will have EEPROM (I2C) support transparent mode with internal arbiter forward bridge mode. designated operation with respect values TM1, TM0, CFN_L, REVRSB pins defined Table 3-1: Table Mode Selection
Strapped CFN_L REVRSB Functional Mode EEPROM (I2C) support support Transparent mode Non-Transparent mode Internal arbiter External arbiter Forward bridge mode Reverse bridge mode
PCI-X SELECTION
secondary interface capable operating either conventional mode PCI-X mode. PI7C9X110 controls mode frequency secondary utilizing pull-up circuit connected PCIXCAP. There pull-up resistors circuit recommended PCI-X addendum. first resistor weak pull-up (56K ohms) whose value selected voltage PCIXCAP below threshold when PCI-X 66MHz device attached secondary bus. second resistor strong pull-up, externally wired between PCIXCAP PCIXUP. value resistor ohm) selected voltage PCIXCAP above high threshold when devices secondary PCI-X 66MHz capable. detect mode frequency secondary bus, PCIXUP initially disabled PI7C9X110 samples value PCIXCAP.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
PI7C9X110 sees logic PCIXCAP, more devices secondary have either pulled signal ground (PCI-X 66MHz capable) tied ground (only capable conventional mode). differentiate between conditions, PI7C9X110 then enables PCIXUP strong pull-up into circuit node. PCIXCAP remains logic LOW, must tied ground more devices, initialized conventional mode. PCIXUP pulled more devices capable only PCI-X 66MHz operation initialized PCI-X 66MHz mode. PI7C9X110 sees logic HIGH PCIXCAP, then devices secondary capable PCI-X 100MHz 133MHz operation. Since PI7C9X110 does have distinguish between 100MHz 133MHz clock frequencies, logic based 133MHz. secondary initialized PCI-X 133MHz mode. However, 100MHz clock still used devices PCI-X 100MHz capable clock input (pin CLKIN) 100MHz frequency. There M66EN secondary interface PI7C9X110 because internal bypassed conventional mode. CLKIN used directly, eliminating need distinguish between conventional 33MHz 66MHz. Figure PCI-X Selection
PI7C9X110
3.3v Ohms PCIXCAP Ohms Strong Pull-up 0.01uF PCIXUP Ohms 0.01uF 0.01uF Weak Pull-up
Enable During Capability Determination
3.3v
Card
PCI-X 66MHz Card
PCI-X 100MHz 133MHz Card
STRAPPING
strapped high, PI7C9X110 uses TM1, TM0, MSK_IN strapping pins. strapping functions listed Table show states operations during Express PERST_L de-assertion transition forward bridge mode RESET_L de-assertion transition reverse bridge mode. Table Strapping
Strapped Strapped Strapped MSK_IN Strapped Test Functions
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Strapped
Strapped
Strapped
MSK_IN Strapped
Test Functions test Shorten initialization test with hotplug enabled Functional loopback test Bridge test (PRBS, IDDQ, etc.) Reserved Shorten initialization test with hotplug disabled Reserved Reserved
FORWARD REVERSE BRIDGING
PI7C9X110 supports forward reverse transparent non-transparent combination modes operation. example, when PI7C9X110 operating forward (REVRSB=0) non-transparent bridge mode (TM0=1) shown Figure 4-1, Express interface connected root complex interface connected devices. Another example, PI7C9X110 configured reverse (REVRSB=1) transparent (TM0=0) bridge shown Figure 4-2. non-transparent bridge feature PI7C9X110 allows Processor isolated from Host Processor memory which avoiding memory address conflict when both host processors needed sideby-side. based systems peripherals ubiquitous interconnect technology market today. will tremendous effort convert existing based products used Express systems. PI7C9X110 provides solution bridge existing based products latest Express technology. Figure Forward Non-transparent Bridge Mode
Host Processor
System Memory
Root Complex
link
PI7C9X110
Local Memory
Local Processor
Fibre Channel
Fast Ethernet
SCSI
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PI7C9X110
PCIe-to-PCI Reversible Bridge
reverse (REVRSB=1) transparent (TM0=0) mode shown Figure 3-2, PI7C9X110 becomes PCI-to-PCI Express bridge that interface connected host chipset between Express link. enables legacy Host Systems provide Express capability. PI7C9X110 provides solution convert existing based designs adapt quickly into Express base platforms. Existing based applications will have undergo complete re-architecture order interface Express technology. Figure Reverse Transparent Bridge Mode
Host Processor
System Memory
Chipset
32bit 66MHz 32bit 66MHz
PI7C9X110
Fibre Channel
Fast Ethernet
SCSI
link
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PI7C9X110
PCIe-to-PCI Reversible Bridge
TRANSPARENT NON-TRANSPARENT BRIDGING
TRANSPARENT MODE
transparent bridge mode, base class code PI7C9X110 (bridge device). sub-class code (PCI-to-PCI bridge). Programming interface 00h. Hence, PI7C9X110 subtractive decoding bridge. PI7C9X110 type-1 configuration header (transparent bridge mode). These configuration registers same traditional transparent PCI-to-PCI Bridge. fact, backward compatible software that supporting traditional transparent PCI-to-PCI bridges. Configuration registers accessed from several different ways. Express access, Express configuration transaction forward bridge mode. access, configuration cycle mainly reverse bridge mode. However, PI7C9X110 allows configuration access forward mode secondary configuration access. access, protocol used with EEPROM selected (TM1=0). access, protocol used with selected (TM1=1).
NON-TRANSPARENT MODE
non-transparent bridge mode, base class code PI7C9X110 (bridge device). sub-class code (other bridge). Programming interface 00h. Hence, PI7C9X110 subtractive decoding bridge. PI7C9X110 type-0 configuration header (non-transparent mode). configuration registers similar traditional device. However, there configuration registers primary interface another configuration registers secondary interface. addition, CSRs (Control Status Registers) implemented support memory transfers between primary secondary buses. CSRs accessed through memory transaction access within lowest memory range Space (bit [64:12] zeros). non-transparent configuration registers accessed through several different ways (PCI Express, PCI, I2C, bus). Express access, type-0 configuration transactions need used. access, protocol needs used through interface. access, protocol needs used through interface. hardware pins shared interface. TM1=0, will interface respectively. TM1=1, will SMBCLK SMBDATA interface respectively. non-transparent bridge mode, PI7C9X110 supports four three memory BARs (Base Address Registers) BARs (Base Address Registers) depending selection primary bus. Also, PI7C9X110 supports four three memory BARs (Base Address Registers) BARs (Base Address Registers) depending selection secondary bus. Offset defined primary downstream memory BAR. Offset defined primary downstream BAR. Offset defined downstream memory (selectable setup register). Offset defined downstream memory BAR. Offset defined downstream memory lower memory upper respectively support 64-bit decoding. direct offset translation address from primary secondary will done substituting original Base Address primary with downstream Translation Base Address Register values keeping lower address bits same form address forward transaction secondary bus. downstream memory uses direct address translation. There lookup table downstream memory address translation.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Offset defined secondary upstream memory BAR. Offset defined secondary upstream BAR. Offset defined upstream memory (selectable setup register offset E4h). Offset defined upstream memory BAR. Offset defined upstream memory lower memory upper respectively support 64-bit decoding. direct offset translation address from secondary primary will done substituting original Base Address secondary with upstream Translation Base Address Register values keeping lower address bits same form address forward transaction primary bus. upstream memory uses lookup table address translation method which using original base address index select address upstream memory lookup table based page window size defined. Table Non-transparent Registers
Non-transparent Registers Primary Memory Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Downstream Memory Upper 32-bit Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Upper 32-bit Setup Secondary Memory Upstream Memory Translated Base Upstream Memory Setup Secondary Upstream Memory Upstream Memory Translated Base Upstream Memory Setup Upstream Memory Upstream Memory Lookup Table Offset Upstream Memory Lookup Table Data Upstream Memory Lookup Table 32-bit entries) Upstream Memory Upstream Memory Upper 32-bit Upstream Memory Setup Upstream Memory Upper 32-bit Setup Typical access Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Lower Memory access offset 008h Lower Memory access offset 00Ch Configuration access offset Configuration access offset Lower Memory access offset 010h Lower Memory access offset 014h Lower Memory access offset 018h Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Lower Memory access offset 050h Lower Memory access offset 054h Lower Memory access offset 100h 1FFh Configuration access offset Configuration access offset Lower Memory access offset Lower Memory access offset
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PI7C9X110
PCIe-to-PCI Reversible Bridge
EXPRESS FUNCTIONAL OVERVIEW
STRUCTURE
Express (Transaction Layer Packet) Structure comprised format, type, traffic class, attributes, digest, poison, length data payload. There four formats defined PI7C9X110 based states shown Table 6-1. Table Format
Format double word, without data double word, without data double word, with data double word, with data
Data payload PI7C9X110 range from (1DW) (64DW) bytes. PI7C9X110 supports three routing mechanisms. They comprised Address, Implicit routings. Address routing being used Memory requests. based (bus, device, function numbers) routing being used configuration requests. Implicit routing being used message routing. There message groups (baseline advanced switching). baseline message group contains INTx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. other advanced switching support message group. advanced switching support message contains data packet signal packet messages. Advanced switching beyond scope PI7C9X110 implementation. [2:0] values "type" field will determine destination message routed. baseline messages must default traffic class zero (TC0).
VIRTUAL ISOCHRONOUS OPERATION
This section provides summary Virtual Isochronous Operation supported PI7C9X110. Virtual Isochronous support disabled default. Virtual Isochronous feature turned with setting [26] offset one. Control bits designated selecting which traffic class (TC1-7) used upstream (PCI Express-toPCI). PI7C9X110 accepts only packets configuration, message packets downstream (PCI Express-to-PCI). configuration, message packets have traffic class other than TC0, PI7C9X110 will treat them malformed packets. PI7C9X110 maps downstream memory packets from Express transactions regardless virtual Isochronous operation enabled not.
CONFIGURATION REGISTERS
PI7C9X110 supports Type-0 (non-transparent bridge mode) Type-1 (transparent bridge mode) configuration space headers Capability (PCI power management) (PCI Express capability structure). With REVRSB device-port type (bit [7:4]) capability register will (PCI Express-to-PCI/PICX bridge). When REVRSB device-port type (bit [7:4]) capability register will (PCI/PCI-Xto-PCI Express bridge). PI7C9X110 supports Express capabilities register structure with capability version (bit [3:0] offset 02h).
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PI7C9X110
PCIe-to-PCI Reversible Bridge
When TM0=0, PI7C9X110 will transparent bridge mode configuration registers transparent bridge should used. When TM0=1, PI7C9X110 will non-transparent bridge mode configuration registers nontransparent bridge should used.
CONFIGURATION REGISTER
PI7C9X110 supports capability pointer with PCI-X (ID=07h), power management (ID=01h), bridge subsystem vendor (ID=0Dh), Express (ID=10h), vital product data (ID=03h), message signaled interrupt (ID=05h). Slot identification (ID=04h) default turned through configuration programming. Table Configuration Register (00h FFh)
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode Secondary Configuration Access Non-Transparent Mode Only Transparent Mode (type1) Non-Transparent Mode (Type0) EEPROM (I2C) Access Access
Vendor Device Command Register Primary Status Register Class Code Revision Cacheline Size Register Primary Latency Timer Header Type Register Reserved Reserved Reserved Primary Number Register Secondary Number Register Subordinate Number Register Secondary Latency Timer Base Register Limit Register Secondary Status Register Memory Base Register Memory Limit Register Prefetchable Memory Base Register
Vendor Device Primary Command Register Primary Status Register Class Code Revision Primary Cacheline Size Register Primary Latency Timer Header Type Register Reserved Primary Memory Primary Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Upper 32-bit
Yes1 Yes1 Yes1
Yes5 Yes5 Yes5
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PCIe-to-PCI Reversible Bridge
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode
Secondary Configuration Access Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
Access
Prefetchable Memory Limit Register Prefetchable Memory Base Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Base Upper 16-bit Register Limit Upper 16-bit Register Capability Pointer Reserved Reserved Interrupt Line Interrupt Bridge Control Bridge Control Data Buffering Control Chip Control Reserved Reserved Arbiter Mode, Enable, Priority Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Express Control Reserved Reserved Reserved Reserved
Downstream Memory Upper 32-bit
Subsystem Vendor
Yes2
Yes5
Subsystem
Yes2
Yes5
Reserved Reserved Capability Pointer Reserved Reserved Primary Interrupt Line Primary Interrupt Primary Min_Gnt Primary Max_Lat Data Buffering Control Chip Control Secondary Command Register Secondary Status Register Arbiter Mode, Enable, Priority Secondary Cacheline Size Register Secondary Status Register Header Type Reserved Secondary Memory Secondary Upstream Memory Upstream Memory Upstream Memory Upstream Memory Upper 32-bit Express Control Memory Address Forwarding Control Reserved Subsystem Vendor Subsystem
Yes3 Yes3 Yes3 Yes2 Yes2
Yes3 Yes3 Yes3 Yes5 Yes5
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PCIe-to-PCI Reversible Bridge
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode
Secondary Configuration Access Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
Access
EEPROM (I2C) Control Status Register Reserved GPIO Data Control bits) Reserved bits) Reserved bits) Reserved Reserved Reserved Reserved PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control Status Reserved Reserved Slot Capability Clock CLKRUN Control SSID SSVID Capability Subsystem Subsystem Vendor Express Capability Device Capability Device Control Status Link Capability Link Control Status Slot Capability Slot Control Status XPIP Configuration Register XPIP Configuration Register XPIP Configuration Register Reserved Capability Register Data Register
EEPROM (I2C) Control status Register Reserved GPIO Data Control bits) Bridge Control Status bits) Reserved bits) Secondary Interrupt Line Secondary Interrupt Secondary Min_Gnt Secondary Max_Lat PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control Status Downstream Memory Translated Base Downstream Memory Setup Slot Capability Clock CLKRUN Control Downstream Memory Translated Base Downstream Memory Setup Express Capability Device Capability Device Control Status Link Capability Link Control Status Slot Capability Slot Control Status XPIP Configuration Register XPIP Configuration Register XPIP Configuration Register Reserved Capability Register Data Register
Yes3 Yes3
Yes3 Yes3 Yes3
Yes4
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PCIe-to-PCI Reversible Bridge
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode
Secondary Configuration Access Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
Access
Reserved Reserved Reserved
Reserved Capability Register Message Address Message Upper Address Message Date
Note When masquerade enabled, pre-loadable. Note When both masquerade non-transparent mode enabled, pre-loadable. Note When non-transparent mode enabled, pre-loadable. Note data read/write through during operation. Note Read access only.
Upstream Memory Translated Base Upstream Memory setup Upstream Memory Translated Base Upstream Memory Setup Capability Register Message Address Message Upper Address Message Date
Yes3 Yes3
Yes3 Yes3
EXPRESS EXTENDED CAPABILITY REGISTER
PI7C9X110 also supports Express Extended Capabilities with from 257-byte 4096-byte space. offset range from 100h FFFh. offset 100h defined Advance Error Reporting (ID=0001h). offset 150h defined Virtual Channel (ID=0002h). Table Express Extended Capability Register (100h FFFh)
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode 103h 100h Secondary Configuration Access Non-Transparent Mode Only Transparent Mode (type1) Non-Transparent Mode (Type0) EEPROM (I2C) Access Access
103h 100h
107h 104h 10Bh 108h 10Fh 10Ch 113h 110h 117h 114h 11Bh 118h 12Bh 11Ch 12Fh 12Ch
107h 104h 10Bh 108h 10Fh 10Ch 113h 110h 117h 114h 11Bh 118h 12Bh 11Ch 12Fh 12Ch
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask Control Header Register Secondary Uncorrectable Error Status
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask Control Header Register Secondary Uncorrectable Error Status
Yes5
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PCIe-to-PCI Reversible Bridge
Primary Configuration Access both Transparent Non-Transparent mode, Secondary Configuration Access Transparent Mode 133h 130h
Secondary Configuration Access Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
Access
133h 130h
137h 134h 13Bh 138h 14Bh 13Ch 14Fh 14Ch 153h 150h 157h 154h 15Bh 158h 15Fh 15Ch 163h 160h 167h 164h 16Bh 168h 2FFh 170h 303h 300h 307h 304h 30Fh 308h 310h
137h 134h 13Bh 138h 14Bh 13Ch 14Fh 14Ch 153h 150h 157h 154h 15Bh 158h 15Fh 15Ch 163h 160h 167h 164h 16Bh 168h 2FFh 170h 503h 500h 507h 504h 50Fh 508h 510h
4FFh 314h 503h 500h 504h 50Fh 505h 510h FFFh 514h Note Read access only.
4FFh 314h 303h 300h 304h 30Fh 305h 310h FFFh 514h
Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary Control Secondary Header Register Reserved Capability Port Capability Port Capability Port Status Control Resource Capability Resource Control Resource Status Reserved Reserved Extended GPI/GPO Data Control Reserved Replay Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary Control Secondary Header Register Reserved Capability Port Capability Port Capability Port Status Control Resource Capability Resource Control Resource Status Reserved Reserved Extended GPI/GPO Data Control Reserved Replay Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
CONTROL STATUS REGISTER
Table Control Status Register (CSR) (000h FFFh)
Express Memory Offset 007h 000h 00Bh 008h 00Fh 00Ch 013h 010h 017h 014h 01Bh 018h 02Fh 01Ch Offset Register Name Reset Value EEPROM (I2C) Access Access
207h 200h 20Bh 208h 20Fh 20Ch 213h 210h 217h 214h 21Bh 218h 22Fh 21Ch
Reserved Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Upper 32-bit Setup Reserved
XXXX_XXXXh 0000_0000h XXXX_XXXXh 0000_0000h 0000_0000h
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PCIe-to-PCI Reversible Bridge
Express Memory Offset 033h 030h 037h 034h 03Bh 038h 04Fh 03Ch 050h 053h 051h 057h 054h 05Bh 058h 05Fh 05Ch 063h 060h 067h 064h 06Fh 068h 071h 070h 073h 072h 075h 074h 077h 076h 079h 078h 07Bh 07Ah 07Dh 07Ch 07Fh 07Eh 09Fh 080h 0A3h 0A0h 0A7h 0A4h 0ABh 0A8h 0AFh 0ACh 0B3h 0B0h 0B7h 0B4h 0BBh 0B8h 0BFh 0BCh 0FFh 0C0h 1FFh 100h FFFh 200h
Offset
Register Name
Reset Value
233h 230h 237h 234h 21Bh 218h 24Fh 23Ch 250h 253h 251h 257h 254h 25Bh 258h 25Fh 25Ch 263h 260h 267h 264h 26Fh 268h 271h 270h 273h 272h 275h 274h 277h 276h 279h 278h 27Bh 27Ah 27Dh 27Ch 27Fh 27Eh 29Fh 280h 2A3h 2A0h 2A7h 2A4h 2ABh 2A8h 2AFh 2ACh 2B3h 2B0h 2B7h 2B4h 2BBh 2B8h 2BCh 2BFh 2FFh 2C0h 3FFh 300h 11FFh 400h
Reserved Upstream Memory Setup Upstream Memory Upper 32-bit Setup Reserved Lookup Table Offset Register Reserved Lookup Table Data Register Upstream Page Boundary Upstream Page Boundary Upstream Page Boundary Mask Upstream Page Boundary Mask Reserved Primary Clear Register Secondary Clear Register Primary Register Secondary Register Primary Clear Mask Register Secondary Clear Mask Register Primary Mask Register Secondary Mask Register Reserved Scratch Scratch Scratch Scratch Scratch Scratch Scratch Scratch Reserved Upstream Memory Lookup Table Reserved
0000_0000h 0000_0000h XXXX_XXXXh 0000_0000h 0000_0000h FFFF_FFFFh FFFF_FFFFh 0000h 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh
EEPROM (I2C) Access
Access
CONFIGURATION REGISTERS TRANSPARENT BRIDGE MODE
following section describes configuration space when device transparent mode. descriptions different register type listed follow:
Register Type Descriptions Read Only Read Only Sticky Read/Write
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PI7C9X110
PCIe-to-PCI Reversible Bridge
RWCS
Read/Write clear Read/Write Sticky Read/Write clear Sticky
7.4.1
VENDOR OFFSET
15:0 FUNCTION Vendor TYPE DESCRIPTION Identifies Pericom vendor this device. Returns 12D8h when read.
7.4.2
DEVICE OFFSET
31:16 FUNCTION Device TYPE DESCRIPTION Identifies this device PI7C9X110. Returns E110 when read.
7.4.3
COMMAND REGISTER OFFSET
FUNCTION Space Enable TYPE DESCRIPTION Ignore transactions primary interface Enable response memory transactions primary interface Reset Ignore memory read transactions primary interface Enable memory read transactions primary interface Reset initiate memory transactions primary interface disable response memory transactions secondary interface Enable bridge operate master primary interfaces memory transactions forwarded from secondary interface. primary reverse bridge PCI-X mode, bridge allowed initiate split completion transaction regardless status bit. Reset PI7C9X110 does respond target Special Cycle transactions, this defined Read-Only must return when read Reset PI7C9X110 does originate Memory Write Invalidate transaction. Implements this Read-Only returns when read (unless forwarding transaction another master). This will ignored PCI-X mode. Reset This applies reverse bridge only. Ignore palette access primary Enable positive decoding response palette writes primary interface with address bits [9:0] equal 3C6h, 3C8h, 3C9h (inclusive alias; [15:0] decoded value) Reset ignore parity error that detected take normal action This set, enables setting Master Data Parity Error Status Register when poisoned received parity error detected takes normal action Reset Wait cycle control supported Reset Disable Enable PI7C9X110 forward bridge mode report non-fatal fatal error message Root Complex. Also, reverse bridge mode assert
Memory Space Enable
Master Enable
Special Cycle Enable
Memory Write Invalidate Enable
Palette Snoop Enable
Parity Error Response Enable
Wait Cycle Control
SERR_L Enable
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION
TYPE
DESCRIPTION SERR_L primary interface Reset Fast back-to-back enable supported Reset This applies reverse bridge only. INTA_L, INTB_L, INTC_L, INTD_L asserted interface Prevent INTA_L, INTB_L, INTC_L, INTD_L from being asserted interface Reset Reset 00000
Fast Back-to-Back Enable
Interrupt Disable
15:11
Reserved
7.4.4
PRIMARY STATUS REGISTER OFFSET
18:16 FUNCTION Reserved Reserved (transparent mode) Capability List Capable TYPE DESCRIPTION Reset Reset PI7C9X110 supports capability list (offset pointer data structure) Reset This applies reverse bridge only. 66MHz capable Reset when forward bridge when reverse bridge. Reset This applies reverse bridge only. Enable fast back-to-back transactions Reset when forward bridge when reverse bridge mode. Parity Error Enable either conditions occurs primary: FORWARD BRIDGE Receives completion marked poisoned Poisons write request REVERSE BRIDGE Detected parity error when receiving data Split Response read Observes P_PERR_L asserted when sending data receiving Split Response write Receives Split Completion Message indicating data parity error occurred non-posted write Reset These bits apply reverse bridge only. fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
66MHz Capable
Reserved Fast Back-to-Back Capable
Master Data Parity Error Detected
26:25
DEVSEL_L Timing (medium decode)
Signaled Target Abort
Reset when forward bridge when reverse bridge. FORWARD BRIDGE This when PI7C9X110 completes request using completer abort status primary REVERSE BRIDGE This indicate target abort primary Reset FORWARD BRIDGE
Received Target Abort
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION
TYPE
DESCRIPTION This when PI7C9X110 receives completion with completer abort completion status primary REVERSE BRIDGE This when PI7C9X110 detects target abort primary Reset FORWARD BRIDGE This when PI7C9X110 receives completion with unsupported request completion status primary REVERSE BRIDGE This when PI7C9X110 detects master abort primary FORWARD BRIDGE This when PI7C9X110 sends ERR_FATAL ERR_NON_FATAL message primary REVERSE BRIDGE This when PI7C9X110 asserts SERR_L primary Reset FORWARD BRIDGE This when poisoned detected primary REVERSE BRIDGE This when address data parity error detected primary Reset
Received Master Abort
Signaled System Error
Detected Parity Error
7.4.5
REVISION REGISTER OFFSET
FUNCTION Revision TYPE DESCRIPTION Reset 00000002h
7.4.6
CLASS CODE REGISTER OFFSET
15:8 FUNCTION Programming Interface TYPE DESCRIPTION Subtractive decoding PCI-PCI bridge supported Reset 00000000 Sub-Class Code 00000100: PCI-to-PCI bridge Reset 00000100 Base class code 00000110: Bridge Device (transparent mode) Reset 00000110 (transparent mode)
23:16
Sub-Class Code
31:24
Base Class Code
7.4.7
CACHE LINE SIZE REGISTER OFFSET
FUNCTION Reserved TYPE DESCRIPTION [1:0] supported Reset Cache line size double words Reset Cache line size double words Reset Cache line size double words
Cache Line Size
Cache Line Size
Cache Line Size
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Cache Line Size
TYPE
DESCRIPTION Reset Cache line size double words Reset [7:6] supported Reset
Reserved
7.4.8
PRIMARY LATENCY TIMER REGISTER OFFSET
15:8 FUNCTION Primary Latency Timer TYPE DESCRIPTION bits primary latency timer PCI/PCI-X FORWARD BRIDGE with reset REVERSE BRIDGE with reset mode PCI-X mode
7.4.9
PRIMARY HEADER TYPE REGISTER OFFSET
22:16 FUNCTION PCI-to-PCI bridge configuration (transparent mode) Other bridge configuration (non-transparent mode) Single Function Device TYPE DESCRIPTION PCI-to-PCI bridge configuration 3Fh) Reset 0000001 (transparent mode)
Type-0 header format configuration (10-3Fh) Reset 0000000 (non-transparent mode) Indicates single function device Reset Reset
31:24
Reserved
7.4.10 RESERVED REGISTERS OFFSET 7.4.11 PRIMARY NUMBER REGISTER OFFSET
FUNCTION Primary Number TYPE DESCRIPTION Reset
7.4.12 SECONDARY NUMBER REGISTER OFFSET
15:8 FUNCTION Secondary Number TYPE DESCRIPTION Reset
7.4.13 SUBORDINATE NUMBER REGISTER OFFSET
23:16 FUNCTION Subordinate Number TYPE DESCRIPTION Reset
7.4.14 SECONDARY LATENCY TIME REGISTER OFFSET
31:24 FUNCTION Secondary Latency Timer TYPE DESCRIPTION Secondary latency timer PCI-X mode FORWARD BRIDGE with reset mode PCI-X mode REVERSE BRIDGE with reset
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.15 BASE REGISTER OFFSET
FUNCTION 32-bit Addressing Support Reserved Base TYPE DESCRIPTION Indicates PI7C9X110 supports 32-bit addressing Reset Reset Indicates base (0000_0000h) Reset 0000
7.4.16 LIMIT REGISTER OFFSET
FUNCTION 32-bit Addressing Support Reserved Base TYPE DESCRIPTION Indicates PI7C9X110 supports 32-bit addressing Reset Reset Indicates Limit (0000_0FFFh) Reset 0000
11:10 15:12
7.4.17 SECONDARY STATUS REGISTER OFFSET
20:16 FUNCTION Reserved 66MHz Capable TYPE DESCRIPTION Reset 00000 Indicates PI7C9X110 66MHz capable Reset Reset FORWARD BRIDGE: reset when secondary mode (supports fast back-to-back transactions) reset when secondary PCI-X mode (does support fast back-to-back transactions) REVERSE BRIDGE: reset (does support fast back-to-back transactions) This parity error enable either conditions occur primary: FORWARD BRIDGE Detected parity error when receiving data split response read Observes S_PERR_L asserted when sending data receiving split response write Receives split completion message indicating data parity error occurred non-posted write REVERSE BRIDGE Receives completion marked poisoned Poisons write request Reset These bits apply forward bridge only. medium DEVSEL_L decoding Reset when forward mode when reverse mode. FORWARD BRIDGE when PI7C9X110 signals target abort REVERSE BRIDGE when PI7C9X110 completes request using completer abort completion status Reset
Reserved Fast Back-to-Back Capable
Master Data Parity Error Detected
26:25
DEVSEL_L Timing (medium decoding)
Signaled Target Abort
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Received Target Abort
TYPE
DESCRIPTION FORWARD BRIDGE when PI7C9X110 detects target abort secondary interface REVERSE BRIDGE when PI7C9X110 receives completion with completer abort completion status secondary interface Reset FORWARD BRIDGE when PI7C9X110 detects master abort secondary interface REVERSE BRIDGE when PI7C9X110 receives completion with unsupported request completion status primary interface Reset FORWARD BRIDGE when PI7C9X110 detects SERR_L assertion secondary interface REVERSE BRIDGE when PI7C9X110 receives ERR_FATAL ERR_NON_FATAL message secondary interface Reset FORWARD BRIDGE when PI7C9X110 detects address data parity error REVERSE BRIDGE when PI7C9X110 detects poisoned secondary interface Reset
Received Master Abort
Received System Error
Detected Parity Error
7.4.18 MEMORY BASE REGISTER OFFSET
15:4 FUNCTION Reserved Memory Base TYPE DESCRIPTION Reset 0000 Memory Base (80000000h) Reset 800h
7.4.19 MEMORY LIMIT REGISTER OFFSET
19:16 31:20 FUNCTION Reserved Memory Limit TYPE DESCRIPTION Reset 0000 Memory Limit (000FFFFFh) Reset 000h
7.4.20 PREFETCHABLE MEMORY BASE REGISTER OFFSET
FUNCTION 64-bit Addressing Support TYPE DESCRIPTION 0001: Indicates PI7C9X110 supports 64-bit addressing Reset 0001 Prefetchable Memory Base (00000000_80000000h) Reset 800h
15:4
Prefetchable Memory Base
7.4.21 PREFETCHABLE MEMORY LIMIT REGISTER OFFSET
FUNCTION TYPE DESCRIPTION
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PI7C9X110
PCIe-to-PCI Reversible Bridge
19:16
FUNCTION 64-bit Addressing Support
TYPE
DESCRIPTION 0001: Indicates PI7C9X110 supports 64-bit addressing Reset 0001 Prefetchable Memory Limit (00000000_000FFFFFh) Reset 000h
31:20
Prefetchable Memory Limit
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.22 PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET
31:0 FUNCTION Prefetchable Base Upper 32bit TYPE DESCRIPTION [63:32] prefetchable base Reset 00000000h
7.4.23 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET
31:0 FUNCTION Prefetchable Limit Upper 32-bit TYPE DESCRIPTION [63:32] prefetchable limit Reset 00000000h
7.4.24 BASE UPPER 16-BIT REGISTER OFFSET
15:0 FUNCTION Base Upper 16-bit TYPE DESCRIPTION [31:16] Base Reset 0000h
7.4.25 LIMIT UPPER 16-BIT REGISTER OFFSET
31:16 FUNCTION Limit Upper 16-bit TYPE DESCRIPTION [31:16] Limit Reset 0000h
7.4.26 CAPABILITY POINTER OFFSET
31:8 FUNCTION Reserved Capability Pointer TYPE DESCRIPTION Reset Capability pointer Reset
7.4.27 EXPANSION BASE ADDRESS REGISTER OFFSET
31:0 FUNCTION Expansion Base Address TYPE DESCRIPTION Expansion supported. Reset 00000000h
7.4.28 INTERRUPT LINE REGISTER OFFSET
FUNCTION Interrupt Line TYPE DESCRIPTION These bits apply reverse bridge only. initialization code program tell which input interrupt controller PI7C9X110's INTA_L connected Reset 00000000
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.29 INTERRUPT REGISTER OFFSET
15:8 FUNCTION Interrupt TYPE DESCRIPTION These bits apply reverse bridge only. Designates interrupt INTA_L, used Reset when forward mode when reverse mode.
7.4.30 BRIDGE CONTROL REGISTER OFFSET
FUNCTION Parity Error Response Enable TYPE DESCRIPTION Ignore parity errors secondary Enable parity error detection secondary FORWARD BRIDGE Controls response uncorrectable address attribute data errors secondary REVERSE BRIDGE Controls setting master data parity error response received poisoned from secondary (PCIe link) Reset Disable forwarding SERR_L ERR_FATAL ERR_NONFATAL Enable forwarding SERR_L ERR_FATAL ERR_NONFATAL Reset (FORWARD BRIDGE) REVERSE BRIDGE Forward downstream addresses address range defined Base Limit registers Forward upstream addresses address range defined Base Limit registers that first 64KB address space (top bytes each block) Reset forward compatible memory addresses from primary secondary, unless they enabled forwarding defined memory address ranges Forward compatible memory addresses from primary secondary enable memory enable bits set), independent enable Execute 10-bit address decodes accesses Execute 16-bit address decode accesses Reset report master aborts (return FFFFFFFFh reads discards data write) Report master abort signaling target abort possible assertion SERR_L enabled). Reset force assertion RESET_L secondary forward bridge, generate reset PCIe link reverse bridge Force assertion RESET_L secondary forward bridge, generate reset PCIe link reverse bridge Reset Fast back-to-back supported Reset
SERR_L Enable
Enable
Enable
16-bit Decode
Master Abort Mode
Secondary Interface Reset
Fast Back-to-Back Enable
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Primary Master Timeout
TYPE
DESCRIPTION Primary discard timer counts clock cycles Primary discard timer counts clock cycles FORWARD BRIDGE ignored PI7C9X110 Reset Secondary discard timer counts clock cycles Secondary discard timer counts clock cycles REVERSE BRIDGE ignored PI7C9X110 Reset when discard timer expires delayed completion discarded interface forward reverse bridge Reset enable generate ERR_NONFATAL ERR_FATAL forward bridge, assert P_SERR_L reverse bridge result expiration discard timer interface. Reset Reset 0000
Secondary Master Timeout
Master Timeout Status
Discard Timer SERR_L Enable
31:28
Reserved
7.4.31 DATA BUFFERING CONTROL REGISTER OFFSET
FUNCTION Secondary Internal Arbiter's PARK Function TYPE DESCRIPTION Park last master Park PI7C9X110 secondary port Reset Enable memory read prefetching dynamic control PCIe read Disable memory read prefetching dynamic control PCIe read Reset Enable completion data prediction PCIe read. Disable completion data prediction Reset Reset These bits ignored PCI-X mode. cache line prefetch memory read multiple address prefetchable range interface Full prefetch address prefetchable range interface, PI7C9X110 will keep remaining data after disconnects external master during burst read with read multiple command until discard timer expires Full prefetch address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X110 will keep remaining data after read multiple terminated either external master PI7C9X110, until discard time expires Reset
Memory Read Prefetching Dynamic Control Disable
Completion Data Prediction Control
Reserved Read Multiple Prefetch Mode
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Read Line Prefetch Mode
TYPE
DESCRIPTION These bits ignored PCI-X mode. Once cache line prefetch memory read address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X110 will keep remaining data after disconnected external master during burst read with read line command, until discard timer expires Full prefetch memory read line address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X110 will keep remaining data after read line terminated either external master PI7C9X110, until discard timer expires Reset cache line prefetch memory read address prefetchable range interface Reserved Full prefetch memory read address prefetchable range interface Disconnect first DWORD Reset Retry master that repeats transaction with command code changes. Allows master change memory command code (MR, MRL, MRM) after received retry. PI7C9X110 will complete memory read transaction return data back master address byte enables same. Reset Reset Maximum byte count used PI7C9X110 when generating memory read requests PCIe link response memory read initiated [9:8], [7:6], [5:4] "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: bytes (default) bytes bytes bytes 1024 bytes 2048 bytes 4096 bytes bytes
Read Prefetch Mode
Special Delayed Read Mode Enable
14:12
Reserved Maximum Memory Read Byte Count
Reset
7.4.32 CHIP CONTROL REGISTER OFFSET
FUNCTION Flow Control Update Control TYPE DESCRIPTION Flow control updated every credits available Flow control updated every credit available Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Retry Counter Status
TYPE
DESCRIPTION retry counter expired since last reset retry counter expired since last reset Reset expiration limit Allow retries before expiration Allow retries before expiration Allow retries before expiration Reset Enable discard timer conjunction with [27] offset (bridge control register) Disable discard timer conjunction with [27] offset (bridge control register) Reset [24] offset forward bridge [25] offset reverse bridge indicate many clocks should allowed before discard timer expires clocks allowed before discard timer expires Reset Timer expires 25us Timer expires 0.5ms Timer expires Timer expires 25ms Reset Enable out-of-order capability between delayed transactions Disable out-of-order capability between delayed transactions Reset Timer expires 50us Timer expires 10ms Timer expires 50ms Timer disabled Reset memory transactions from PCI-X PCIe will mapped memory transactions from PCI-X PCIe will mapped Traffic Class defined [29:27] offset 40h. Reset Reset Normal mode Enable serial link interface loopback mode TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. transaction from will loop back forward bridge Reset PI7C9X110 configuration space accessed from both interfaces PI7C9X110 configuration space only accessed from secondary interface. Primary accessed receives completion with status forward bridge, target retry reverse bridge Reset
18:17
Retry Counter Control
Discard Timer Disable
Discard Timer Short Duration
22:21
Configuration Request Retry Timer Counter Value Control
Delayed Transaction Order Control
25:24
Completion Timer Counter Value Control
Isochronous Traffic Support Enable
29:27
Traffic Class Used Isochronous Traffic Serial Link Interface Loopback Enable
Primary Configuration Access Lockout
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.33 RESERVED REGISTER OFFSET
31:0 FUNCTION Reserved TYPE DESCRIPTION Reset 00000000h
7.4.34 ARBITER ENABLE REGISTER OFFSET
FUNCTION Enable Arbiter TYPE DESCRIPTION Disable arbitration internal PI7C9X110 request Enable arbitration internal PI7C9X110 request Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
7.4.35 ARBITER MODE REGISTER OFFSET
FUNCTION External Arbiter TYPE DESCRIPTION Enable internal arbiter CFN_L tied LOW) external arbiter CFN_L tied HIGH) Reset according what CFN_L tied Broken master timeout disable This enables internal arbiter count cycles while waiting FRAME_L become active when device's active idle. broken master timeout expires, device de-asserted. Reset
Broken Master Timeout Enable
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Broken Master Refresh Enable
TYPE
DESCRIPTION broken master will ignored forever after de-asserting REQ_L least clock Refresh broken master state after other masters have been served once Reset 08h: These bits initialization value counter used internal arbiter. controls number cycles that arbiter holds device's active after detecting REQ_L from another device. counter reloaded whenever asserted. every GNT, counter armed decrement when detects fall FRAME_L. arbiter fairness counter 00h, arbiter will remove device's until device deasserted REQ. Reset GNT_L de-asserted after granted master assert FRAME_L GNT_L de-asserts clock after clocks granted master asserting FRAME_L Reset Reset
19:12
Arbiter Fairness Counter
GNT_L Output Toggling Enable
Reserved
7.4.36 ARBITER PRIORITY REGISTER OFFSET
FUNCTION Arbiter Priority TYPE DESCRIPTION priority request internal PI7C9X110 High priority request internal PI7C9X110 Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset
Arbiter Priority
Arbiter Priority
Arbiter Priority
Arbiter Priority
Arbiter Priority
Arbiter Priority
Arbiter Priority
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Arbiter Priority
TYPE
DESCRIPTION priority request master High priority request master Reset Reset
Reserved
7.4.37 RESERVED REGISTERS OFFSET 7.4.38 EXPRESS TRANSMITTER/RECEIVER REGISTER OFFSET
FUNCTION Nominal Driver Current Control TYPE DESCRIPTION 20mA 10mA 28mA Reserved Reset 0000: 1.00 nominal driver current 0001: 1.05 nominal driver current 0010: 1.10 nominal driver current 0011: 1.15 nominal driver current 0100: 1.20 nominal driver current 0101: 1.25 nominal driver current 0110: 1.30 nominal driver current 0111: 1.35 nominal driver current 1000: 1.60 nominal driver current 1001: 1.65 nominal driver current 1010: 1.70 nominal driver current 1011: 1.75 nominal driver current 1100: 1.80 nominal driver current 1101: 1.85 nominal driver current 1110: 1.90 nominal driver current 1111: 1.95 nominal driver current Reset 0000 0000: 0.00 0001: -0.35 0010: -0.72 0011: -1.11 0100: -1.51 0101: -1.94 0110: -2.38 0111: -2.85 1000: -3.35 1001: -3.88 1010: -4.44 1011: -5.04 1100: -5.68 1101: -6.38 1110: -7.13 1111: -7.96 Reset 1000 ohms ohms ohms ohms Reset
Driver Current Scale Multiple Control
11:8
Driver De-emphasis Level Control
13:12
Transmitter Termination Control
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PI7C9X110
PCIe-to-PCI Reversible Bridge
15:14
FUNCTION Receiver Termination Control
TYPE
DESCRIPTION ohms ohms ohms ohms Reset Reset
29:16
Reserved
7.4.39 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET
31:30 FUNCTION Memory Write Fragment Control TYPE DESCRIPTION Upstream Memory Write Fragment Control Fragment 32-byte boundary Fragment 64-byte boundary Fragement 128-byte boundary Reset
7.4.40 RESERVED REGISTER OFFSET 7.4.41 EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET
FUNCTION Initiate EEPROM Read Write Cycle TYPE DESCRIPTION This will reset after EEPROM operation finished. EEPROM AUTOLOAD disabled Starts EEPROM Read Write cycle Reset Read Write Reset EEPROM acknowledge always received during EEPROM cycle EEPROM acknowledge received during EEPROM cycle Reset EEPROM autoload successfully completed EEPROM autoload successfully completed Reset Where PCLK 125MHz PCLK 4096 PCLK 2048 PCLK 1024 PCLK Reset Enable EEPROM autoload Disable EEPROM autoload Reset Normal speed EEPROM autoload Increase EEPROM autoload Reset
Control Command EEPROM
EEPROM Error
EPROM Autoload Complete Status
EEPROM Clock Frequency Control
EEPROM Autoload Control
Fast EEPROM Autoload Control
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION EEPROM Autoload Status
TYPE
DESCRIPTION EEPROM autoload going EEPROM autoload going Reset EEPROM word address EEPROM cycle Reset 0000000 EEPROM data written into EEPROM Reset 0000h
15:9
EEPROM Word Address
31:16
EEPROM Data
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.42 RESERVED REGISTER OFFSET 7.4.43 GPIO DATA CONTROL REGISTER OFFSET
11:0 15:12 19:16 23:20 27:24 31:28 FUNCTION Reserved GPIO Output Write-1-toClear GPIO Output Write-1-to-Set GPIO Output Enable Write1-to-Clear GPIO Output Enable Write1-to-Set GPIO Input Data Register TYPE DESCRIPTION Reset 000h Reset Reset Reset Reset Reset
7.4.44 RESERVED REGISTER OFFSET 7.4.45 PCI-X CAPABILITY REGISTER OFFSET
FUNCTION PCI-X Capability TYPE DESCRIPTION PCI-X Capability Reset
7.4.46 NEXT CAPABILITY POINTER REGISTER OFFSET
15:8 FUNCTION Next Capability Pointer TYPE DESCRIPTION Point power management Reset
7.4.47 PCI-X SECONDARY STATUS REGISTER OFFSET
FUNCTION 64-bit Device Secondary Interface 133MHz Capable TYPE DESCRIPTION 64-bit supported Reset When this PI7C9X110 133MHz capable secondary interface Reset forward bridge mode reverse bridge mode This read-only reverse bridge mode read-write forward bridge mode When this split completion been discarded PI7C9X110 secondary because requester accept split completion transaction Reset This forward bridge mode read-write reverse bridge mode When this unexpected split completion been received with requester equaled secondary number, device number, function number PI7X9X110 secondary interface Reset
Split Completion Discarded
Unexpected Split Completion
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Split Completion Overrun
TYPE
DESCRIPTION When this split completion been terminated PI7C9X110 with either retry disconnect next buffer full condition Reset When this split request delayed because PI7C9X110 able forward split request transaction secondary insufficient room within limit specified split transaction commitment limit field downstream split transaction control register Reset These bits only meaningful forward bridge mode. reverse bridge mode, three bits zero. 000: Conventional mode (minimum clock period applicable) 001: 66MHz (minimum clock period 15ns) 010: 133MHz (minimum clock period 7.5ns) 011: Reserved 1xx: Reserved Reset 0000000
Split Request Delayed
24:22
Secondary Clock Frequency
31:25
Reserved
7.4.48 PCI-X BRIDGE STATUS REGISTER OFFSET
FUNCTION Function Number TYPE DESCRIPTION Function number [10:8] type configuration transaction) Reset Device number [15:11] type configuration transaction) assigned PI7C9X110 connection system hardware. Each time PI7C9X110 addressed configuration write transaction, bridge updates this register with contents [15:11] address phase configuration transaction, regardless which register PI7C9X110 addressed transaction. PI7C9X110 addressed configuration write transaction following true: transaction uses configuration write command IDSEL asserted during address phase [1:0] (type configuration transaction) [10:8] configuration address contain appropriate function number Reset 11111 Additional address from which contents primary number register type configuration space header read. PI7C9X110 uses number, device number, function number fields create completer when responding with split completion read internal PI7C9X110 register. These fields also used cases when interface conventional mode other PCI-X mode. Reset 11111111 64-bit supported Reset When this PI7C9X110 133MHz capable primary interface Reset forward bridge mode reverse bridge mode
Device Number
15:8
Number
64-bit Device Primary Interface 133MHz Capable
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PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Split Completion Discarded
TYPE
DESCRIPTION This read-only reverse bridge mode read-write forward bridge mode When this split completion been discarded PI7C9X110 primary because requester accept split completion transaction Reset This forward bridge mode read-write reverse bridge mode When this unexpected split completion been received with requester equaled primary number, device number, function number PI7X9X110 primary interface Reset When this split completion been terminated PI7C9X110 with either retry disconnect next buffer full condition Reset When this split request delayed because PI7C9X110 able forward split request transaction primary insufficient room within limit specified split transaction commitment limit field downstream split transaction control register Reset 0000000000
Unexpected Split Completion
Split Completion Overrun
Split Request Delayed
31:22
Reserved
7.4.49 UPSTREAM SPLIT TRANSACTION REGISTER OFFSET
15:0 FUNCTION Upstream Split Transaction Capability TYPE DESCRIPTION Upstream Split Transaction Capability specifies size buffer unit ADQs) store split completions memory read. applies requesters secondary addressing completers primary bus. 0010h value shows that buffer ADQs bytes storage Reset 0010h Upstream Split Transaction Commitment Limit indicates cumulative sequence size commitment limit units ADQs. This field programmed value equal content split capability field. example, limit FFFFh, PI7C9X110 allowed forward split requests size regardless amount buffer space available. split transaction commitment limit 0010h that same value split transaction capability. Reset 0010h
31:16
Upstream Split Transaction Commitment Limit
7.4.50 DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET
15:0 FUNCTION Downstream Split Transaction Capability TYPE DESCRIPTION Downstream Split Transaction Capability specifies size buffer unit ADQs) store split completions memory read. applies requesters primary addressing completers secondary bus. 0010h value shows that buffer ADQs bytes storage Reset 0010h
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PI7C9X110
PCIe-to-PCI Reversible Bridge
31:16
FUNCTION Downstream Split Transaction Commitment Limit
TYPE
DESCRIPTION Downstream Split Transaction Commitment Limit indicates cumulative sequence size commitment limit units ADQs. This field programmed value equal content split capability field. example, limit FFFFh, PI7C9X110 allowed forward split requests size regardless amount buffer space available. split transaction commitment limit 0010h that same value split transaction capability. Reset 0010h
7.4.51 POWER MANAGEMENT REGISTER OFFSET
FUNCTION Power Management TYPE DESCRIPTION Power Management Register Reset
7.4.52 NEXT CAPABILITY POINTER REGISTER OFFSET
15:8 FUNCTION Next Pointer TYPE DESCRIPTION Next pointer (point Subsystem Subsystem Vendor Reset
7.4.53 POWER MANAGEMENT CAPABILITY REGISTER OFFSET
18:16 FUNCTION Version Number TYPE DESCRIPTION Version number that complies with revision Power Management Interface specification. Reset clock required PME_L generation Reset Reset special initialization this function beyond standard configuration header required following transition un-initialized state Reset 000: 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset power management supported Reset power management supported Reset PME_L supported cold, hot, states. Reset 11001
Clock
Reserved Device Specific Initialization (DSI)
24:22
Current
Power Management
Power Management
31:27
PME_L Support
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.54 POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET
FUNCTION Power State TYPE DESCRIPTION Power State used determine current power state PI7C9X110. non-implemented state written this register, PI7C9X110 will ignore write data. When present state changing state programming this register, power state change causes device reset without activating RESET_L PCI/PCI-X interface state state implemented state implemented state Reset Reset 000000 PME_L assertion disabled PME_L assertion enabled Reset Data register implemented Reset 0000 Data register implemented Reset PME_L supported Reset
Reserved Enable
12:9
Data Select
14:13
Data Scale
Status
RWCS
7.4.55 PCI-TO-PCI SUPPORT EXTENSION REGISTER OFFSET
21:16 FUNCTION Reserved B2/B3 Support TYPE DESCRIPTION Reset 000000 support D3hot Reset Power/Clock Disabled Reset Data register implemented Reset
Power/Clock Control Enable Data Register
31:24
7.4.56 RESERVED REGISTERS OFFSET 7.4.57 CAPABILITY REGISTER OFFSET
FUNCTION Capability TYPE DESCRIPTION Capability Slot Identification. default turned through EEPROM interface Reset
7.4.58 NEXT POINTER REGISTER OFFSET
15:8 FUNCTION Next Pointer TYPE DESCRIPTION Next pointer points Express capabilities register Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.59 SLOT NUMBER REGISTER OFFSET
20:16 FUNCTION Expansion Slot Number TYPE DESCRIPTION Expansion slot number Reset 00000 First chassis Reset Reset
First Chassis
23:22
Reserved
7.4.60 CHASSIS NUMBER REGISTER OFFSET
31:24 FUNCTION Chassis Number TYPE DESCRIPTION Chassis number Reset
7.4.61 SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET
FUNCTION S_CLKOUT0 Enable TYPE DESCRIPTION S_CLKOUT (Slot Enable forward bridge mode only enable S_CLKOUT0 enable S_CLKOUT0 enable S_CLKOUT0 disable S_CLKOUT0 driven Reset S_CLKOUT (Slot Enable forward bridge mode only enable S_CLKOUT1 enable S_CLKOUT1 enable S_CLKOUT1 disable S_CLKOUT1 driven Reset S_CLKOUT (Slot Enable forward bridge mode only enable S_CLKOUT2 enable S_CLKOUT2 enable S_CLKOUT2 disable S_CLKOUT2 driven Reset S_CLKOUT (Slot Enable forward bridge mode only enable S_CLKOUT3 enable S_CLKOUT3 enable S_CLKOUT3 disable S_CLKOUT3 driven Reset S_CLKOUT (Device Enable forward bridge mode only enable S_CLKOUT4 disable S_CLKOUT4 driven Reset
S_CLKOUT1 Enable
S_CLKOUT2 Enable
S_CLKOUT3 Enable
S_CLKOUT4 Enable
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION S_CLKOUT5 Enable
TYPE
DESCRIPTION S_CLKOUT (Device Enable forward bridge mode only enable S_CLKOUT5 disable S_CLKOUT5 driven Reset S_CLKOUT (Device Enable forward bridge mode only enable S_CLKOUT6 disable S_CLKOUT6 driven Reset S_CLKOUT (Device Enable forward bridge mode only enable S_CLKOUT7 disable S_CLKOUT7 driven Reset S_CLKOUT (the bridge) Enable forward bridge mode only enable S_CLKOUT8 disable S_CLKOUT8 driven Reset Secondary clock stop status secondary clock stopped secondary clock stopped Reset disable protocol enable protocol Reset Stop secondary clock only when bridge D3hot state Stop secondary clock whenever secondary idle there requests from primary Reset Reset 0000h
S_CLKOUT6 Enable
S_CLKOUT7 Enable
S_CLKOUT8 Enable
Secondary Clock Stop Status
Secondary Clkrun Protocol Enable
Clkrun Mode
31:16
Reserved
7.4.62 CAPABILITY REGISTER OFFSET
FUNCTION Capability TYPE DESCRIPTION Capability subsystem subsystem vendor Reset
7.4.63 NEXT POINTER REGISTER OFFSET
15:8 FUNCTION Next Item Pointer TYPE DESCRIPTION Next item pointer (point Express Capability default programmed Slot Identification Capability enabled) Reset
7.4.64 RESERVED REGISTER OFFSET
31:16 FUNCTION Reserved TYPE DESCRIPTION Reset 0000h
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.65 SUBSYSTEM VENDOR REGISTER OFFSET
15:0 FUNCTION Subsystem Vendor TYPE DESCRIPTION Subsystem vendor identifies particular add-in card subsystem Reset
7.4.66 SUBSYSTEM REGISTER OFFSET
31:16 FUNCTION Subsystem TYPE DESCRIPTION Subsystem identifies particular add-in card subsystem Reset
7.4.67 EXPRESS CAPABILITY REGISTER OFFSET
FUNCTION Express Capability TYPE DESCRIPTION Express capability Reset
7.4.68 NEXT CAPABILITY POINTER REGISTER OFFSET
15:8 FUNCTION Next Item Pointer TYPE DESCRIPTION Next item pointer (points register) Reset
7.4.69 EXPRESS CAPABILITY REGISTER OFFSET
19:16 23:20 FUNCTION Capability Version Device Port Type TYPE DESCRIPTION Reset 0000: Express endpoint device 0001: Legacy Express endpoint device 0100: Root port Express root complex 0101: Upstream port Express switch 0110: Downstream port Express switch 0111: Express bridge 1000: Express bridge Others: Reserved Reset Forward Bridge Reverse Bridge Reset Forward Bridge Reverse Bridge Reset Reset
29:25 31:30
Slot Implemented Interrupt Message Number Reserved
7.4.70 DEVICE CAPABILITY REGISTER OFFSET
FUNCTION Maximum Payload Size TYPE DESCRIPTION 000: bytes 001: bytes 010: bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Phantom Functions
TYPE
DESCRIPTION phantom functions supported Reset 8-bit field supported Reset Endpoint L0's acceptable latency 000: less than 001: 010: 011: 100: 101: 110: 111: more than Reset Endpoint L1's acceptable latency 000: less than 001: 010: 011: 100: 101: 110: 111: more than Reset Plug disabled Plug enabled Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enable Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enable Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset These bits Set_Slot_Power_Limit message Reset This value Set_Slot_Power_Limit message Reset Reset
8-bit Field
Endpoint L0's Latency
11:9
Endpoint L1's Latency
Attention Button Present
Attention Indicator Present
Power Indicator Present
17:15 25:18
Reserved Captured Slot Power Limit Value Captured Slot Power Limit Scale Reserved
27:26
31:28
7.4.71 DEVICE CONTROL REGISTER OFFSET
FUNCTION Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable TYPE DESCRIPTION Reset Reset Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Unsupported Request Reporting Enable Relaxed Ordering Enable Payload Size
TYPE
DESCRIPTION Reset Relaxed Ordering disabled Reset This field sets maximum payload size PI7C9X110 000: bytes 001: bytes 010: bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset Reset Phantom functions supported Reset Auxiliary power supported Reset Bridge never sets Snoop attribute transaction initiates Reset This field sets maximum Read Request Size device requester 000: bytes 001: bytes 010: bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset Reset
Extended Field Enable Phantom Functions Enable
Auxiliary Power Enable
Snoop Enable
14:12
Maximum Read Request Size
Configuration Retry Enable
7.4.72 DEVICE STATUS REGISTER OFFSET
FUNCTION Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected Power Detected Transaction Pending TYPE DESCRIPTION Reset Reset Reset Reset Reset transaction pending transaction layer interface Transaction pending transaction layer interface Reset Reset 0000000000
31:22
Reserved
7.4.73 LINK CAPABILITY REGISTER OFFSET
FUNCTION TYPE DESCRIPTION
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
FUNCTION Maximum Link Speed
TYPE
DESCRIPTION Indicates maximum speed Express link 0001: 2.5Gb/s link Reset Indicates maximum width Express link reset) 000000: reserved 000001: 000010: 000100: 001000: 001100: 010000: 100000: Reset 000001 This field indicates level Active State Power Management Support reserved L0's entry supported reserved L0's L1's supported Reset Reset Reset Reset Reset
Maximum Link Width
11:10
ASPM Support
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
7.4.74 LINK CONTROL REGISTER OFFSET
FUNCTION ASPM Control TYPE DESCRIPTION This field controls level ASPM supported Express link disabled L0's entry enabled L1's entry enabled L0's L1's entry enabled Reset Reset Read completion boundary supported Reset Forward Bridge Reset Forward Bridge Reset Reset Reset Reset
Reserved Read Completion Boundary (RCB) Link Disable
Retrain Link
15:8
Common Clock Configuration Extended Sync Reserved
7.4.75 LINK STATUS REGISTER OFFSET
FUNCTION TYPE DESCRIPTION
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
19:16
FUNCTION Link Speed
TYPE
DESCRIPTION This field indicates negotiated speed Express link 001: 2.5Gb/s link Reset 000000: reserved 000001: 000010: 000100: 001000: 001100: 010000: 100000: Reset 000001 Reset Reset Reset Reset
25:20
Negotiated Link Width
31:29
Link Train Error Link Training Slot Clock Configuration Reserved
7.4.76 SLOT CAPABILITY REGISTER OFFSET
FUNCTION Attention Button Present TYPE DESCRIPTION Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Reset Reset Reset
Power Controller Present Sensor Present
Attention Indicator Present
Power Indicator Present
Plug Surprise Plug Capable
14:7 16:15 18:17 31:19
Slot Power Limit Value Slot Power Limit Scale Reserved Physical Slot Number
7.4.77 SLOT CONTROL REGISTER OFFSET
FUNCTION Attention Button Present Enable Power Fault Detected Enable TYPE DESCRIPTION Reset Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
15:11
FUNCTION Sensor Changed Enable Presence Detect Changed Enable Command Completed Interrupt Enable Plug Interrupt Enable Attention Indicator Control Power Indicator Control Power Controller Control Reserved
TYPE
DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset
7.4.78 SLOT STATUS REGISTER OFFSET
31:23 FUNCTION Attention Button Pressed Power Fault Detected Sensor Changed Presence Detect Changed Command Completed Sensor State Presence Detect State Reserved TYPE DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset
7.4.79 XPIP CONFIGURATION REGISTER OFFSET
FUNCTION Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct Configuration State when LTSSM state Internal Selection Debug Mode Negotiate Lane Number Times Number Counter Reserved LTSSM Enter Timer Default Value TYPE DESCRIPTION Reset Reset Reset Reset
12:8 15:13 31:16
Reset Reset Reset Reset Reset 0400h
7.4.80 XPIP CONFIGURATION REGISTER OFFSET
15:10 31:16 FUNCTION L0's Lifetime Timer Reserved Lifetime Timer TYPE DESCRIPTION Reset Reset Reset
7.4.81 XPIP CONFIGURATION REGISTER OFFSET
FUNCTION Recovery Time number order sets) L0's Exit Latency Reserved Exit Latency Reserved TYPE DESCRIPTION Reset Fast Training Sequence order composes K28.5 (COM) Symbol three K28.1 Symbols. Reset Reset Reset Reset
14:8 22:16
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.82 SWAP SWITCH DEBOUNCE COUNTER OFFSET
31:24 FUNCTION Swap Debounce Counter TYPE DESCRIPTION Swap enabled, this counter read-write able. This counter read only (RO) Swap disabled 00h: 01h: 02h: 03h: FFh: 256ms Reset
7.4.83 CAPABILITY REGISTER OFFSET
FUNCTION Capability Register TYPE DESCRIPTION Reset
7.4.84 NEXT POINTER REGISTER OFFSET
15:8 FUNCTION Next Pointer TYPE DESCRIPTION Next pointer (F0h, points capabilities) Reset
7.4.85 REGISTER OFFSET
17:16 23:18 30:24 FUNCTION Reserved Address Read/Write Cycle Reserved Operation TYPE DESCRIPTION Reset Reset Reset Generate read cycle from EEPROM address specified bits [7:2] offset D8h. This remains until EEPROM cycle finished, after which then `1'. Data reads available register ECh. Generate write cycle EEPROM address specified bits [7:2] offset D8h. This remains until EEPROM cycle finished, after which then cleared `0'. Reset
7.4.86 DATA REGISTER OFFSET
31:0 FUNCTION Data TYPE DESCRIPTION Data (EEPROM data [address 0x40]) least significant byte this register corresponds byte address specified address register. data read form written this register uses normal byte transfer capabilities. Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.87 RESERVED REGISTERS OFFSET 7.4.88 MESSAGE SIGNALED INTERRUPTS REGISTER
FUNCTION Capability Registers TYPE DESCRIPTION Reset
7.4.89 NEXT CAPABILITIES POINTER REGISTER
15:8 FUNCTION Next Pointer TYPE DESCRIPTION Next pointer (00h indicates capabilities) Reset
7.4.90 MESSAGE CONTROL REGISTER OFFSET
FUNCTION Enable TYPE DESCRIPTION Disable default INTx interrupt Enable interrupt service ignore INTx interrupt pins 000: message requested 001: messages requested 010: messages requested 011: messages requested 100: messages requested 101: messages requested 110: reserved 111: reserved Reset 000: message requested 001: messages requested 010: messages requested 011: messages requested 100: messages requested 101: messages requested 110: reserved 111: reserved Reset Reset Reset
19:17
Multiple Message Capable
22:20
Multiple Message Enable
31:24
64-bit Address Capable Reserved
7.4.91 MESSAGE ADDRESS REGISTER OFFSET
31:2 FUNCTION Reserved System Specified Message Address TYPE DESCRIPTION Reset Reset
7.4.92 MESSAGE UPPER ADDRESS REGISTER OFFSET
31:0 FUNCTION System Specified Message Upper Address TYPE DESCRIPTION Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.93 MESSAGE DATA REGISTER OFFSET
15:0 31:16 FUNCTION System Specified Message Data Reserved TYPE DESCRIPTION Reset Reset
7.4.94 ADVANCE ERROR REPORTING CAPABILITY REGISTER OFFSET 100h
15:0 FUNCTION Advance Error Reporting Capability TYPE DESCRIPTION Reset 0001h
7.4.95 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER OFFSET 100h
19:16 FUNCTION Advance Error Reporting Capability Version TYPE DESCRIPTION Reset
7.4.96 NEXT CAPABILITY OFFSET REGISTER OFFSET 100h
31:20 FUNCTION Next Capability Offset TYPE DESCRIPTION Next capability offset (150h points capability) Reset 150h
7.4.97 UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h
11:5 31:21 FUNCTION Training Error Status Reserved Data Link Protocol Error Status Reserved Poisoned Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed Status ECRC Error Status Unsupported Request Error Status Reserved TYPE RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset
7.4.98 UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h
11:5 FUNCTION Training Error Mast Reserved Data Link Protocol Error Mask Reserved Poisoned Mask Flow Control Protocol Error Mask TYPE DESCRIPTION Reset Reset Reset Reset Reset Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
31:21
FUNCTION Completion Timeout Mask Completion Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed Mask ECRC Error Mask Unsupported Request Error Mask Reserved
TYPE
DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset
7.4.99 UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch
11:5 31:21 FUNCTION Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed Severity ECRC Error Severity Unsupported Request Error Severity Reserved TYPE DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset
7.4.100 CORRECTABLE ERROR STATUS REGISTER OFFSET 110h
11:9 31:13 FUNCTION Receiver Error Status Reserved Status DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Reserved TYPE RWCS RWCS RWCS RWCS RWCS DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset
7.4.101 CORRECTABLE ERROR MASK REGISTER OFFSET 114h
11:9 31:13 FUNCTION Receiver Error Mask Reserved Mask DLLP Mask REPLAY_NUM Rollover Mask Reserved Replay Timer Timeout Mask Reserved TYPE DESCRIPTION Reset Reset Reset Reset Reset Reset Reset Reset
Page Pericom Semiconductor November 2007, Revision
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.102 ADVANCED ERROR CAPABILITIES CONTROL REGISTER OFFSET 118h
31:9 FUNCTION First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved TYPE DESCRIPTION Reset Reset Reset Reset Reset Reset
7.4.103 HEADER REGISTER OFFSET 11Ch
15:8 23:16 31:24 FUNCTION Header Byte Header Byte Header Byte Header Byte TYPE DESCRIPTION Reset Reset Reset Reset
7.4.104 HEADER REGIS
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