EZ-ColorHB Controller Controller Configurable Dimmers Support Ind

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EZ-ColorHB Controller Controller Configurable Dimmers Support Ind

Datasheet Thumbnail

Top Searches for this datasheet

CY8CLED08
EZ-ColorHB Controller
Controller Configurable Dimmers Support Independent Channels 8-32 Bits Resolution Channel Dynamic Reconfiguration Enables Controller plus other Features; Battery Charging, Motor Control Visual Embedded Design, PSoC Express Based Express Drivers Binning Compensation Temperature Feedback DMX512 PrISM Modulation Technology Reduces Radiated Reduces Frequency Blinking Powerful Harvard Architecture Processor Processor Speeds 5.25V Operating Voltage Operating Voltages down 1.0V using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash
Advanced Peripherals (PSoC Blocks) Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Full-Duplex UART Multiple SPIMasters Slaves Connectable GPIO Pins Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Complex Peripherals Combining Blocks Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink GPIO Pull Pull down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Four Analog Outputs GPIO Configurable Interrupt GPIO Complete Development Tools Free Development Software PSoC PSoC Express Full featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure KBytes Trace Memory
Cypress Semiconductor Corporation Document Number: 001-12981 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised June 2007
CY8CLED08
Overview Block Diagram
Port Port Port Port Port Port Analog Drivers
PSoC CORE
System
Global Digital Interconnect SRAM Bytes Interrupt Controller
Global Analog Interconnect Flash Sleep Watchdog
SROM
Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Analog Input Muxing
Digital Clocks
Multiply Accum.
Decimator System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Document Number: 001-12981 Rev.
Page
CY8CLED08
EZ-Color Functional Overview
Cypress' EZ-Color family devices offers ideal control solution High Brightness applications requiring intelligent dimming control. EZ-Color devices combine power flexibility PSoC (Programmable System-on-ChipTM); with Cypress' PrISM (precise illumination signal modulation) modulation technology providing lighting designers fully customizable integrated lighting solution platform. EZ-Color family supports independent channels with bits resolution channel, enabling lighting designers flexibility choose array size color quality. PSoC Express software, with lighting specific drivers, significantly development time simplify implementation fixed color points through temperature binning compensation. EZ-Color's virtually limitless analog digital customization allow simple integration features addition intelligent lighting, such Battery Charging, Image Stabilization, Motor Control during development process. These features, along with Cypress' best-in-class quality design support, make EZ-Color ideal choice intelligent control applications.
Resource), provide flexibility integrate almost timing requirement into EZ-Color device. EZ-Color GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
Digital System
Digital System composed digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Figure Digital System Block Diagram
Port Port Port Port Port Port
Digital Clocks From Core
System
Analog System
Target Applications
Backlight Large Signs
Input Configuration
DIGITAL SYSTEM
Digital PSoC Block Array
DBB00 DBB01 DCB02 DCB03 Output Configuration
General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights
Input Configuration
DBB10 DBB11 DCB12
DCB13
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. utilizes interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, bytes SRAM data storage, EEPROM emulated using Flash. Program Flash utilizes four protection levels blocks bytes, allowing customized software protection. EZ-Color family incorporates flexible internal clock generators, including (internal main oscillator) accurate 2.5% over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. crystal accuracy desired, (32.768 external crystal oscillator) available Real Time Clock (RTC) optionally generate crystal-accurate system clock using PLL. clocks, together with programmable clock dividers System Document Number: 001-12981 Rev.
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include those listed below.
PrISM bit) PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity slave master slave multi-master available System Resource) Cyclical Redundancy Checker/Generator bit) IrDA Generators bit) Page
CY8CLED08
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies EZ-Color device family. This allows optimum choice system resources your application. Family resources shown table titled EZ-Color Device Characteristics.
Figure Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
P2[3]
Analog System
Analog System composed configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common EZ-Color analog functions (most available user modules) listed below.
P2[1]
P2[4] P2[2] P2[0]
Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (four with drive Core Resource) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible
Interface Digital System ACB00 ASC10 ASD20
ACI0[1:0]
Array Input Configuration
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog Reference
RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks, shown figure below.
Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-12981 Rev.
Page
CY8CLED08
Additional System Resources
System Resources, some which have been previously listed, provide additional capability useful complete systems. Additional resources include multiplier, decimator, switch mode pump, voltage detection, power reset. Statements describing merits each system resource below.
module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter.
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist general math digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs.
EZ-Color Device Characteristics
Depending your EZ-Color device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific EZ-Color device groups. device covered this data sheet shown highlighted table Table EZ-Color Device Characteristics
PSoC Part Number CY8CLED04 CY8CLED08 CY8CLED16 CapSense Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size Flash Size
Bytes
Document Number: 001-12981 Rev.
Page
CY8CLED08
Getting Started
quickest path understanding EZ-Color silicon reading this data sheet using PSoC Express Integrated Development Environment (IDE). This data sheet overview EZ-Color integrated circuit presents specific pin, register, electrical specifications. up-to-date Ordering, Packaging, Electrical Specification information, reference latest device data sheets
Development Tools
PSoC Express high-level design tool creating embedded systems with devices using Cypress's PSoC Mixed-Signal technology. With PSoC Express create complete embedded solution including necessary on-chip peripherals, block configuration, interrupt handling application software without writing single line assembly code. PSoC Express solves design problems think about system:
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PSoC development. Cypress Online Store site http://www.cypress.com, click Online Store shopping cart icon bottom page, click EZ-Color view current list available items.
Select input output devices based upon system requirements. communications interface define interface system (using registers). Define when output device changes state based upon other system devices. Based upon design, automatically select more PSoC Mixed-Signal Controllers that match system requirements. Figure PSoC Express
Technical Training Modules
Free PSoC technical training modules available users PSoC. Training modules cover designing, debugging, advanced analog CapSense.
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com, click Design Support located left side page, select CYPros Consultants.
Technical Support
PSoC application engineers take pride fast accurate response. They reached with 4-hour guaranteed response
PSoC Express Subsystems
Express Editor Express Editor allows create designs visually dragging dropping inputs, outputs, communication interfaces, other design elements, then describing logic that controls them. Project Manager Project Manager allows work with your applications projects PSoC Express. PSoC Express application level container projects their associated files. Each project contains design that uses single PSoC device. application contain multiple projects creating application that uses multiple PSoC devices keep projects together single application. Most files associated with project automatically generated PSoC Express during build process, make changes directly custom.c custom.h files
Application Notes
long list application notes will assist every aspect your design effort. view PSoC application notes, http://www.cypress.com site select Application Notes under Design Resources list located center page. Application Notes sorted date default.
Document Number: 001-12981 Rev.
Page
CY8CLED08
also your custom code project Project Manager.
Acronyms Used
following table lists acronyms that used this document.
Acronym EEPROM GPIO IPOR alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor slow switch mode pump static random access memory Description
Application Editor
Application Editor allows edit custom.c custom.h well assembly language source code that your project. With PSoC Express create application software without writing single line assembly code, have full featured application editor your finger tips want Build Manager Build Manager gives ability build application software, assign pins, generate data sheet, schematic, your project. Board Monitor Board Monitor debugging tool designed used while attached prototype board through communication interface that allows monitor changes various design elements real time. default communication board monitor I2C. uses CY3240-I2USB Bridge Debugging/Communication Kit. Tuners Tuner visual interface Board Monitor that allows view performance drivers your test board while your program running, manually override values results.
Document Conventions
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
PPOR PSoC® SLIMO SRAM
Numeric Naming
Hexidecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexidecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (e.g., 01010100b' `01000011b'). Numbers indicated decimal.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Information
Pinouts
48-Pin Part Pinout SSOP Table 48-Pin Part Pinout (SSOP)
Input Power Type Digital Power Analog
Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4]
Description
Analog column input. Analog column input column output. Analog column input column output. Analog column input.
48-Pin Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, XTALin, P1[1]
Direct switched capacitor block input. Direct switched capacitor block input.
Switch Mode Pump (SMP) connection external components required.
Serial Clock (SCL). Serial Data (SDA). Crystal Input (XTALin), Serial Clock (SCL), ISSP SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP SDATA.* Optional External Clock Input (EXTCLK).
SSOP
P0[6], P0[4], P0[2], P0[0], P2[6], External VRef P2[4], External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout,
Digital
Analog
Name
P4[6] P4[6]
Description
P2[0] P2[2] P2[4] P2[6]
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
Power
P0[0] P0[2] P0[4] P0[6]
Active high external reset with internal pull down.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset).
Document Number: 001-12981 Rev.
Page
CY8CLED08
48-Pin Part Pinout Table 48-Pin Part Pinout (QFN**)
Power Input Power
Type Digital
Power
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Direct switched capacitor block input. Direct switched capacitor block input.
Switch Mode Pump (SMP) connection external components required.
Serial Clock (SCL). Serial Data (SDA). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). package center that must connected ground (Vss).
Document Number: 001-12981 Rev.
SCL, XTALin, P1[1] SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2]
P5[1] SCL, P1[7]
SDA, P1[5] P1[3]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3]
P0[6], P0[4], P0[2], P0[0], P2[6], External VRef P2[4], External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0]
Analog
Name
Description
48-Pin PSoC Device
P2[5] P2[7] P0[1], P0[3], P0[5], P0[7],
(Top View)
Page
CY8CLED08
Register Reference
This chapter lists registers CY8CLED08 EZ-Color device.
Register Mapping Tables
device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields reserved should accessed.
Register Conventions
register conventions specific this section listed following table. Register Mapping Tables
Convention Description
Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Table Register Bank Table: User Space
Name
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2
Addr (0,Hex)
Access
Name
Addr (0,Hex)
Access
Name
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
Addr (0,Hex)
Access
Name
Addr (0,Hex)
Access
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH
DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0
AMX_IN
ARF_CR CMP_CR0
Blank fields Reserved should accessed.
Access specific.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table Register Bank Table: User Space (continued)
Name
DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0
Addr (0,Hex)
Access
Name
ASY_CR CMP_CR1
Addr (0,Hex)
Access
Name
Addr (0,Hex)
Access
Name
DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2
Addr (0,Hex)
Access
ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1
CPU_F CPU_SCR1 CPU_SCR0
Blank fields Reserved should accessed.
Access specific.
Table Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 (1,Hex) Blank fields Reserved should accessed. Access Name Addr (1,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) Access OSC_GO_EN OSC_CR4 OSC_CR3 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Name Addr (1,Hex) Access
Access specific.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table Register Bank Table: Configuration Space (continued)
Name DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU (1,Hex) ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 Access Name CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 Addr (1,Hex) RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access Name Addr (1,Hex) Access specific. CPU_SCR1 CPU_SCR0 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR Access Name OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP Addr (1,Hex) Access
Blank fields Reserved should accessed.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Electrical Specifications
This section presents electrical specifications CY8CLED08 EZ-Color device. most date electrical specifications, confirm that have most recent data sheet going Specifications valid -40oC 85oC 100oC, except where noted. Specifications devices running greater than valid -40oC 70oC 82oC. Figure Voltage versus Frequency
5.25
following table lists units measure that used this section. Table Units Measure
Symbol
Unit Measure
Symbol
Unit Measure
degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
Kbit
Vrms
4.75 Voltage 3.00
Frequency
Absolute Maximum Ratings
Table Absolute Maximum Ratings
Symbol Description Units
rati
Notes
TSTG
Storage Temperature
+100
Higher storage temperatures will reduce data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
VIOZ IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch-up Current
-0.5 Vss- 2000
+6.0
Human Body Model ESD.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Operating Temperature
Table Operating Temperature
Symbol Description Units
Notes
Ambient Temperature Junction Temperature
+100
temperature rise from ambient junction package specific. "Thermal Impedances" page user must limit power consumption comply with this requirement.
Electrical Characteristics
Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications
Symbol Description Units Notes
Supply Voltage Supply Current
3.00
5.25
Conditions 5.0V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions 3.3V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions with internal slow speed oscillator, 3.3V, Conditions with internal slow speed oscillator, 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V,
IDD3
Supply Current
ISBH ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal high temperature.a Reference Voltage (Bandgap) Silicon Reference Voltage (Bandgap) Silicon
ISBXTLH
VREF VREF
1.275 1.280
1.300 1.300
1.325 1.320
Trimmed appropriate Vdd. Trimmed appropriate Vdd.
Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This should compared with devices that have similar functions enabled. Refer "Ordering Information" page
Document Number: 001-12981 Rev.
Page
CY8CLED08
General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications
Symbol Description Units Notes
Pull Resistor Pull down Resistor High Output Level
4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
Output Level
0.75
COUT
Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input
Capacitive Load Pins Output
Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Operational Amplifier Specifications
Symbol Description Units Notes
Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Typical parameters apply 25°C design guidance only.
VOSOA
Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 35.0
V/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias)
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
CMRROA
Common Mode Rejection Ratio Power Power Medium Power High
GOLOA
Open Loop Gain Power Power Medium Power High
Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
VOHIGHOA
High Output Voltage Swing (internal signals) Power Power Medium Power High
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table Operational Amplifier Specifications (continued)
Symbol Description Units Notes
VOLOWOA
Output Voltage Swing (internal signals) Power Power Medium Power High 1200 2400 4600 1600 3200 6400
ISOA
Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High
PSRROA
Supply Voltage Rejection Ratio
(Vdd 2.25) (Vdd 1.25V) Vdd.
Table 3.3V Operational Amplifier Specifications
Symbol Description Units Notes
VOSOA
Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only 1.65 1.32 35.0
V/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
CMRROA
Common Mode Rejection Ratio Power Power Medium Power High
GOLOA
Open Loop Gain Power Power Medium Power High
Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
VOHIGHOA
High Output Voltage Swing (internal signals) Power Power Medium Power High only 1200 2400 4600 1600 3200 6400
VOLOWOA
Output Voltage Swing (internal signals) Power Power Medium Power High
ISOA
Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High
PSRROA
Supply Voltage Rejection Ratio
(Vdd 2.25) (Vdd 1.25V) Vdd.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications
Symbol Description Units Notes
VREFLPC ISLPC VOSLPC
power comparator (LPC) reference voltage range supply current voltage offset
Analog Output Buffer Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications
Symbol Description Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High
V/°C
VOHIGHOB
High Output Voltage Swing (Load ohms Vdd/2) Power Power High
VOLOWOB
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB
Supply Current Including Bias Cell Load) Power Power High
PSRROB
Supply Voltage Rejection Ratio
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table 3.3V Analog Output Buffer Specifications
Symbol Description Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High
V/°C
VOHIGHOB
High Output Voltage Swing (Load ohms Vdd/2) Power Power High
VOLOWOB
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB
Supply Current Including Bias Cell Load) Power Power High
PSRROB
Supply Voltage Rejection Ratio
Switch Mode Pump Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Switch Mode Pump (SMP) Specifications
Symbol Description Units Notes
VPUMP VPUMP IPUMP
Output Voltage Output Voltage Available Output Current VBAT 1.5V, VPUMP 3.25V VBAT 1.8V, VPUMP 5.0V
4.75 3.00
3.25
5.25 3.60
Configuration footnote.a Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.a Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.a
trip voltage 3.25V. trip voltage 5.0V. Configuration footnote.a trip voltage 5.0V. Configuration footnote.a trip voltage 3.25V. Configuration footnote.a Configuration footnote.a "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.a "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.a Load 5mA. Configuration footnote.a Load trip voltage 3.25V.
VBAT5V VBAT3V VBATSTART
VPUMP_Line
Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery Start Pump Line Regulation (over VBAT range)
VPUMP_Load
Load Regulation
VPUMP_Ripple
Output Voltage Ripple (depends capacitor/load) Efficiency Switching Frequency Switching Duty Cycle
mVpp
FPUMP DCPUMP
inductor, capacitor, Schottky diode.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Figure Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Analog Reference Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high.
Table Analog Reference Specifications
Symbol Description Units
Bandgap Voltage Reference AGND Vdd/2a AGND BandGapa
1.28 Vdd/2 0.030 0.043 P2[4] 0.011 0.009 0.018 Vdd/2)a -0.034
1.30 Vdd/2 P2[4] 0.000
1.32 Vdd/2 0.007 0.024 P2[4] 0.011 0.009 0.018 0.034
AGND P2[4] (P2[4] Vdd/2) AGND BandGapa AGND BandGapa
AGND Block Block Variation (AGND RefHi Vdd/2 BandGap RefHi BandGap
Vdd/2
0.06 P2[6] 0.06 P2[4] 0.06 P2[4] P2[6] 0.06 0.06
Vdd/2 0.01
0.01 P2[6] 0.01 P2[4] 0.01 P2[4] P2[6] 0.01 0.01
Vdd/2
0.06 P2[6] 0.06 P2[4] 0.06 P2[4] P2[6] 0.06 0.06
RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V)
Vdd/2 0.051
0.06 P2[6] 0.04 P2[4] 0.056 P2[4] P2[6] 0.056
Vdd/2 0.01
0.01 P2[6] 0.01 P2[4] 0.01 P2[4] P2[6] 0.01
Vdd/2 0.06
0.06 P2[6] 0.04 P2[4] 0.056 P2[4] P2[6] 0.056
AGND tolerance includes offsets local buffer PSoC block.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table 3.3V Analog Reference Specifications
Symbol Description Units
Bandgap Voltage Reference AGND Vdd/2a AGND BandGapa AGND P2[4] (P2[4] Vdd/2) AGND BandGapa AGND BandGapa AGND Block Block Variation (AGND RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) Vdd/2)a
1.28 Vdd/2 0.027 Allowed P2[4] 0.008 0.009 0.018 -0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.06 Allowed Allowed Allowed Allowed Allowed P2[4] P2[6] 0.048
1.30 Vdd/2
1.32 Vdd/2 0.005
P2[4] 0.000
P2[4] 0.009 0.009 0.018 0.034
P2[4] P2[6] 0.01
P2[4] P2[6] 0.057
P2[4] P2[6] 0.01
P2[4] P2[6] 0.048
AGND tolerance includes offsets local buffer PSoC block. Note Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V.
Analog PSoC Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog PSoC Block Specifications
Symbol Description Units Notes
Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap)
12.2
Document Number: 001-12981 Rev.
Page
CY8CLED08
Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV table below refer bits VLT_CR register. Table Specifications
Symbol Description Units Notes
Value PPOR Trip (positive ramp) VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value PUMP Trip VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 2.82 4.39 4.55 2.91 4.39 4.55
must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications
Symbol Description Units Notes
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (per block) Flash Endurance (total)a
50,000 1,800,000
Driving internal pull-down resistor. Driving internal pull-down resistor.
0.75 Years Erase/write cycles block. Erase/write cycles.
Flash Data Retention
maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Electrical Characteristics
Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications
Symbol Description Units Notes
FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW
Internal Main Oscillator Frequency Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Speed Oscillator Frequency External Crystal Oscillator Frequency Period Jitter (PLL) Lock Time Lock Time Gain Setting External Crystal Oscillator Startup External Crystal Oscillator Startup
23.4 0.93 0.93
32.768 23.986 1700 2800
24.6a
24.6a,b 12.3
Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Refer Digital Block Specifications below.
49.2a,b,d 24.6b,
2620 3800
Accuracy capacitor crystal dependent. duty cycle. Multiple (x732) crystal frequency.
TOSACC
crystal oscillator frequency within final value Tosacc period. Correct operation assumes properly loaded maximum drive level 32.768 crystal. 3.0V 5.5V,
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time
46.8
48.0 12.3 49.2a,c
Trimmed. Utilizing factory trim values.
4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
Figure Lock Timing Diagram
Enable
TPLLSLEW
FPLL
Gain
Document Number: 001-12981 Rev.
Page
CY8CLED08
Figure Lock Gain Setting Timing Diagram
Enable
TPLLSLEWLOW
FPLL
Gain
Figure External Crystal Oscillator Startup Timing Diagram
Select
F32K2
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ECO) Timing Diagram
Jitter32k
32K2
General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications
Symbol Description Units Notes
FGPIO TRiseF TFallF TRiseS TFallS
GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload
Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Document Number: 001-12981 Rev.
Page
CY8CLED08
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table Operational Amplifier Specifications
Symbol Description Units Notes
TROA
Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High 0.72 0.62
TSOA
Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High 0.15 0.01 0.75 0.92 0.72
SRROA
Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High nV/rt-Hz
SRFOA
Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High
BWOA
Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High
ENOA
Noise (Power Medium, Opamp Bias High)
Document Number: 001-12981 Rev.
Page
CY8CLED08
Table 3.3V Operational Amplifier Specifications
Symbol Description Units Notes
TROA
Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Low, Opamp Bias High 3.92 0.72
TSOA
Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High 0.31 0.24 0.67 5.41 0.72
SRROA
Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High nV/rt-Hz
SRFOA
Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High
BWOA
Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High
ENOA
Noise (Power Medium, Opamp Bias High)
When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
Document Number: 001-12981 Rev.
Page
CY8CLED08
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level. Figure Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications
Symbol Description Units Notes overdrive comparator reference within VREFLPC.
TRLPC
response time
Document Number: 001-12981 Rev.
Page
CY8CLED08
Digital Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Digital Block Specifications
Function Description Units Notes
Functions Timer
Maximum Block Clocking Frequency 4.75V) Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture
49.2 24.6 49.2 24.6 49.2 24.6
4.75V 5.25V. 3.0V 4.75V.
4.75V 5.25V.
Counter
Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input
4.75V 5.25V.
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency
49.2 49.2 24.6 24.6 49.2 24.6 49.2
Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate over clocking. 4.75V 5.25V. 4.75V 5.25V.
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits
minimum input pulse width based input synchronizers running nominal period).
Document Number: 001-12981 Rev.
Page
CY8CLED08
Analog Output Buffer Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications
Symbol Description Units Notes
TROB
Rising Settling Time 0.1%, Step, 100pF Load Power Power High 0.65 0.65 0.65 0.65
TSOB
Falling Settling Time 0.1%, Step, 100pF Load Power Power High
SRROB
Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High
SRFOB
Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High
BWOB
Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High
BWOB
Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High
Table 3.3V Analog Output Buffer Specifications
Symbol Description Units Notes
TROB
Rising Settling Time 0.1%, Step, 100pF Load Power Power High
TSOB
Falling Settling Time 0.1%, Step, 100pF Load Power Power High
SRROB
Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High
SRFOB
Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High
BWOB
Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High
BWOB
Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High
Document Number: 001-12981 Rev.
Page
CY8CLED08
External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table External Clock Specifications
Symbol Description Units Notes
FOSCEXT
Frequency High Period Period Power Switch
0.093 20.6 20.6
24.6 5300
Table 3.3V External Clock Specifications
Symbol Description Units Notes
FOSCEXT FOSCEXT
Frequency with Clock divide Frequency with Clock divide greaterb High Period with Clock divide Period with Clock divide Power Switch
0.093 0.186 41.7 41.7
12.3 24.6 5300
Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider will ensure that fifty percent duty cycle requirement met.
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications
Symbol Description Units Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3
Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK
Document Number: 001-12981 Rev.
Page
CY8CLED08
Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Characteristics Pins
Standard Mode Symbol Description Fast Mode Units Notes
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Set-up Time Repeated START Condition Data Hold Time Data Set-up Time Set-up Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
100a
Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Document Number: 001-12981 Rev.
Page
CY8CLED08
Packaging Information
This section illustrates packaging specifications CY8CLED08 EZ-Color device, along with thermal impedances each package typical package capacitance crystal pins. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 48-Lead (300-Mil) SSOP
Document Number: 001-12981 Rev.
Page
CY8CLED08
Figure 48-Lead (7x7
001-12919
Important Note information preferred dimensions mounting packages, following Application Note Important Note Pinned vias thermal conduction required low-power PSoC device.
Document Number: 001-12981 Rev.
Page
CY8CLED08
Thermal Impedances
Table Thermal Impedances Package
Package Typical
Development Tool Selection
This section presents development tools available current PSoC device families including CY8CLED08 EZ-Color family.
SSOP QFN** POWER
oC/W oC/W
Software Tools
PSoC ExpressAs newest addition PSoC development software suite, PSoC Express first visual embedded system design tool that allows user create entire PSoC project generate schematic, BOM, data sheet without writing single line code. Users work directly with application objects such LEDs, switches, sensors, fans. PSoC Express available free charge PSoC DesignerUtilized thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under DESIGN RESOURCES Software Drivers. PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge CY3202-C iMAGEcraft Compiler CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items.
achieve thermal impedance specified package, center thermal should soldered ground plane.
Capacitance Crystal Pins
Table Typical Package Capacitance Crystal Pins
Package Package Capacitance
SSOP
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature
Package Minimum Peak Temperature* Maximum Peak Temperature
SSOP
220oC 240oC
260oC 260oC
*Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
Hardware Tools
In-Circuit Emulator cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal will operate with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation. Bridge Bridge quick easy link from design application's design testing, debugging communication. Document Number: 001-12981 Rev. Page
CY8CLED08
PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge CY3202-C iMAGEcraft Compiler CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items.
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Device Programmers Evaluation Tools
evaluation tools purchased from Cypress Online Store. CY3261A-RGB EZ-Color CY3261A-RGB board preprogrammed color board with seven pre-set colors using CY8CLED16 EZ-Color Controller. board accompanied containing color selector software application, PSoC Express Beta PSoC Programmer, suite documents, schematics, firmware examples. color selector software application installed host used control EZ-Color controller using included cable. application enables select colors 1931 chart entering coordinates. includes:
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
Training Board (CY8CLED16) mini-A mini-B Cable PSoC Express CD-ROM Design Files Application Installation CD-ROM
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. includes:
program tune this PSoC Express must Mini Programmer Unit (CY3217 Kit) CY3240-I2CUSB kit. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Document Number: 001-12981 Rev.
Page
CY8CLED08
Accessories (Emulation Programming)
Table Emulation Programming Accessories
Part Package Flex-Pod Kita Foot Kitb Adapterc
Third Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards.
CY8CLED08-48PVXI CY8CLED08-48LFXI
SSOP CY3250-27XXX CY3250-27XXX
CY3250-48 Adapters SSOP-FK found CY3250-48 http://www.e QFN-FK mulation.com.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com/an2323. following table lists CY8CLED08 EZ-Color devices' package features ordering codes.
Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
Ordering Information
Device Table Device Features Ordering Information
Analog Blocks Digital Blocks (Rows
(Columns
Switch Mode Pump
Temperature Range
Package
Ordering Code
(300 Mil) SSOP (300 Mil) SSOP (Tape Reel) (7x7) (7x7) (Tape Reel)
CY8CLED08-48PVXI
-40C +85C -40C +85C -40C +85C -40C +85C
CY8CLED08-48PVXIT CY8CLED08-48LFXI CY8CLED08-48LFXIT
Ordering Code Definitions
xxxx Package Type: Thermal Rating: PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended LFX/LKX Pb-Free TQFP Pb-Free Count Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
Document Number: 001-12981 Rev.
Page
XRES
Digital Pins
Analog Outputs
Flash (Bytes)
Analog Inputs
(Bytes)
CY8CLED08
Document History
Table CY8CLED08 Data Sheet Revision History
Document Title:
CY8CLED08 EZ-Color Controller
Description Change
Document Number: 001-12981 Revision Issue Date Origin Change document (revision **). 1148504 SFVTMP3 Distribution: External Public Posting: None
Cypress Semiconductor Corporation, 2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 001-12981 Rev.
Page

EZ-ColorHB Controller Controller Configurable Dimmers Support Ind

Top Searches for this datasheet

Other recent searches