Designed space savings with low-power Programmable PLLs clock outputs.

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Designed space savings with low-power Programmable PLLs clock outputs.

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1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
Designed space savings with low-power Programmable PLLs clock outputs. Low-power consumption (<10µA when activated) Output frequency: <133MHz 1.8V operation <166MHz 2.5V operation <200MHz 3.3V operation Input frequency: Fundamental Crystal: 10MHz 50MHz Reference Input: 1MHz 200MHz Programmable pins configured Output Enable (OE), Configuration Switching (CSEL), Power Down (PDB) input, Clock outputs. Single 1.8V 3.3V, power supply Operating temperature range from -40C Available GREEN/RoHS compliant SOP-8L MSOP-10L packages.
DESCRIPTION
PL612-05 advanced dual design based PhaseLink's PicoPLL world's smallest programmable clock, technology. This flexible programmable architecture ideal high performance, low-power, low-cost applications. When using power down (PDB) feature PL612-05 consumes less than power, while Configuration Select (CSEL) function allows switching programmable configurations. Besides small form factor outputs that reduce overall system costs, PL612-05 offers superior phase noise, jitter power consumption performance.
CONFIGURATION
CLK4, CSEL^ CLK2, OEM^, PDB^ CLK3 PL612-05 XIN, XOUT CLK1 CLK0
XIN, CLK2, OEM^, PDB^ CLK0
PL612-05
XOUT CLK1
MSOP-10L
Denotes internal pull
SOP-8L
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
PACKAGE ASSIGNMENT
Name XIN, CLK4, CSEL CLK2, OEM, CLK3 CLK0 CLK1 XOUT Package Type MSOP-10L SOP-8L Description Crystal Reference Clock input Programmable Clock (CLK4) output Configuration Switching input Programmable Clock (CLK2) output, Output Enable Master (OEM) clock outputs, Power Down mode (PDB) input connection Programmable Clock (CLK3) output Programmable Clock (CLK0) output connection Programmable Clock (CLK1) output Crystal output pin. Connect when using
Note: bidirectional buffers (I/Os) incorporate internal pull resistor except when mode used. configurations that PDB, will have pull resistor.
PROGRAMMING PARAMETERS
CLK[ Output Frequency CLK[0] VCO2 CLK[1] VCO1 (P*(1,2,4,8)) (P*(1,2,4,8)) CLK[2] (P*(1,2,4,8)) CLK[3] VCO2 (P*(1,2,4,8)) (P*(1,2,4,8)) CLK[4] Where (Odd/Even Divider) Output Drive Strength Each output three optional drive strengths choose from. They are: Low: Std: (default) High:16mA Programmable Input/Output Most pins multi-function I/Os configured (Master controlling outputs) CSEL (Device Configuration Switching) (Power Down) CLK[0:4] (Output) Active disabled state
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
FUNCTIONAL DESCRIPTION
PL612-05 highly featured, very flexible, advanced Dual design high performance, low-power applications. Starting from low-cost fundamental input crystal 10MHz 50MHz reference clock input 1MHz 200MHz, PL612 capable producing (SOP-8L) (MSOP-10L) distinct output frequencies 200MHz. Both PLLs fully programmable, with total three Odd/Even (patent pending) `5-bit' Post (P-counter) dividers with additional `Post P-counter' dividers allow generating most demanding frequencies easily. outputs programmed deliver generated frequencies from PLLs, reference input. Each bidirectional feature (I/O) PL613-05 incorporates pull resistor (10M function) configured perform various functions. Usage various design features these products mentioned following paragraphs. Programming PLLs PL612-05 fully programmable. Each equipped with 8-bit input frequency divider (R-Counter) 11-bit frequency feedback loop (M-Counter) divider. outputs transferred Odd/Even (patent pending) 5-bit post dividers (P-Counter), shown above diagrams. addition, there three optional (÷1, `post P-Counter' dividers that further divide frequency. general, output frequency determined following formula (R*P). output calculations, please note that includes counter bits plus additional optional (÷1, dividers, used. CLKx (Clock Outputs) There maximum (SOP-8L) (MSOP10L) outputs available PL612-05. Clock output frequencies configured follows: CLK[0] VCO2 CLK[1] VCO1 (P*(1,2,4,8)) (P*(1,2,4,8)) CLK[2] (P*(1,2,4,8)) CLK[3] VCO2 (P*(1,2,4,8)) (P*(1,2,4,8)) CLK[4] Each output programmed with 4mA, 8mA, 16mA drive strength. maximum output frequency 200MHz 3.3V, 166MHz 2.5V 133MHz 1.8V.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
(Master Output Enable) configured single Master (OEM) input that controls outputs PL612-05. addition state disabled outputs programmed float operate `Active low' mode. Function operates following logic: Type Output (Programmable) (Default) Active
Normal Operation (Default)
Note: Typical enable time 10ns.
Power-Down Control (PDB) When activated, `Disables PLLs, oscillator circuitry, counters, other active circuitry. activation disables outputs consumes <10µA power. input incorporates pull resistor normal operating condition. feature programmed allow output float operate `Active low' mode. logic shown below: Type Output Program (Default) Active Normal Operation (Default)
Note: Typical enable time 2ms.
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
On-The-Fly Configuration Switching (CSEL) PL612-05 programmed allow switching between different configurations, allowing changes output frequency other feature changes. Many applications (i.e. video/audio) same design footprint, allow configuration switching, adhering various standards. CSEL used make switching selection. This incorporates pull resistor normal operating condition. logic configuration switching programmed parts shown below: CSEL Programmed Configuration 1(Default)
Note: Typical enable time 100µs
LAYOUT RECOMMENDATIONS
following guidelines assist with performance optimized design:
Signal Integrity Termination Considerations
Keep traces short! Trace Inductor. With capacitive load this equals ringing! Long trace Transmission Line. Without proper termination this will cause reflections looks like ringing Design long traces inch) "striplines" "microstrips" with defined impedance. Match trace side avoid reflections bouncing back forth.
Decoupling Power Supply Considerations
Place decoupling capacitors close possible pin(s) limit noise from power supply Multiple pins should decoupled separately best performance. Addition ferrite bead series with help prevent noise from other board sources Value decoupling capacitor frequency dependant. Typical values 0.1F designs using frequencies 50MHz 0.01F designs using frequencies 50MHz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention Storage Temperature Ambient Operating Temperature* SYMBOL MIN. -0.5 -0.5 -0.5 MAX. +0.5 +0.5 UNITS Year
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. *Operating temperature guaranteed design. Parts tested commercial grade only.
SPECIFICATIONS
PARAMETERS Crystal Input Frequency (XIN) Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude =3.3V =2.5V =1.8V Internally coupled (High Frequency) Internally coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz =3.3V Output Frequency Settling Time Output Enable Time Sensitivity Output Rise Time Output Fall Time Duty Cycle Period Jitter, Pk-to-Pk* (10,000 samples) =2.5V =1.8V power-up (after increases over 1.62V) Function; 15pF Load Function; 15pF Load Frequency +/-10% 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V Enabled, Input 16MHz fundamental mode crystal, outputs 40MHz, 10pF Load, with capacitive decoupling between GND. CONDITIONS Fundamental Crystal MIN. TYP. MAX. UNITS
Note: Jitter performance depends programming parameters.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
SPECIFICATIONS
PARAMETERS Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Voltage Output High Voltage Output Current, Drive Output Current, Drive Output Current, High Drive SYMBOL CONDITIONS outputs 20MHz, 10pF Load, 3.3V outputs 20MHz, 10pF Load, 2.5V outputs 20MHz, 10pF Load, 1.8V When PDB=0 3.3V Operation 2.5V Operation 1.8V Operation +4mA Std. Drive -4mA Std. Drive 0.4V, 2.4V 0.4V, 2.4V 0.4V, 2.4V 2.97 2.25 1.62 MIN. TYP. MAX. 3.63 2.75 1.98 UNITS
CRYSTAL SPECIFICATIONS
PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating Maximum Sustainable Drive Level Operating Drive Level Crystal Shunt Capacitance Metal Crystal Small Crystal Shunt Capacitance Shunt Capacitance SYMBOL (xtal) MIN. TYP. MAX. UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP-10L Dimension Min. Max. 0.86 1.06 0.05 0.15 0.81 0.91 0.17 0.25 3.00 3.00 -5.08 0.43 0.63 0.50
Symbol
SOP-8L Symbol Dimension Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, Output Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER order number this device combination following: Part number, Package type Operating temperature range
PL612-05-XXX
PART NUMBER DIGIT Code (will assigned programming time) PACKAGE TYPE M=MSOP-10L S=SOP-8L NONE= TUBE R=TAPE REEL TEMPERATURE C=COMMERCIAL 70C) INDUSTRIAL (-40C +85C)
PhaseLink will assign unique 3-digit code each approved programmed part number.
Part Number/Order Number PL612-05-XXXMC PL612-05-XXXMC-R PL612-05-XXXSC PL612-05-XXXSC-R
Marking K2XXX K2XXX P612-05 P612-05
Package Option 10-Pin MSOP (Tube) 10-Pin MSOP (Tape Reel) 8-Pin (Tube) 8-Pin (Tape Reel)
Note: `XXX' designates marking identifier that, times, could independent part number. Please consult your PhaseLink sales representative marking information.
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
Solder reflow profile available
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 9/4/07 Page

Designed space savings with low-power Programmable PLLs clock outputs.

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