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Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A Sum


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Instruction Extensions, Jazelle® Technology Java® Acceleration Kbyte Data Cache, Kbyte Instruction Cache, Write Buffer MIPS Memory Management Unit EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories Kbyte Internal ROM, Single-cycle Access Maximum Matrix Speed Kbyte Internal SRAM, Single-cycle Access Maximum Matrix Speed External Interface (EBI) Supports Mobile DDR, SDRAM, Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash CompactFlashMetal Programmable (MP) Block 500,000 Gates/250,000 Gates Metal Programmable Logic (through Metal Layers) AT91CAP9S500A/AT91CAP9S250A Respectively 36-bit Dual Port RAMs Eight 72-bit Single Port RAMs High Connectivity Three Masters Four Slaves Seven Interrupt Inputs Four Hardware Handshake Interfaces Delay Lines Double Data Rate Interface UTMI+ Full Connection Dedicated I/Os Controller Supports Passive Active Displays Bits Pixel Mode, Bits Pixel Color Mode Colors Mode, Resolution 2048x2048, Supports Wider Screen Buffers Image Sensor Interface ITU-R 601/656 External Interface, Programmable Frame Capture Rate 12-bit Data Interface Support High Sensibility Sensors Synchronization, Preview Path with Scaler, YCbCr Format Full Speed Mbits second) OHCI Host Double Port Dual On-chip Transceivers Integrated FIFOs Dedicated Channels High Speed (480 Mbits second) Device Port On-chip Transceiver, Kbyte Configurable Integrated DPRAM Integrated FIFOs Dedicated Channels Integrated UTMI+ Physical Interface Ethernet 10/100 Base Media Independent Interface (MII) Reduced Media Independent Interface (RMII) 28-byte FIFOs Dedicated Channels Receive Transmit Multi-Layer Matrix Twelve 32-bit-layer Matrix, Allowing Maximum 38.4 Gbps On-chip Bandwidth Maximum System Clock Speed Boot Mode Select Option, Remap Command Fully-featured System Controller, Including Reset Controller, Shutdown Controller
Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A Summary Preliminary
NOTE: This summary document. complete document available Atmel website www.atmel.com.
6264BS-CAP-26-Nov-07
Four 32-bit Battery Backup Registers Total Bytes Clock Generator Power Management Controller Advanced Interrupt Controller Debug Unit Periodic Interval Timer, Watchdog Timer Real-Time Timer Reset Controller (RSTC) Based Power-on Reset Cells, Reset Source Identification Reset Output Control Shutdown Controller (SHDC) Programmable Shutdown Control Wake-up Circuitry Clock Generator (CKGR) 32,768 Low-power Oscillator Battery Backup Power Supply, Providing Permanent Slow Clock On-chip Oscillator PLLs Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART Support Debug Communication Channel, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) Key-protected, Programmable Only Once, Windowed 16-bit Counter Running Slow Clock Real-Time Timer (RTT) 32-bit Free-running Backup Counter Running Slow Clock with 16-bit Prescaler Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC PIOD) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Controller (DMAC) Acts Matrix Master Embeds Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering Control Supports Four External Requests Four Internal Requests from Metal Programmable Block (MPBlock) Twenty-two Peripheral Controller Channels (PDC) 2.0A 2.0B Compliant Controller Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Multimedia Card Interfaces (MCI) SDCard/SDIO MultiMediaCard 3.31 Compliant Automatic Protocol Control Fast Automatic Data Transfers with Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
AC97 Controller (AC97C)
6-channel Single AC97 Analog Front Interface, Slot Assigner
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Synchronous Communications Mbits/sec Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Controller (PWMC) Two-wire Interface (TWI) Master Slave Mode Support, Two-wire Atmel EEPROMs Supported 8-channel, 10-bit Analog-to-Digital Converter (ADC) Eight Channels Multiplexed with Digital I/Os IEEE® 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies: 1.08V 1.32V VDDCORE VDDBU, VDDUPLL VDDUTMIC 3.0V 3.6V VDDOSC, VDDPLL VDDIOP0 (Peripheral I/Os) VDDANA (ADC) Programmable 1.65V 1.95V 3.0V 3.6V VDDIOP1 (Peripheral I/Os), VDDIOM (Memory I/Os) VDDMPIOA/VDDMPIOB Block I/Os) Available 400-ball LFBGA RoHS-compliant Package also Delivered 324-ball TFBGA RoHS-compliant Package According User Needs
Description
AT91CAP9S500A/AT91CAP9S250A family based integration ARM926EJ-S processor with fast SRAM memories, wide range peripherals. providing 500K gates metal programmable logic, AT91CAP9S500A/AT91CAP9S250A ideal platform creating custom designs. AT91CAP9S500A/AT91CAP9S250A embeds High-speed Device, 2-port OHCI Host, Controller, 4-channel Controller, Image Sensor Interface. also integrates several standard peripherals, such USART, SPI, TWI, Timer Counters, generators, Multimedia Card interface, Controller. AT91CAP9S500A/AT91CAP9S250A architectured 12-layer matrix, allowing maximum internal bandwidth twelve 32-bit buses. also features external memory (EBI) capable interfacing with wide range memory devices. AT91CAP9S500A/AT91CAP9S250A packaged 400-ball LFBGA RoHS-compliant package. also delivered 324-ball TFBGA RoHS-compliant package according customer's requirements.
6264BS-CAP-26-Nov-07
Figure 2-1.
UTMI+ Transc.
Transc. Transc.
HSLR HSDP FSDP HDPA _VSYN CKNC LCDD LCDV LCDH DOYN LCDD DCEN ECXE ERRS EMX0 EMDCETX
System Controller JTAG Boundary Scan Controller 10/100 Ethernet High-Speed Device OHCI In-Circuit Emulator
AT91CAP9S500A/AT91CAP9S250A Block Diagram
RTS0 S0-CT TXX0 -SCS2 D0-RDK2 NPCS NPCS3 NPCS2 IOA0- TIOK2 97CK AC97 TF0-T RF0-RD1 0-RD1 VDVR
MCI0_, MCI1_
SPI0_, SPI1_
CompactFlash NAND Flash
MASTER
SLAVE
IRQ0-IRQ1
DBGU FIFO FIFO FIFO
ICache bytes Interface DCache bytes
ARM926EJ-S Processor
DRXD DTXD PCK0-PCK3 FIFO
Image Sensor Interface
DDRSDR Controller
PLLRCA
PLLA
PLLRCB
PLLB
XOUT 12-layer Matrix
Burst Cellular Memory Controller
GPREG
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A22 A16/BA0 A17/BA1 NCS0 NCS1/BCCS NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKN DQS0, DQS1 SDCKE/BCCRE RAS/BCADV, CAS/BCOE SDWE/BCWE, SDA10 NANDOE, NANDWE BCOWAIT
XIN32 XOUT32 PIOA PIOB PIOC PIOD 32Kbytes Peripheral Bridge SRAM 32Kbytes 4-channel
SHDN WKUP 24-channel Peripheral
SHDC
Static Memory Controller
AT91CAP9S500A/AT91CAP9S250A Block Diagram
VDDBU
RSTC
VDDCORE
NWAIT A23-A24 NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 D16-D31
NRST 512x36 SPI0 SPI1 PWMC AC97C SSC0 SSC1 USART0 USART1 USART2 8-channel 10-bit Metal Programable Block 500K Gates (CAP9500) 250K Gates (CAP9250) 512x72
AT91CAP9S500A/AT91CAP9S250A
MCI0 MCI1
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Signal Description
Table gives details signal name classified peripheral. Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM VDDIOP0 VDDIOP1 VDDIOMPA VDDIOMPB VDDBU VDDPLL VDDUTMII VDDUTMIC VDDUPLL VDDANA VDDCORE GNDPLL GNDUTMII GNDUTMIC GNDUPLL GNDANA GNDBU GNDTHERMAL
Lines Power Supply Peripherals Lines Power Supply Peripherals Lines Power Supply Block Lines Power Supply Block Lines Power Supply Backup Lines Power Supply Power Supply UTMI+ Interface Power Supply UTMI+ Core Power Supply UTMI+ Power Supply Analog Power Supply Core Chip Power Supply Ground Ground UTMI+ Interface Ground UTMI+ Core Ground UTMI+ Ground Analog Ground Backup Ground Thermal Ground Ball
Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground
1.65V 3.6V 3.0V 3.6V 1.65V 3.6V 1.65V 3.6V 1.65V 3.6V 1.08V 1.32V 3.0V 3.6V 3.0V 3.6V 1.08V 1.32V 1.08V 1.32V 3.0V 3.6V 1.08V 1.32V
Thermally coupled with package substrate
Clocks, Oscillators PLLs XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Filter Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input over VDDBU Accept between VDDBU
6264BS-CAP-26-Nov-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function JTAG Type Active Level Comments
NTRST JTAGSEL RTCK
Test Reset Signal Test Clock Test Data Test Data Test Mode Select JTAG Selection Return Test Clock Reset/Test
Input Input Input Output Input Input Output
pull-up resistor pull-up resistor pull-up resistor
pull-up resistor Pull-down resistor
NRST
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit DBGU
Input Input
Pull-up resistor Pull-down resistor Pull-up resistor
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input Input Input
Controller PIOA PIOB PIOC PIOD PA31 PB31 PC31 PD31 Parallel Controller Parallel Controller Parallel Controller Parallel Controller Pulled-up input reset Pulled-up input reset Pulled-up input reset Pulled-up input reset
Direct Memory Access Controller DMARQ0-DMARQ3 Requests Input External Interface NWAIT Data Address External Wait Signal Output Input Pulled-up input reset reset
Static Memory Controller NCS0 NCS5 NWR0 NWR3 NBS0 NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Table 3-1.
Signal Name
Signal Description List (Continued)
Function CompactFlash Support Type Active Level Comments
CFCE1 CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 CFCS1
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Lines NAND Flash Support
Output Output Output Output Output Output Output
NANDCS NANDOE NANDWE
NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable DDR/SDRAM Controller
Output Output Output
SDCK SDCKN DQS0 DQS1 SDCKE SDCS SDWE SDA10
DDR/SDRAM Clock Inverted Clock Data Qualifier Strobe Data Qualifier Strobe SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Column Signal SDRAM Address Line
Output Output Output Output Output Output Output Output High
Burst CellularRAM Controller BCCK BCCRE BCADV BCWE BCOE BCOWAIT Burst CellularRAM Clock Burst CellularRAM Enable Burst CellularRAM Burst Advance Signal Burst CellularRAM Write Enable Burst CellularRAM Output Enable Burst CellularRAM Output Wait Output Output Output Output Output Input
Multimedia Card Interface MCIx_CK MCIx_CD MCIx_D0 Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output
6264BS-CAP-26-Nov-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Comments
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request Send USARTx Clear Send Input Output Input
Synchronous Serial Controller SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter TCLKx TIOAx TIOBx Channel External Clock Input Channel Line Channel Line Input Input Output Output Input Output Input
Pulse Width Modulation Controller- PWMC PMWx Pulse Width Modulation Output Output
Serial Peripheral Interface SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 SPIx_NPCS3 Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select Two-Wire Interface TWCK Two-wire Serial Data Two-wire Serial Clock Output
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Controller Type Active Level Comments
CANRX CANTX
input output Controller LCDC
Input Output
LCDD0 LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC
Data Vertical Synchronization Horizontal Synchronization Clock Data Enable Contrast Control Ethernet 10/100
Input Output Output Output Output Output
ETXCK/EREFCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Transmit Clock Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. High Speed Device
Input Input Output Output Output Input Input Input Input Input Output Output High
only, REFCK RMII only
ETX0-ETX1 only RMII only RXDV MII, CRSDV RMII ERX0-ERX1 only RMII
only only
RMII only
FSDM FSDP HSDM HSDP PLLRCU
Full Speed Data Full Speed Data High Speed Data High Speed Data Bias Voltage Reference Test
Analog Analog Analog Analog Analog Analog
6264BS-CAP-26-Nov-07
Table 3-1.
Signal Name
Signal Description List (Continued)
Function OHCI Host Port Type Active Level Comments
HDPA HDMA HDPB HDMB
Host Port Data Host Port Data Host Port Data Host Port Data
Analog Analog Analog Analog
AD0-AD7 ADVREF ADTRIG
Analog Inputs Voltage Reference Trigger
Analog Analog Input Image Sensor Interface
ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK
Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock MPBLOCK
Input Output Input Input Input
MPIOA0-MPIOA31 MPIOB0-MPIOB44
MPBlock I/Os MPBlock I/Os
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Package Pinout
AT91CAP9S500A/AT91CAP9S250A available packages: 400-ball RoHS-compliant LFBGA package, ball pitch 324-ball RoHS-compliant TFBGA package, ball pitch
400-ball LFBGA Package Outline
Figure shows orientation 400-ball Package. detailed mechanical description given section "AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics" product datasheet. Figure 4-1. 400-ball LFBGA Package Outline Marking (Top View)
View
CAP9
Corner
Corner
6264BS-CAP-26-Nov-07
400-ball LFBGA Package Pinout
AT91CAP9S500A/AT91CAP9S250A Pinout 400-ball Package
Signal Name VDDIOM VDDIOP0 PC24 VDDCORE GNDIO PB23 GNDPLL WKUP0 SHDW PLLRCA PA10 PA11 PA12 PD10 GNDIO GNDCORE VDDIOP0 PB25 PB21 VDDPLL Signal Name PA22 PA25 PA29 PA31 GNDIO GNDCORE PA18 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE GNDIO VDDCORE MPIOB28 MPIOB32 MPIOB34 MPIOB31 MPIOB29 PA26 PA30 PD11 PD12 PD13 PD15 GNDCORE PA28 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL MPIOB26 GNDIO MPIOB16 GNDCORE Signal Name PD22 PD23 PD30 VDDCORE SDDRCS DQS0 SDA10 VDDCORE MPIOA0 MPIOA9 GNDIO MPIOA25 MPIOA24 MPIOA29 MPIOB3 MPIOB17 MPIOB18 PD25 PD31 BCCLK NWR1 DQS1 GNDIO MPIOA4 MPIOA11 MPIOA16 VDDMPIOA MPIOA23
Table 4-1.
NRST
Signal Name
GNDCORE PB18 PB17 PB14 PB15 GNDANA PB26 VDDIOP0 GNDIO FSDP FSDM HSDP HSDM PC17 PC16 PC14 PC11 PC10 PB20 PB19 PB13 ADVREF PB16 PB27 PB24 HDMA VDDIOP0
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Table 4-1.
GNDIO VDDUTMII GNDUTMII PC23 PC22 PC21 PC20 PC18 PC15 PC12 NTRST VDDANA PB12 PB29 HDPA HDPB VDDUPLL VDDUTMIC PC29 PC28 PC27 PC26 PC25 PC19 NANDOE GNDIO PB31 PB22 VDDCORE
AT91CAP9S500A/AT91CAP9S250A Pinout 400-ball Package (Continued)
Signal Name GNDCORE PLLRCB PA13 PA14 PA15 VDDIOP1 VDDCORE GNDIO GNDIO PB10 VDDMPIOB JTAGSEL GNDCORE GNDPLL VDDCORE MPIOB44 XOUT32 XIN32 PA17 PA19 VDDIOP0 PA16 GNDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDIO GNDBU GNDBU Signal Name MPIOB27 MPIOB25 MPIOB24 PD16 PD19 PD20 PD29 GNDIO VDDIOM NCS1 VDDCORE VDDCORE MPIOB11 MPIOB13 MPIOB12 MPIOB14 MPIOB15 MPIOB22 MPIOB23 PD14 PD18 PD27 PD28 VDDIOM NWR3 GNDIO MPIOB8 MPIOB0 Signal Name MPIOA28 MPIOB6 MPIOB9 PD26 SDCKE VDDIOM GNDCORE MPIOA1 MPIOA6 MPIOA10 MPIOA13 MPIOA17 MPIOA20 MPIOA27 MPIOB5 VDDMPIOB SDWE BCOWAIT NANDWE GNDIO NWR0 MPIOA2 MPIOA5 MPIOA8 MPIOA12
Signal Name
6264BS-CAP-26-Nov-07
Table 4-1.
HDMB
AT91CAP9S500A/AT91CAP9S250A Pinout 400-ball Package (Continued)
Signal Name MPIOB42 MPIOB39 MPIOB43 MPIOB41 GNDIO PA21 PA24 PA27 PA23 GNDIO PA20 VDDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE MPIOB33 MPIOB30 MPIOB35 MPIOB38 MPIOB40 MPIOB37 MPIOB36 Signal Name MPIOB1 MPIOB7 MPIOB10 MPIOB21 VDDMPIOB PD21 PD17 PD24 VDDCORE VDDIOM VDDIOM VDDIOM MPIOB2 MPIOB4 MPIOB19 MPIOB20 Signal Name MPIOA15 MPIOA21 MPIOA22 GNDIO VDDCORE SDCK SDCKN GNDCORE NCS0 MPIOA3 MPIOA7 VDDMPIOA MPIOA14 MPIOA18 MPIOA19 MPIOA26 MPIOA30 MPIOA31
Signal Name
PLLRCU GNDUTMIC GNDUPLL PC30 PC31 GNDIO VDDCORE PC13 RTCK VDDIOP0 PB30 PB28 PB11 VDDPLL VDDBU XOUT
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
324-ball TFBGA Package Outline
Figure shows orientation 324-ball TFBGA green package. detailed mechanical description given section "AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics" product datasheet. Figure 4-2. 324-ball TFBGA Package Outline Marking (Top View)
View
Corner Corner
CAP9
324-ball TFBGA Package Pinout
assignment 324-ball TFBGA package customizable dependent upon needs user. Important: possible partially totally remove connections dedicated Metal Programmable I/0s: MPIOAO-MPIOA31 MPIOB0-MPIOB44. Likewise, PA16-PA31, PB21PB31, PDC0-PC27, PD-12-PD31 partially totally disconnected. However, incumbent upon user ensure that associated functionality removed needed intended application. Refer Section 10.3.1 page Section 10.3.2 page Section 10.3.3 page Section 10.3.4 page information multiplexing verify functionality before disconnecting signals.
6264BS-CAP-26-Nov-07
Power Considerations
Power Supplies
AT91CAP9S500A/AT91CAP9S250A several types power supply pins: VDDCORE pins: Power core, including processor, embedded memories peripherals; voltage range between1.08V 1.32V, 1.2V nominal. VDDIOM pins: Power External Interface; voltage ranges between 1.65V 1.95V (1.8V nominal) between 3.0V 3.6V (3.3V nominal). VDDIOP0 pins: Power Peripherals lines transceivers; voltage range between 3.0V 3.6V, 3.3V nominal. VDDIOP1 pins: Power Peripherals lines involving Image Sensor Interface; voltage ranges from 1.65V 3.6V, 1.8V, 2.5V, 3.3V nominal. VDDIOMPA pins: Power Block lines; voltage ranges from 1.65V 3.6V, 1.8V, 2.5V, 3.3V nominal. VDDIOMPB pins: Power dedicated Block lines; voltage ranges from 1.65V 3.6V, 1.8V, 2.5V, 3.3V nominal. VDDBU pin: Powers Slow Clock oscillator part System Controller; voltage range between1.08V 1.32V, 1.2V nominal. VDDPLL pin: Powers cells; voltage ranges between 3.0V 3.6V, 3.3V nominal. VDDUTMII pin: Powers UTMI+ interface; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDUTMIC pin: Powers UTMI+ core; voltage ranges between 1.08V 1.32V, 1.2V nominal. VDDUPLL pin: Powers cell; voltage ranges between 1.08V 1.32V, 1.2V nominal. VDDANA pin: Powers cell; voltage ranges between 3.0V 3.6V, 3.3V nominal. power supplies VDDIOM, VDDIOP0 VDDIOP1 identified pinout table multiplexing tables. These supplies enable user power device differently interfacing with memories interfacing with peripherals. Ground pins GNDIO common VDDIOM, VDDIOP0, VDDIOP1, VDDIOMPA VDDIOMPB power supplies. Separated ground pins provided VDDCORE, VDDBU, VDDPLL, VDDUTMII, VDDUTMIC, VDDUPLL VDDANA. These ground pins are, respectively, GNDBU, GNDOSC, GNDPLL, GNDUTMII, GNDUTMIC, GNDUPLL GNDANA. Special GNDTHERMAL ground balls thermally coupled with package substrate.
Power Consumption
AT91CAP9S500A/AT91CAP9S250A consumes about (TBC) static current VDDCORE 25°C. This static current (TBC) temperature increases 85°C. VDDBU, current does exceed (TBC) @25°C, rise (TBC) @85°C. dynamic power consumption, AT91CAP9S500A/AT91CAP9S250A consumes maximum (TBC) VDDCORE typical conditions (1.2V, 25°C, processor running fullperformance algorithm).
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Programmable Lines Power Supplies
power supply pins VDDIOM, VDDMPIOA VDDMPIOB accept voltage ranges. This allows device reach maximum speed either 1.8V 3.3V external memories. target maximum speed DDR/SDR MPIOA MPIOB pins loaded with power supply 1.8V power supply 3.3V. other signals (control, address data signals) over MHz. voltage ranges determined programming registers Chip Configuration registers located Matrix User Interface. reset, selected voltage defaults 3.3V nominal power supply pins accept either 1.8V 3.3V. Obviously, device cannot reach maximum speed voltage supplied pins 1.8V only. user must make sure program voltage range before getting device Slow Clock Mode.
6264BS-CAP-26-Nov-07
Line Considerations
JTAG Port Pins
TMS, Schmitt trigger inputs have pull-up resistors. RTCK outputs, driven VDDIOP0, have pull-up resistors. JTAGSEL used select JTAG boundary scan when asserted high level. integrates permanent pull-down resistor about GNDBU that left unconnected normal operations. NTRST signal described Section "Reset Pins" page JTAG signals supplied with VDDIOP0.
Test
used manufacturing test purposes when asserted high. integrates permanent pull-down resistor about GNDBU that left unconnected normal operations. Driving this line high level leads unpredictable results. This supplied with VDDBU.
Reset Pins
NRST open-drain output integrating non-programmable pull-up resistor. driven with voltage VDDIOP0. NTRST input which allows reset JTAG Test Access port. action processor. product integrates power-on reset cells that manage processor JTAG reset, NRST NTRST pins left unconnected. NRST NTRST pins both integrate permanent pull-up resistor minimum VDDIOP0. NRST signal inserted Boundary Scan.
Controllers
lines which managed Controllers integrate programmable pull-up resistor minimum. Programming this pull-up resistor performed independently each line through Controllers. After reset, lines default inputs with pull-up resistors enabled, except those multiplexed with External Interface signals that must enabled Peripheral reset. This indicated column "Reset State" Controller multiplexing tables.
Shutdown Logic Pins
SHDN output only, which driven Shutdown Controller only level. tied high with external pull-up resistor VDDBU only. WKUP input-only. accept voltages only between VDDBU.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Processor Architecture
ARM926EJ-S Processor
RISC Processor based v5TEJ Architecture with Jazelle technology Java acceleration Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction Instruction Extensions 5-Stage Pipeline Architecture: Instruction Fetch Instruction Decode Execute Data Memory Register Write 16-Kbyte Data Cache, 16-Kbyte Instruction Cache Virtually-addressed 4-way Associative Cache Eight words line Write-through Write-back Operation Pseudo-random Round-robin Replacement Write Buffer Main Write Buffer with 16-word Data Buffer 4-address Buffer DCache Write-back Buffer with 8-word Entries Single Address Entry Software Control Drain Standard Memory Management Unit (MMU) Access Permission Sections Access Permission large pages small pages specified separately each quarter page embedded domains Interface Unit (BIU) Arbitrates Schedules Requests Separate Masters both instruction data access providing complete Matrix system flexibility Separate Address Data Buses both 32-bit instruction interface 32-bit data interface Address Data Buses, data 8-bit (Bytes), 16-bit (Half-words) 32-bit (Words)
Matrix
12-layer Matrix, handling requests from masters Programmable Arbitration strategy Fixed-priority Arbitration
6264BS-CAP-26-Nov-07
Round-Robin Arbitration, either with default master, last accessed default master fixed default master Burst Management Breaking with Slot Cycle Limit Support Undefined Burst Length Support Address Decoder provided Master Three different slaves assigned each decoded memory area: internal boot, external boot, after remap Boot Mode Select Non-volatile Boot Memory internal external Selection made sampled reset Remap Command Allows Remapping Internal SRAM Place Boot Non-Volatile Memory Allows Handling Dynamic Exception Vectors
Matrix Masters
Matrix AT91CAP9S500A/AT91CAP9S250A manages twelve Masters thus each master perform access concurrently with others, assuming that slave accesses available. Each Master decoder, which defined specifically each master. order simplify addressing, masters have same decoding. Table 7-1.
Master Master Master Master Master Master Master Master Master Master Master Master
List Matrix Masters
ARM926Instruction ARM926 Data Peripheral Controller Controller High Speed Device Controller Image Sensor Interface Controller Ethernet OHCI Host Controller Block Master Block Master Block Master
Matrix Slaves
Matrix AT91CAP9S500A/AT91CAP9S250A manages Slaves. Each Slave arbiter, thus permitting different arbitration Slave programmed.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Controller, Host High Speed Device have user interface mapped Slave Matrix. They share same layer, programming them does require high bandwidth. Table 7-2.
Slave Slave
List Matrix Slaves
Internal SRAM Kbytes Block Slave Block Internal Memories) Internal Controller User Interface
Slave High Speed Device Interface OHCI Host Interface Slave Slave Slave Slave Slave Slave Slave Block Slave Block Internal Memories) External Interface Controller Port Controller Port Block Slave Block External Chip Selects) Block Slave Block Internal Peripherals) Internal Peripherals AT91CAP9
Master-to-Slave Access
Masters normally access Slaves. However, some paths make sense, such allowing access from Ethernet Internal Peripherals. Thus, these paths forbidden simply wired, shown Table 7-3, "AT91CAP9S500A/AT91CAP9S250A Masters Slaves Access," page
6264BS-CAP-26-Nov-07
Table 7-3.
Master
AT91CAP9S500A/AT91CAP9S250A Masters Slaves Access
ARM926 Instruction Peripheral Ctrl Image Sensor Interface OHCI Host Ctrl Block Master Block Master Block Master X(1) X(1)
High Speed Device Ctrl
ARM926 Data
Slave
Internal SRAM Kbytes Block Slave Internal Controller User Interface
Ethernet
Ctrl
LCDCtrl
High Speed Device Interface OHCI Host Interface
MPBlock Slave External Interface
Port Port Port Port
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
MPBlock Slave MPBlock Slave Internal Peripherals
Note:
Port Port selectable each master through Matrix Remap Control Register.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Peripheral Controller
Acting Matrix Master Allows data transfers from/to peripheral to/from memory space without intervention processor. Next Pointer Support, forbids strong real-time constraints buffer management. Twenty-two Channels each USART Debug Unit Controller AC97 Controller each Serial Synchronous Controller each Serial Peripheral Interface each Multimedia Card Interface Peripheral Controller handles transfer requests from channel according following priorities (Low High priorities): DBGU Transmit Channel USART2 Transmit Channel USART1 Transmit Channel USART0 Transmit Channel AC97 Transmit Channel SPI1 Transmit Channel SPI0 Transmit Channel SSC1 Transmit Channel SSC0 Transmit Channel DBGU Receive Channel Transmit/Receive Channel Receive Channel USART2 Receive Channel USART1 Receive Channel USART0 Receive Channel AC97 Receive Channel SPI1 Receive Channel SPI0 Receive Channel SSC1 Receive Channel SSC0 Receive Channel MCI1 Transmit/Receive Channel MCI0 Transmit/Receive Channel
6264BS-CAP-26-Nov-07
Controller
Acting Matrix Master Embeds unidirectional channels with programmable priority Address Generation Source destination address programming Address increment, decrement change chaining support multiple non-contiguous data blocks through linked lists Scatter support placing fields into system memory area from contiguous transfer. Writing stream data into non-contiguous fields system memory Gather support extracting fields from system memory area into contiguous transfer User enabled auto-reloading source, destination control registers from initially programmed values block transfer Auto-loading source, destination control registers from system memory block transfer block chaining mode Unaligned system address data transfer width supported hardware Channel Buffering 8-word FIFO Automatic packing/unpacking data FIFO width Channel Control Programmable multiple transaction size each channel Support cleanly disabling channel without data loss Suspend operation Programmable lock transfer support Transfer Initiation Support four External Requests four Internal request from Block Support Software handshaking interface. Memory mapped registers used control flow transfer place hardware handshaking interface Interrupt Programmable Interrupt generation Transfer completion Block Transfer completion, Single/Multiple transaction completion Error condition
Debug Test ARM926 Real-time In-circuit Emulator real-time Watchpoint Units Independent Registers: Debug Control Register Debug Status Register Test Access Port Accessible through JTAG Protocol Debug Communications Channel Debug Unit Two-pin UART
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Debug Communication Channel Interrupt Handling Chip Register IEEE1149.1 JTAG Boundary-scan Digital Pins
6264BS-CAP-26-Nov-07
Memories
Figure 8-1. AT91CAP9S500A/AT91CAP9S250A Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory SRAM SLAVE0 SLAVE0 LCDC
Notes ROM, EBI_NCS0 SRAM depending RCB0, RCB1
256M Bytes
0x1000 0000 Chip Select
0x1FFF FFFF 0x0030 0000
256M Bytes
0x0040 0000 0x0050 0000
0x2000 0000 Chip Select BCRAMC 256M Bytes
0x0060 0000 0x0070 0000
UDPHS HOST
0x2FFF FFFF
0x3000 0000 Chip Select
0x3FFF FFFF
256M Bytes
0x0080 0000 SLAVE1 0x0090 0000 SLAVE1 0x00A0 0000
0x4000 0000
Chip Select NAND Flash Chip Select Compact Flash Slot Chip Select Compact Flash Slot DDRSDRC
256M Bytes
0x00B0 0000
SLAVE1 SLAVE1
0x4FFF FFFF
0x5000 0000
256M Bytes
0xFF00 0000
Peripheral Mapping
Reserved 0xFFF7 8000 UDPHS 0xFFF7 C000 TCO, TC1, 0xFFF8 0000 MCI0 Bytes Bytes Bytes Bytes Bytes Bytes Bytes 0xFFFF EC00 SSC1 0xFFFA 0000 AC97C Bytes Bytes Bytes Bytes Bytes Bytes Bytes 0xFFFF FC00 EMAC 0xFFFC 0000 ADCC 0xFFFC 4000 Bytes Bytes Bytes Bytes 0xFFFF FFFF Bytes Bytes 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 RSTC SHDC GPBR Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes 0xFFFF EE00 DBGU 0xFFFF F000 SPI0 0xFFFA 8000 SPI1 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 4000 Reserved 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD Reserved bytes bytes bytes 0xFFFF F200 0xFFFF F400 PIOB Bytes PIOA bytes bytes Bytes 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 0xFFFF EA00 0xFFFF EB10 SSC0 Bytes Reserved Bytes Bytes
0x5FFF FFFF
0x6000 0000
System Controller Mapping
0xFFFF C000
256M Bytes
0x6FFF FFFF
0x7000 0000 256M Bytes
0xFFF8 4000 MCI1 0xFFF8 8000 BCRAMC DDRSDRC MATRIX Bytes CCFG Bytes Bytes Bytes bytes Bytes
0x7FFF FFFF
0x8000 0000 SLAVE2 Chip Select
0x8FFF FFFF
256M Bytes
0xFFF8 C000 USART0 0xFFF9 0000 USART1
0x9000 0000 SLAVE Chip Select
0x9FFF FFFF
256M Bytes
0xFFF9 4000 USART2 0xFFF9 8000
0xA000 0000 SLAVE Chip Select
0xAFFF FFFF
256M Bytes
0xFFF9 C000
0xB000 0000 SLAVE Chip Select
0xBFFF FFFF
256M Bytes
0xFFFA 4000
0xC000 0000
Undefined (Abort)
768M Bytes
0xFFFB 8000 PWMC 0xFFFB C000
0xEFFF FFFF
Undefined (Abort) 0xFCFF FFFF 0xFD00 0000 SLAVE3 0xFE00 0000 SLAVE3 0xFF00 0000 Internal Peripherals
0xFFFF FFFF
0xF000 0000
0xFFFC 8000
208M Bytes Bytes Bytes Bytes
Reserved 0xFFFC C000 Reserved 0xFFFF C000 SYSC 0xFFFF FFFF
Reserved
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
first level address decoding performed Matrix, i.e., implementation Advanced High-performance (AHB) Master Slave interfaces with additional features. Decoding breaks bytes address space into banks 256M bytes. banks directed that associates these banks external chip selects EBI_NCS0 EBI_NCS5 EBI_SDDRCS. bank reserved addressing internal memories, second level decoding provides byte internal memory area. banks directed Block (Slave used address external memories. bank split into three parts, reserved peripherals that provides access Advanced Peripheral (APB), others directed Block (Slave provide access Block other peripherals. Other areas unused performing access within them provides abort master requesting such access. Each Master decoder, thus allowing different memory mapping Master. However, order simplify mappings, masters have similar address decoding. Regarding Master Master (ARM926 Instruction Data), three different Slaves assigned memory space decoded address 0x0: internal boot, external boot after remap. Refer Table 8-1, "Internal Memory Mapping," page details.
Embedded Memories
Kbyte Single Cycle Access full matrix speed Kbyte Fast SRAM Single Cycle Access full matrix speed Kbyte Block Fast Dual Port (ten 512x36 instances) Used Dual Port completely managed Block Kbyte Block Fast Single Port (eight 512x72 instances) Used Single Port completely managed Block
6264BS-CAP-26-Nov-07
8.1.1
Internal Memory Mapping Table summarizes Internal Memory Mapping, depending Remap Command (RBC) status state reset.
Table 8-1.
Address
Internal Memory Mapping
ARM926 RCB0 RCB0 SRAM EBI_NCS0 ARM926 RCB1 SRAM Abort RCB1 Other Masters
0x0000 0000
EBI_NCS0
8.1.1.1
Internal Kbyte Fast SRAM AT91CAP9S500A/AT91CAP9S250A integrates Kbyte SRAM, mapped address 0x0010 0000,which accessible from bus. This SRAM single cycle accessible full matrix speed. Boot Memory AT91CAP9S500A/AT91CAP9S250A Matrix manages boot memory which depends level reset. internal memory area mapped between address 0x000F FFFF reserved this effect. detected boot memory memory connected Chip Select External Interface. default configuration Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled Chip Select, allows boot 16-bit non-volatile memory. detected boot memory embedded ROM.
8.1.1.2
8.1.2
Boot Program Downloads runs application from external storage media into internal SRAM Downloaded code size depends embedded SRAM size Automatic detection valid application Bootloader non-volatile memory DataFlash® connected NPCS0 SPI0 Boot Uploader case valid program detected external supporting several communication media Serial communication DBGU Bulk Device Port External Memories Mapping external memories accessed through External Interface. Each Chip Select lines Mbyte memory area assigned.
External Memories
external memories accessed through External Interfaces. Each Chip Select line Mbyte memory area assigned. Refer Figure page
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
8.2.1 External Interface AT91CAP9S500A/AT91CAP9S250A features External Interface offer high bandwidth system prevent bottleneck while accessing external memories. Optimized Application Memory Space support Integrates three External Memory Controllers: Static Memory Controller 4-port DDR/SDRAM Controller Burst/CellularRAM Controller Controller NAND Flash Additional logic NAND Flash CompactFlash Optional Full 32-bit External Data 26-bit Address Mbytes linear chip select) chips selects, Configurable Assignment: Static Memory Controller NCS0 Burst/CellularRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2 Static Memory Controller NCS3, Optional NAND Flash support Static Memory Controller NCS4 NCS5, Optional CompactFlash support dedicated chip select: DDR/SDRAM Controller NCS6 8.2.2 Static Memory Controller 32-bit Data Multiple Access Modes supported Byte Write Byte Select Lines Asynchronous read Page Mode supported 32-byte page size) Multiple device adaptability Compliant with Module Control signals programmable setup, pulse hold time each Memory Bank Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time Slow Clock mode supported 8.2.3 DDR/SDRAM Controller Supported devices: Standard Power SDRAM (Mobile SDRAM) Mobile Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks
6264BS-CAP-26-Nov-07
SDRAM with 32-bit Data Path Mobile with four Internal Banks Mobile with 16-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Multiport Ports) Energy-saving capabilities Self-refresh, power down deep power down modes supported Error detection Refresh Error Interrupt DDR/SDRAM Power-up Initialization software SDRAM Latency supported latency supported Auto Precharge Command used 8.2.4 Burst Cellular Controller Supported devices: Synchronous Cellular version 1.0, Numerous configurations supported 64K, 128K, 256K, 512K Address Memory Parts Cellular with 32-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Timing parameters specified software Only Continuous read write burst supported Energy-saving capabilities Standby Deep Power Down (DPD) modes supported Power features (PASR/TCSR) supported Cellular Power-up Initialization hardware Cellular latency supported (Version 1.0) Cellular latency supported (Version 2.0) Cellular variable fixed latency supported (Version 2.0) Multiplexed address/data supported (Version 2.0) Asynchronous Page mode supported.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
8.2.5 Error Corrected Code Controller Tracking accesses NAND Flash device trigging corresponding chip select Single error correction 2-bit Random detection. Automatic Hamming Code Calculation while writing value available register Automatic Hamming Code Calculation while reading Error Report, including error flag, correctable error flag word address being detected erroneous Support 16-bit NAND Flash devices with 512-, 1024-, 2048- 4096-byte pages
6264BS-CAP-26-Nov-07
System Controller
System Controller peripherals, which allow handling elements system, such power, resets, clocks, time, interrupts, watchdog, etc. System Controller User Interface also embeds registers that allow configuration Matrix registers chip configuration. chip configuration registers used configure: chip select assignment voltage range external memories Block System Controller peripherals mapped within highest Kbytes address space, between addresses 0xFFFF C000 0xFFFF FFFF. However, registers System Controller mapped address space. This allows registers System Controller addressed from single pointer using standard instruction set, Load/Store instructions have indexing mode Kbytes. Figure page shows System Controller block diagram. Figure page shows mapping User Interfaces System Controller peripherals.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
System Controller Block Diagram
AT91CAP9S500A/AT91CAP9S250A System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq1 periph_irq[2.29] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer rtt_irq rtt_alarm Debug Unit Advanced Interrupt Controller por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 9-1.
dbgu_irq dbgu_txd
proc_nreset debug
pit_irq jtag_nreset wdt_irq periph_nreset Matrix Boundary Scan Controller
VDDBU
SLCK backup_nreset
SLCK SHDN WKUP backup_nreset XIN32 XOUT32 SLOW CLOCK rtt_alarm Shut-Down Controller Voltage Controller battery_save
UDPHSCK General-purpose Backup Registers periph_clk[28] periph_nreset High-speed Device Port
SLCK UTMI XOUT PLLRCA PLLRCB MAIN PLLA PLLB periph_nreset UDPHSCK Power Management Controller
periph_clk[2.31] pck[0-3]
periph_irq[28]
MAINCK
UHPCK pmc_irq idle
UHPCK periph_clk[29] periph_nreset periph_irq[29] Host Port
PLLACK PLLBCK
periph_clk[7.31] periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 periph_irq[2] irq0-irq1 dbgu_txd periph_nreset periph_irq[7.27] enable Embedded Peripherals
Controllers
6264BS-CAP-26-Nov-07
Reset Controller
Based Power-on-Reset cells VDDBU VDDCORE Status last reset Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset watchdog reset Controls internal resets NRST output Allows shaping reset signal external devices
Shutdown Controller
Shutdown Wake-Up logic Software programmable assertion SHDN Deassertion Programmable WKUP level change alarm
Clock Generator
Embeds power 32,768 Slow Clock Oscillator Provides permanent Slow Clock SLCK system Embeds Main Oscillator Oscillator bypass feature Supports crystals crystal required High-Speed Device Embeds PLLs Output clocks Integrates input divider increase output accuracy minimum input frequency
Figure 9-2.
Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
Divider Divider Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Power Management Controller
Provides: Processor Clock Master Clock MCK, particular Matrix memory interfaces High-speed Device Clock UDPHSCK Host Clock UHPCK independent peripheral clocks, typically frequency four programmable clock outputs: PCK0 PCK3 Five flexible operating modes: Normal Mode, processor peripherals running programmable frequency Idle Mode, processor stopped waiting interrupt Slow Clock Mode, processor peripherals running frequency Standby Mode, Idle Backup Mode, peripheral running frequency, processor stopped waiting interrupt Backup Mode, Main Power Supplies off, VDDBU powered battery Figure 9-3. AT91CAP9S500A/AT91CAP9S250A Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.,/64 Divider /1,/2,/4 Peripherals Clock Controller ON/OFF DDRCK Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,.,/64 pck[.] Idle Mode
periph_clk[.]
Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UHPCK
Periodic Interval Timer
Includes 20-bit Periodic Counter, with less than accuracy Includes 12-bit Interval Overlay Counter Real-time Linux/WinCE compliant tick generator
6264BS-CAP-26-Nov-07
Watchdog Timer
16-bit key-protected only-once-Programmable Counter Windowed, prevents processor dead-lock watchdog access
Real-time Timer
Real-time Timers, allowing backup time with different accuracies 32-bit Free-running back-up Counter Integrates 16-bit programmable prescaler running embedded 32,768 oscillator Alarm Register generate wake-up system through Shutdown Controller
General-Purpose Backed-up Registers
Four 32-bit backup general-purpose registers
9.10
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Thirty-two individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (PIT, RTT, PMC, DBGU, etc.) Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level-sensitive Four External Sources plus Fast Interrupt signal 8-level Priority Controller Drives Normal Interrupt processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes Interrupt Service Routine Branch Execution 32-bit Vector Register interrupt source Interrupt Vector Register reads corresponding current Interrupt Vector Protect Mode Easy debugging preventing automatic operations when protect models enabled Fast Forcing Permits redirecting normal interrupt source Fast Interrupt processor
9.11
Debug Unit
Composed functions Two-pin UART Debug Communication Channel (DCC) support
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Two-pin UART Implemented features 100% compatible with standard Atmel USART Independent receiver transmitter with common programmable Baud Rate Generator Even, Odd, Mark Space Parity Generation Parity, Framing Overrun Error Detection Automatic Echo, Local Loopback Remote Loopback Channel Modes Support channels with connection receiver transmitter Debug Communication Channel Support Offers visibility interrupt trigger from COMMRX COMMTX signals from Processor's Interface
9.12
Chip Identification
Chip 0x039A03A0 JTAG 0x05B1B03F ARM926 0x0792603F
9.13
Controllers
Controllers, PIOA PIOD, controlling total Lines Each Controller controls programmable Lines PIOA Lines PIOB Lines PIOC Lines PIOD Lines Fully programmable through Set/Clear Registers Multiplexing peripheral functions Line each Line (whether assigned peripheral used general purpose I/O) Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
6264BS-CAP-26-Nov-07
Peripherals
10.1 User Interface
peripherals mapped upper Mbytes address space between addresses 0xFFFA 0000 0xFFFC FFFF. Each user peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Identifiers
AT91CAP9S500A/AT91CAP9S250A embeds wide range peripherals. Table 10-1 defines Peripheral Identifiers AT91CAP9S500A/AT91CAP9S250A. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller. Table 10-1.
Peripheral
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers
Peripheral Mnemonic SYSC PIOA-D MPB0 MPB1 MPB2 MPB3 MPB4 MCI0 MCI1 SPI0 SPI1 SSC0 SSC1 AC97 TC0, TC1, PWMC EMAC Reserved Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel Controller Block Peripheral Block Peripheral Block Peripheral Block Peripheral Block Peripheral USART USART USART Multimedia Card Interface Multimedia Card Interface Controller Two-Wire Interface Serial Peripheral Interface Serial Peripheral Interface Synchronous Serial Controller Synchronous Serial Controller AC97 Controller Timer/Counter Pulse Width Modulation Controller Ethernet Reserved External Interrupt
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Table 10-1.
Peripheral
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers (Continued)
Peripheral Mnemonic ADCC LCDC UDPHS Peripheral Name Controller Image Sensor Interface Controller Controller High Speed Device Port Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt
10.2.1 10.2.1.1
Peripheral Interrupts Clock Control System Interrupt System Interrupt Source wired-OR interrupt signals coming from: DDR/SDRAM Controller BCRAM Controller Debug Unit Periodic Interval Timer Real-Time Timer Watchdog Timer Reset Controller Power Management Controller Block clock these peripherals cannot deactivated Peripheral only used within Advanced Interrupt Controller.
10.2.1.2
External Interrupts external interrupt signals, i.e., Fast Interrupt signal Interrupt signals IRQ0 IRQ1, dedicated Peripheral However, there clock control associated with these peripheral IDs. Timer Counter Interrupts three Timer Counter channels interrupt signals OR-wired together provide interrupt source Advanced Interrupt Controller. This forces programmer read Timer Counter status registers before branching right Interrupt Service Routine. Timer Counter channels clocks cannot deactivated independently. Switching clock Peripheral disables clock channels.
10.2.1.3
6264BS-CAP-26-Nov-07
10.2.2
Controller Request Signals requests Controller come from eight different sources: four external requests four internal requests from MPBlock
Table 10-2.
Controller Request Source Signal Names
Internal Request from MPBlock External Request Channel DMARQ3 Channel DMARQ2 Channel DMARQ1 Channel DMARQ0
Channel MP_DMARQ3
Channel MP_DMARQ2
Channel MP_DMARQ1
Channel MP_DMARQ0
Each request source selected through DMAC Channel Configuration Register. also necessary choose hardware handshaking interface from SRC_H2SEL DST_H2SEL fields. (For more details, Controller (DMAC) section DMAC User Interface product datasheet.)
10.3
Peripheral Signal Multiplexing Lines
AT91CAP9S500A/AT91CAP9S250A features controllers, PIOA, PIOB, PIOC PIOD, that multiplex lines peripheral set. Each Controller controls lines. Each line assigned peripheral functions, multiplexing tables following paragraphs define lines peripherals multiplexed Controllers. columns "Function" "Comments" have been inserted this table user's comments; they used track pins defined application. Note that some peripheral functions which output only duplicated within both tables. column "Reset State" indicates whether Line resets mode peripheral mode. mentioned, Line resets input with pull-up enabled, that device maintained static state soon reset released. result, corresponding Line register PIO_PSR (Peripheral Status Register) resets low. signal name mentioned "Reset State" column, Line assigned this function corresponding PIO_PSR resets high. This case pins controlling memories, particular address lines, which require driven soon reset released. Note that pull-up resistor also enabled this case.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
10.3.1 Controller Multiplexing Multiplexing Controller
Controller Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Note: Peripheral MCI0_D0 MCI0_CD MCI0_CK MCI0_D1 MCI0_D2 MCI0_D3 AC97FS AC97CK AC97TX AC97RX IRQ0 DMARQ0 CANTX CANRX TCLK2 DMARQ3 MCI1_CK MCI1_CD MCI1_D0 MCI1_D1 MCI1_D2 MCI1_D3 TXD0 RXD0 RTS0 CTS0 SCK0 PCK1 SPI0_NPCS3 TIOA0 TIOB0 DMARQ1 IRQ1 PCK2 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK ISI_D8 ISI_D9 ISI_D10 ISI_D11 PWM1 PWM3 PCK0 Peripheral SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0 Comments Reset State Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed Function 324-BGA Options(1)
Table 10-3.
user must ensure that removing designated pins does have adverse effect intended application.
6264BS-CAP-26-Nov-07
10.3.2
Controller Multiplexing Multiplexing Controller
Controller Application Usage Comments Reset State TWCK TIOA1 TIOB1 PWM2 LCDCC PCK1 TIOA2 TIOB2 PCK3 TCLK0 PWM3 EF100 Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 removed removed removed removed removed removed removed removed removed removed removed Function 324-BGA Options(1)
Table 10-4.
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note:
Peripheral SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PWM0 PWM1 ETXCK/EREFCK ERXDV ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO ADTRIG
Peripheral
user must ensure that removing designated pins does have adverse effect intended application.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
10.3.3 Controller Multiplexing Multiplexing Controller
Controller Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note: Peripheral LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ECRS ECOL ERXCK TCLK1 PWM2 Peripheral Comments Reset State Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function 324-BGA Options(1) removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed removed
Table 10-5.
user must ensure that removing designated pins does have adverse effect intended application.
6264BS-CAP-26-Nov-07
10.3.4
Controller Multiplexing Multiplexing Controller
Controller Application Usage Comments Reset State RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function 324-BGA Options(1) removed removed removed removed removed removed removed removed removed removed removed
Table 10-6.
Line PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 Note:
Peripheral TXD1 RXD1 TXD2 RXD2 DMARQ2 NWAIT NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS2 A25/CFRNW NCS3/NANDCS
Peripheral SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3
user must ensure that removing designated pins does have adverse effect intended application.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
10.4
10.4.1
Embedded Peripherals
Serial Peripheral Interface Supports communication with serial external devices Four chip selects with external decoder support allow communication with peripherals Serial memories, such DataFlash 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Very fast transfers supported Transfers with baud rates chip select line left active speed transfers same device
10.4.2
Two-wire Interface Compatibility with standard two-wire serial memory One, three bytes slave address Sequential read/write operations
10.4.3
USART Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection MSB- LSB-first Optional break generation detection by-16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out transmitter timeguard Optional Multi-drop Mode with address generation detection Optional Manchester Encoding RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit
6264BS-CAP-26-Nov-07
IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Synchronous Serial Controller Provides serial synchronous communication links used audio telecom applications (with CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader, etc.) Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal 10.4.5 AC97 Controller Compatible with AC97 Component Specification V2.2 Capable Interface with Single Analog Front Three independent Channels three independent Channels channel dedicated AC97 Analog Front control channel data transfers, associated with channel data transfers with Time Slot Assigner allowing assign time slots channel Channels support mono stereo sample length Variable sampling rate AC97 Codec Interface (48KHz below) 10.4.6 Timer Counter Three 16-bit Timer Counter Channels Wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals global registers that three Channels
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
10.4.7 Pulse Width Modulation Controller channels, 16-bit counter channel Common clock generator, providing Thirteen Different Clocks Modulo counter providing eleven clocks independent Linear Dividers working modulo counter outputs Independent channel programming Independent Enable Disable Commands Independent Clock Selection Independent Period Duty Cycle, with Double Bufferization Programmable selection output waveform polarity Programmable center left aligned output waveform 10.4.8 Multimedia Card Interface double-channel Multimedia Card Interface, allowing concurrent transfers with cards Compatibility with MultiMedia Card Specification Version 3.31 Compatibility with Memory Card Specification Version Compatibility with SDIO Specification Version V1.0. Cards clock rate Master Clock divided Embedded power management slow down clock rate when used Each slot supporting MultiMediaCard cards) Memory Card SDIO Card Support stream, block multi-block data read write 10.4.9 Controller Fully compliant with 16-mailbox 2.0A 2.0B Controllers rates 1Mbit/s. Object-oriented mailboxes, each with following properties: Specification Part Part Programmable Each Message Object Configurable receive (with overwrite not) transmit Local Mask Filters 29-bit Identifier/Channel bits access Data registers each mailbox data object Uses 16-bit time stamp receive transmit message Hardware concatenation unmasked bitfields speedup family processing 16-bit internal timer Time Stamping Network synchronization Programmable reception buffer length mailbox object Priority Management between transmission mailboxes Autobaud listening mode power mode programmable wake-up activity application Data, Remote, Error Overload Frame handling
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
10.4.10 Host Port Compliance with OHCI Specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-speed Mbps Full-speed Mbps devices Root integrated with downstream ports embedded transceivers Supports power management Operates master Matrix Internal Controller, operating Master Matrix 10.4.11 High Speed Device Port V2.0 high-speed compliant, MBits second Embedded V2.0 UTMI+ high-speed transceiver Embedded 4K-byte dual-port endpoints Embedded channels controller Suspend/Resume logic banks isochronous bulk endpoints Seven endpoints: Endpoint bytes Endpoint 1024 bytes, banks mode, isochronous capable Endpoint 1024 bytes, banks mode, isochronous capable Endpoint 1024 bytes, banks mode Endpoint 1024 bytes, banks mode 10.4.12 Controller Single Dual scan color monochrome passive panels supported Single scan active panels supported 4-bit single scan, 8-bit single dual scan, 16-bit dual scan interfaces supported 24-bit single scan interfaces supported gray levels mono 4096 colors color displays bits pixel (palletized), bits pixel (non-palletized) mono bits pixel (palletized), bits pixel (non-palletized) color bits pixel (palletized), bits pixel (non-palletized) Single clock domain architecture Resolution supported 2048x2048 2D-DMA Controller management virtual Frame Buffer Allows management frame buffer larger than screen size moving view over this virtual frame buffer Automatic resynchronization frame buffer pointer prevent flickering 10.4.13 Ethernet 10/100 Compatibility with IEEE Standard 802.3
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
MBits second data throughput capability Full- half-duplex operations RMII interface physical layer Register Interface address, data, status control registers Internal Controller, operating Master Matrix Interrupt generation signal receive transmit completion 28-byte transmit 28-byte receive FIFOs Automatic generation transmitted frames Address checking logic recognize four 48-bit addresses Support promiscuous mode where valid frames copied memory Support physical layer management through MDIO interface control alarm update time/calendar data 10.4.14 Image Sensor Interface ITU-R 601/656 8-bit mode external interface support Support ITU-R BT.656-4 synchronization Vertical horizontal resolutions 2048 2048 Preview Path 640*480 Support packed data formatting YCbCr 4:2:2 formats Preview scaler generate smaller size image Programmable frame capture rate Internal Controller, operating Master Matrix 10.4.15 Analog-to-digital Converter 8-channel 10-bit 440K samples/sec. Successive Approximation Register -2/+2 Integral Linearity, -1/+1 Differential Linearity Individual enable disable each channel External voltage reference better accuracy voltage inputs Multiple trigger source Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 TIOB0 TIOB2 triggers Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Four analog inputs shared with digital signals
6264BS-CAP-26-Nov-07
Metal Programmable Block
Metal Programmable Block (MPBlock) connected internal resources interrupts external resources dedicated pads UTMI+ core. MPBlock used implement Advanced High-speed (AHB) Advanced Peripheral (APB) custom peripherals. MPBlock adds approximately 500K 250K gates standard cell custom logic AT91CAP9S500A/AT91CAP9S250A base design. Figure 11-1 shows MPBlock connections internal external resources. Figure 11-1. MPBlock Connectivity
MASTERS SLAVES
MPBlock Test Wrapper CLOCKS CAN, MACB, OHCI ENABLE MPBLOCK 500K Gates (CAP9500) 250K Gates (CAP9250) 512x36
512x72
CHIP JTAG
UTMI+
Chip Boundary Scan
MPIOA[31:0]
MPIOB[44:0]
11.1
Internal Connectivity
order connect MPBlock custom peripheral AT91CAP9S500A/AT91CAP9S250A base design, following connections made.
11.1.1
Clocks MPBlock receives following clocks: 32,768 Slow Clock Main Oscillator Clock PLLA Clock PLLB Clock Clock Clock
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
UTMI+ Clock System Clock DDRCK Dual Rate System Clock Processor Clock Gated Peripherals Clock (for and/or peripherals) corresponding Peripheral 11.1.2 Master Buses MPBlock implement three masters, each having dedicated master connected Matrix. Slave Buses MPBlock receives four different slave buses coming from Matrix. Each four select signals that implement slaves. Interrupts MPBlock connected dedicated interrupt lines corresponding Peripheral also connected other interrupt lines (through gate) corresponding Peripheral 11.1.5 Channels MPBlock connected hardware handshaking interfaces, allowing implement enabled peripherals. Peripheral Channels MPBlock connected Peripheral Controller. order implement Peripheral Controller (PDC) enabled peripherals, AHB-to-APB Bridge must integrated into MPBlock using master slave bus. MPBlock Single Port RAMs MPBlock connected eight instances 512x72 High-Speed Single Port RAMs. MPBlock control over memory connections. 11.1.8 MPBlock Dual Port RAMs MPBlock connected instances 512x36 High-Speed Dual Port RAMs. MPBlock control over memory connections. 11.1.9 Optional Peripherals Enable MPBlock drives enable optional peripherals, enable disable optional peripherals.
11.1.3
11.1.4
11.1.6
11.1.7
6264BS-CAP-26-Nov-07
11.2
External Connectivity
MPBlock connected following external resources.
11.2.1
Dedicated Lines MPBlock directly connected MPIOA MPIOB lines) dedicated Pads with following features: Supply/Drive control (needed high-speed voltage interfaces) Pull-up control Supported logic levels include: LVCMOS33 maximum frequency LVCMOS25 maximum frequency LVCMOS18 maximum frequency Only dedicated pins available TFBGA324 package.
11.2.2
UTMI+ Transceiver MPBlock connected UTMI+ transceiver. only UTMI+ transceiver available, High-speed Device MPBlock have access UTMI+ same time. However, dual role Master-Slave High-Speed implemented using High-speed Device integrating High-speed Host MPBlock switching between both generated inside MPBlock.
11.3
Prototyping Solution
order prototype final custom design, Prototyping Platform version AT91CAP9S500A/AT91CAP9S250A design been created. platform maps masters slaves into FPGA located outside chip with following features restrictions: AT91CAP9S500A/AT91CAP9S250A FPGA interface provided prototype masters slave into external FPGA exactly were MPBlock. Prototyped Masters Prototyped Masters have access AT91CAP9S500A/AT91CAP9S250A slave resources. Prototyped Masters have access MPBlock (FPGA) slave resources. Prototyped Slaves Prototyped Slaves accessed from AT91CAP9S500A/AT91CAP9S250A master resources. Prototyped Slaves accessed from MPBlock (FPGA) resources. Prototyped Slaves must created locally FPGA implementing bridge. Peripheral controller also necessary implement locally FPGA order prototype enabled peripherals. Figure 11-2 shows typical prototyping solution.
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Figure 11-2. Typical Prototyping Solution
CAP9500 CAP9250
MASTERS
ARM926EJ-S
Matrix
4-channel
Metal Programmable Block 500K Gates (CAP9500) 250K Gates (CAP9250) FPGA Interface
MPIOA[31:0]
MPIOB[44:0] FPGA
CAP9500/CAP9250 FPGA Interface Local Matrix
MASTER
BRIDGE
MASTER
SLAVE
SLAVE SLAVE
MPBlock Emulation Area
6264BS-CAP-26-Nov-07
AT91CAP9S Mechanical Characteristics
12.1 Package Drawing
Figure 12-1. 400-ball LFBGA Package Drawing
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Figure 12-2. 324-ball TFBGA Package
6264BS-CAP-26-Nov-07
AT91CAP9S Ordering Information
Table 13-1. CAP9S Ordering Information
Package BGA400 AT91CAP9S500A-CJ AT91CAP9S250A-CJ BGA324 AT91CAP9S500A-CJ RoHS Compliant Package Type RoHS Compliant Temperature Operating Range Industrial -40°C 85°C Industrial -40°C 85°C
Ordering Code AT91CAP9S250A-CJ
AT91CAP9S500A/AT91CAP9S250A
6264BS-CAP-26-Nov-07
AT91CAP9S500A/AT91CAP9S250A
Revision History
Change Request Ref.
Document Ref.
Comments "Features" PIOD typo fixed. "Required Power Supplies:" page important update supplies added. "One 8-channel, 10-bit Analog-to-Digital Converter (ADC)" added features Section 10.4.15 "Analog-to-digital Converter", added. "Features" 32-ball Package added. Section "Package Pinout", 324-ball TFBGA package added. Figure 4-2, "324-ball TFBGA Package Outline Marking (Top View)," page added. Figure 12-2, "324-ball TFBGA Package," page added. Figure page Block Diagram updated Table 3-1, "Signal Description List," 324-ball TFBGA package options added note MPBLOCK parameters. Section 10.3.1 page Section 10.3.2 page Section 10.3.3 page Section 10.3.4 page Multiplexing I/Os updated with 324-ball TFBGA options. Section 10.4.11 "USB High Speed Device Port", Endpoint information corrected. Figure 8-1, "AT91CAP9S500A/AT91CAP9S250A Memory Mapping," page note associated with "boot memory" updated. Table 8-1, "Internal Memory Mapping," page updated. Figure 4-1, "400-ball LFBGA Package Outline Marking (Top View)," page updated with package marking. Section 10.2.2 "DMA Controller Request Signals", section added. Section 10.4.11 "USB High Speed Device Port", endpoints isochronous capable".
6246BS
4490
4916
4263
6264AS
First issue.
6264BS-CAP-26-Nov-07
Headquarters
Atmel Corporation 2325 Orchard Parkway Jose, 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Krebs Jean-Pierre Timbaud 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Site www.atmel.com www.atmel.com/AT91CAP Technical Support Atmel techincal support Sales Contacts www.atmel.com/contacts/
Literature Requests www.atmel.com/literature
Disclaimer: information this document provided connection with Atmel products. license, express implied, estoppel otherwise, intellectual property right granted this document connection with sale Atmel products. EXCEPT FORTH ATMEL'S TERMS CONDITIONS SALE LOCATED ATMEL'S SITE, ATMEL ASSUMES LIABILITY WHATSOEVER DISCLAIMS EXPRESS, IMPLIED STATUTORY WARRANTY RELATING PRODUCTS INCLUDING, LIMITED IMPLIED WARRANTY MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NON-INFRINGEMENT. EVENT SHALL ATMEL LIABLE DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES LOSS PROFITS, BUSINESS INTERRUPTION, LOSS INFORMATION) ARISING INABILITY THIS DOCUMENT, EVEN ATMEL BEEN ADVISED POSSIBILITY SUCH DAMAGES. Atmel makes representations warranties with respect accuracy completeness contents this document reserves right make changes specifications product descriptions time without notice. Atmel does make commitment update information contained herein. Unless specifically provided otherwise, Atmel products suitable for, shall used automotive applications. Atmel's products intended, authorized, warranted components applications intended support sustain life.
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6264BS-CAP-26-Nov-07

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