Power CapSense Block Configurable Capacitive Sensing Elements Supports

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Power CapSense Block Configurable Capacitive Sensing Elements Supports

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CY8C20534, CY8C20434 CY8C20334, CY8C20234
Power CapSense Block Configurable Capacitive Sensing Elements Supports Combination CapSense Buttons, Sliders, Touchpads, Proximity Sensors Powerful Harvard Architecture Processor Processor Speeds Running Power High Speed 2.4V 5.25V Operating Voltage Industrial Temperature Range: -40°C +85°C Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage Partial Flash Updates Flexible Protection Modes Interrupt Controller In-System Serial Programming (ISSP) Complete Development Tools Free Development Tool (PSoC DesignerTM) Full Featured, In-Circuit Emulator, Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory
Precision, Programmable Clocking Internal ±5.0% 6/12 Main Oscillator Internal Speed Oscillator Watchdog Sleep Programmable Configurations Pull High Open Drain, CMOS Drive Modes GPIO Analog Inputs GPIO Configurable Inputs GPIO Selectable, Regulated Digital Port 3.0V, Total Port Source Current Strong Drive Mode Port Versatile Analog Common Internal Analog Simultaneous Connection Combinations Comparator Noise Immunity Dropout Voltage Regulator Analog Array Additional System Resources Configurable Communication Speeds I2C: Selectable kHz, kHz, SPI: Configurable between 46.9 I2CSlave Master Slave Watchdog Sleep Timers Internal Voltage Reference Integrated Supervisory Circuit
Logic Block Diagram
Port Port Port Port Config
PSoC CORE
System
Global Analog Interconnect SRAM Bytes Interrupt Controller SROM Flash Sleep Watchdog
Core (M8C)
6/12 Internal Main Oscillator
ANALOG SYSTEM
CapSense Block
Analog Ref.
Slave/SPI Master-Slave
System Resets
Analog
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-05356 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised November 2007
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PSoC Functional Overview
PSoC® family consists many Mixed Signal Arrays with On-Chip Controller devices. These devices designed replace multiple traditional based system components with cost single chip programmable component. PSoC device includes configurable analog digital blocks programmable interconnect. This architecture enables user create customized peripheral configurations match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. PSoC architecture this device family, shown Figure comprised three main areas: Core, System Resources, CapSense Analog System. common versatile enables connection between analog system. Each CY8C20x34 PSoC device includes dedicated CapSense block that provides sensing scanning control circuitry capacitive sensing applications. Depending PSoC package, general purpose (GPIO) also included. GPIO provide access analog mux. Figure Analog System Block Diagram
Analog Global
eferenc Buffer
internal
parator
Sens ounters
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (Internal Main Oscillator), (Internal speed Oscillator). core, called M8C, powerful processor with speeds MHz. MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability such configurable slave master-slave communication interface various system resets supported M8C. Analog System composed CapSense PSoC block internal 1.8V analog reference. Together they support capacitive sensing inputs.
apSense Selec elaxation illator (RO)
Analog Multiplexer System Analog connects every GPIO pin. Pins connected individually combination. also connects analog system analysis with CapSense block comparator. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
CapSense Analog System
Analog System contains capacitive sensing hardware. Several hardware algorithms supported. This hardware performs capacitive sensing scanning without requiring external components. Capacitive sensing configurable each GPIO pin. Scanning enabled CapSense pins completed quickly easily across multiple ports.
Complex capacitive sensing interfaces such sliders touch pads Chip-wide that enables analog input from Crosspoint connection between combinations
When designing capacitive sensing applications, refer latest signal-to-noise signal level requirements Application Notes, http://www.cypress.com DESIGN found under RESOURCES Application Notes. general, unless otherwise noted relevant Application Notes, minimum signal-to-noise ratio (SNR) requirement CapSense applications 5:1.
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Additional System Resources
System Resources provide additional capability useful complete systems. Additional resources include voltage detection power reset. Brief statements describing merits each system resource presented below.
Technical Training Modules
Free PSoC technical training modules available users PSoC. Training modules cover designing, debugging, advanced analog, CapSense.
slave master-slave module provides 50/100/400 communication over wires. communication over three four wires speeds 46.9 (lower slower system clock). Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.8V reference provides absolute reference capacitive sensing. maximum input, fixed output, dropout regulator (LDO) provides regulation IOs. register controlled bypass mode enables user disable LDO.
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com, click Design Support located left side page select CYPros Consultants.
Technical Support
PSoC application engineers take pride fast accurate response. They available with four hour guaranteed response
Getting Started
understand PSoC silicon read this datasheet PSoC Designer Integrated Development Environment (IDE). This datasheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming information, refer PSoC Mixed Signal Array Technical Reference Manual http://www.cypress.com/psoc. date Ordering, Packaging, Electrical Specification information, refer latest PSoC device datasheets http://www.cypress.com.
Application Notes
long list application notes assist every aspect your design effort. view PSoC application notes, http://www.cypress.com select Application Notes under Design Resources list located center page. Application notes sorted date default.
Development Tools
PSoC Designer Microsoft® Windows based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer application runs Windows 4.0, Windows 2000, Windows Millennium (Me), Windows more information, Figure page PSoC Designer helps customer select operating configuration PSoC, write application code that uses PSoC, debug application. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, CYASM macro assembler CPUs. PSoC Designer also supports high level language compiler developed specifically devices family.
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PSoC development. Cypress Online Store site http://www.cypress.com, click Online Store shopping cart icon bottom page click PSoC (Programmable System-on-Chip) view current list available items.
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Figure PSoC Designer Subsystems
Context Sensitive Help
Assembler macro assembler enables assembly code seamless merging with code. link libraries automatically absolute addressing compiled relative mode linked with other software modules absolute addressing. Language Compiler language compiler supports PSoC family devices. quickly enables create complete programs PSoC family devices.
PSoC Designer
Graphical Designer Interface
Commands
Results
Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet
PSoC Designer Core Engine
Manufacturing Information File
embedded optimizing compiler provides features language tailored PSoC architecture. comes complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, enabling designer test program physical system while providing internal view PSoC device. Debugger commands enable designer read program, read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also enables designer create trace buffer registers memory locations interest. Online Help System online help system displays online context sensitive help user. Designed procedural quick reference, each functional subsystem context sensitive help. This system also provides tutorials links FAQs Online Support Forum designer started.
PSoC Designer Software Subsystems
Device Editor device editor subsystem enables user select different board analog digital components called user modules using PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic reconfiguration enables changing configurations time. PSoC Designer sets power initialization tables selected PSoC block configurations creates source code application framework. framework contains software operate selected components. project uses more than operating configuration, then contains routines switch between different sets PSoC block configurations time. PSoC Designer prints configuration sheet given project configuration during application programming conjunction with device datasheet. Once framework generated, user adds application specific code flesh framework. also possible change selected components regenerate framework. Application Editor Application Editor edits language Assembly language source code. also assembles, compiles, links, builds.
Hardware Tools
In-Circuit Emulator cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with User Modules
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility. pays dividends managing specification change during development lowering inventory costs. These configurable resources called PSoC Blocks. They implement wide variety user selectable functions. Each block several registers determine their function connectivity other blocks, multiplexers, buses, pins. Iterative development cycles permit adapt hardware software. This substantially lowers risk selecting different part meet final design requirements. speed development process, PSoC Designer Integrated Development Environment (IDE) provides library pre-built pre-tested hardware peripheral functions called User Modules. User modules make selecting implementing peripheral devices simple. They come analog, digital, mixed signal varieties. Each user module establishes basic register settings implement selected function. also provides parameters tailor precise configuration particular application. example, Pulse Width Modulator user module configures more digital PSoC blocks, each 8-bits resolution. user module parameters permit establish pulse width duty cycle. User modules also provide tested software development time. user module application programming interface (API) provides high level functions control respond hardware events time. also provides optional interrupt service routines adapt needed. functions documented user module datasheets that viewed directly PSoC Designer IDE. These datasheets explain internal operation user module provide performance specifications. Each datasheet describes each user module parameter documents setting each register controlled user module. development process starts when open project bring Device Editor, graphical user interface (GUI) configuring hardware. Select user modules need your project them PSoC blocks with point-and-click simplicity. Then, build signal chains interconnecting user modules each other pins. this stage, configure clock source connections enter parameter values directly selecting values from drop down menus. When hardware configuration ready testing moves developing code project, perform "Generate Application" step. PSoC Designer generates source code that automatically configures device your specification provides high level user module functions. Figure User Module Source Code Development Flows
Device Editor
User Module Selection Placement Parameter -ization Source Code Generator
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build
Debugger
Interface Storage Inspector Event Breakpoint Manager
write main program sub-routines using PSoC Designer's Application Editor subsystem. Application Editor includes Project Manager that enables open project source code files (including generated code files) from hierarchal view. source code editor provides syntax coloring advanced edit features both assembly language. File search capabilities include simple string searches recursive "grep-style" patterns. single mouse click invokes Build Manager. employs professional strength "makefile" system automatically analyze file dependencies compiler assembler necessary. Project level options control optimization strategies used compiler linker. Syntax errors displayed console window. Double click error message show offending line source code. When correct, linker builds file image suitable programming. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single step, run-to-breakpoint, watch variable features, Debugger provides large trace buffer. This enables define complex breakpoint events such monitoring address data values, memory locations, external signals.
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Document Conventions Acronyms Used
following table lists acronyms that used this document.
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Acronym GPIO PPOR PSoC® SLIMO SRAM Description alternating current application programming interface central processing unit direct current general purpose graphical user interface in-circuit emulator internal speed oscillator internal main oscillator input output least significant voltage detect most significant power reset precision power reset Programmable System-on-Chipslow static random access memory Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (For example, 01010100b 01000011b). Numbers indicated `h', `b', decimals.
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Pinouts
This section describes, lists, illustrates CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC device pins pinout configurations. CY8C20x34 PSoC device available variety packages that listed shown following tables. Every port (labeled with "P") capable Digital connection common analog bus. However, Vss, Vdd, XRES capable Digital
16-Pin Part Pinout
Figure CY8C20234 16-Pin PSoC Device
P0[1], P0[3], P0[7],
P2[5] P2[1] SCL, P1[7] P1[5]
CLK, SCL, MOSI P1[1]
Table 16-Pin Part Pinout (QFN[2]) Type Name Description Digital Analog P2[5] P2[1] P1[7] SCL, P1[5] SDA, MISO. P1[3] CLK. P1[1] CLK[1], SCL, MOSI. Power Ground connection. P1[0] DATA[1], SDA. P1[2] P1[4] Optional external clock input (EXTCLK). Input XRES Active high external reset with internal pull down. P0[4] Power Supply voltage. P0[7] P0[3] Integrating input. P0[1] Analog, Input, Output, High Output Drive
Notes These ISSP pins, that High (Power Reset). PSoC Mixed Signal Array Technical Reference Manual details. center package connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, electrically floated connected other signal.
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DATA, SDA, P1[0]
CLK, P1[3]
P0[4], XRES P1[4], EXTCLK P1[2],
(Top View
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24-Pin Part Pinout
Figure CY8C20334 24-Pin PSoC Device
P0[1], P0[3], P0[5], P0[7], P0[6], EXTCLK, P1[4] P0[4], P0[2], P0[0], P2[0], XRES P1[6],
Table 24-Pin Part Pinout (QFN [2]) Digital Type Analog Name Description
P2[5] P2[3] P2[1] P1[7] SCL, P1[5] SDA, MISO. P1[3] CLK. P1[1] CLK[1], SCL, MOSI. connection. Power Ground connection. P1[0] DATA[1], SDA. P1[2] P1[4] Optional external clock input (EXTCLK). P1[6] Input XRES Active high external reset with internal pull down. P2[0] P0[0] P0[2] P0[4] P0[6] Analog bypass. Power Supply voltage. P0[7] P0[5] P0[3] Integrating input. P0[1] Power Center connected ground. Analog, Input, Output, High Output Drive
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DATA*, SDA, P1[0] P1[2]
CLK*, MOSI, P1[1]
SCL, SDA, MISO, CLK,
P2[5] P2[3] P2[1] P1[7] P1[5] P1[3]
(Top View)
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28-Pin Part Pinout
Figure CY8C20534 28-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] M,P2[7] M,P2[5] P2[3] P2[1] M,I2C SCL,P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL,P1[1]
SSOP
P0[6], P0[4], P0[2], P0[0], P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA,
Table 28-Pin Part Pinout (SSOP Type Name Description Digital Analog P0[7] Analog column input. P0[5] Analog column input column output. P0[3] Analog column input column output, integrating input. P0[1] Analog column input, integrating input. P2[7] P2[5] P2[3] Direct switched capacitor block input. P2[1] Direct switched capacitor block input. Power Ground connection. P1[7] Serial Clock (SCL). P1[5] Serial Data (SDA). P1[3] P1[1] Serial Clock (SCL), ISSP-SCLK[1]. Power Ground connection. P1[0] Serial Data (SDA), ISSP-SDATA[1]. P1[2] P1[4] Optional External Clock Input (EXTCLK). P1[6] Input XRES Active high external reset with internal pull down. P2[0] Direct switched capacitor block input. P2[2] Direct switched capacitor block input. P2[4] P2[6] P0[0] Analog column input. P0[2] Analog column input. P0[4] Analog column input P0[6] Analog column input. Power Supply voltage. Analog, Input, Output, High Output Drive. Document Number: 001-05356 Rev. Page
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32-Pin Part Pinout
Figure CY8C20434 32-Pin PSoC Device
P0[3], P0[7], P0[6], P0[4], P0[5], P0[2],
SDA, MISO, P1[5] CLK, P1[3]
DATA*, SDA, P1[0]
CLK*, SCL, MOSI, P1[1]
EXTCLK, P1[4]
P1[2]
Table 32-Pin Part Pinout (QFN [2]) Digital Power Input Type Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description
P1[6]
XRES
SCL, SDA, MISO. CLK. CLK[1], SCL, MOSI. Ground connection. DATA[1], SDA. Optional external clock input (EXTCLK). Active high external reset with internal pull down.
Analog bypass.
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Table 32-Pin Part Pinout (QFN [2]) (continued) Power Supply voltage. P0[7] P0[5] P0[3] Integrating input. Power Ground connection. Power Center connected ground. Analog, Input, Output, High Output Drive.
48-Pin Part Pinout
48-Pin part table diagram CY8C20000 On-Chip Debug (OCD) PSoC device. This part only used in-circuit debugging. available production. Figure CY8C20000 PSoC Device
P0[3], P0[5], P0[7], P0[6], OCDO OCDE
HCLK
CLK*, SCL, MOSI, P1[1]
CLK, P1[3]
P1[2]
Table 48-Pin Part Pinout (QFN [2]) Digital Analog P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] SCL, SDA, MISO. Page Name connection. Description
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DATA*, SDA, P1[0]
CCLK
P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] SCL, P1[7] SDA, MISO, P1[5]
P0[4], P0[2], P0[0], P2[6], P2[4], P2[2], P2[0], P3[2], P3[0], XRES P1[6], P1[4], EXTCLK,
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Table 48-Pin Part Pinout (QFN [2]) (continued) Power Power Power Input Power Digital Analog P1[3] P1[1] CCLK HCLK P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[6] OCDO OCDE P0[7] P0[5] P0[3] Integrating input. Ground connection. connection. Center connected ground. connection. connection. connection. Analog bypass. Supply voltage. data output. even data Active high external reset with internal pull down. connection. connection. connection. Optional external clock input (EXTCLK). Name P0[1] connection. connection. connection. connection. CLK. CLK[1], SCL, MOSI. Ground connection. clock output. high speed clock output. DATA[1], SDA. Description
Analog, Input, Output, Connection High Output Drive.
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Electrical Specifications
This section presents electrical specifications CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC devices. latest electrical specifications, check most recent datasheet visiting http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC specified, except where mentioned. Refer Table page electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure Voltage versus Frequency Frequency Trim Options
5.25
5.25
SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0
4.75 Voltage 4.75 Voltage
rati
3.60
SLIMO SLIMO Mode=1 Mode=0
3.00 2.70 2.40
3.00 2.70 2.40
SLIMO Mode=1
SLIMO Mode=0
Frequency
Frequency
Table lists units measure that used this section. Table Units Measure Kbit Vrms
Symbol Unit Measure Symbol Unit Measure
degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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Absolute Maximum Ratings
Table Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100
Units
Notes Higher storage temperatures reduces data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrades reliability.
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch Current
-0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units
Notes temperature rise from ambient junction package specific. Table page user must limit power consumption comply with this requirement.
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Electrical Characteristics
Chip Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Chip Level Specifications Symbol IDD12 IDD6 ISB27 Description Supply Voltage Supply Current, Supply Current, Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Slow Oscillator Active. Temperature Range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Slow Oscillator Active. 2.40 5.25 Units Notes Table page Conditions 3.0V, 25oC, MHz. Conditions 3.0V, 25oC, MHz. 2.55V, 40oC. 3.3V, -40oC 85oC.
General Purpose Specifications
Unless otherwise noted, Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V GPIO Specifications Symbol Description Pull Resistor VOH1 High Output Voltage Port Pins VOH2 High Output Voltage Port Pins VOH3 High Output Voltage Port Pins with Regulator Disabled VOH4 High Output Voltage Port Pins with Regulator Disabled VOH5 High Output Voltage Port Pins with 3.0V Regulator Enabled VOH6 High Output Voltage Port Pins with 3.0V Regulator Enabled VOH7 High Output Voltage Port Pins with 2.4V Regulator Enabled VOH8 High Output Voltage Port Pins with 2.4V Regulator Enabled VOH9 High Output Voltage Port Pins with 1.8V Regulator Enabled 2.75 1.95 Units Notes 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.1V, maximum sourcing 3.1V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V 3.6V. 85oC. Maximum source current IOs.
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Table 3.3V GPIO Specifications (continued) VOH10 High Output Voltage Port Pins with 1.8V Regulator Enabled 3.0V 3.6V. 85oC. Maximum source current IOs. 3.0V, maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]). 3.6V 5.25V. 3.6V 5.25V. Gross tested Package dependent Temperature 25oC. Package dependent Temperature 25oC.
Output Voltage
0.75
COUT
Input Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Table 2.7V GPIO Specifications Symbol VOH1 VOH2 Description Pull Resistor High Output Voltage Port Pins with Regulator Disabled High Output Voltage Port Pins with Regulator Disabled Output Voltage 0.75 Units Notes maximum source current IOs. maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]). IOL=5 Maximum sink current even port pins (for example, P0[2] P3[4]) sink current port pins (for example, P0[3] P2[5]). 2.4V 3.6V. 2.4V 3.6V. 2.4V 2.7V. 2.7V 3.6V. Gross tested Package dependent Temperature 25oC. Package dependent Temperature 25oC.
VOLP1
Output Voltage Port Pins
VIH1 VIH2 COUT
Input Voltage Input High Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
0.75
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Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Analog Specifications Symbol Description Switch Resistance Common Analog Units Notes 2.7V 2.4V 2.7V
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C. These design guidance only. Table Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Units Notes
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.39 2.54 2.75 2.85 2.96 4.52 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 4.73 2.40 2.65 2.95 2.51[3] 2.78[4] 2.99[5] 3.09 3.20 4.83 Units Notes greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
Notes Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply.
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Programming Specifications Symbol Description VddIWRITE Supply Voltage Flash Write Operations IDDP Supply Current During Programming Verify VILP Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[6] FlashDR Flash Data Retention 2.70 -1.0 50,000 1,800,0 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles).
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Electrical Characteristics
Chip Level Specifications Table Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V Chip-Level Specifications Symbol FCPU1 F32K1 FIMO12 Description Frequency (3.3V Nominal) 0.75 Internal Speed Oscillator Frequency Internal Main Oscillator Stability 11.4 (Commercial Temperature)[7] Internal Main Oscillator Stability (Commercial Temperature) Duty Cycle Supply Ramp Time External Reset Pulse Width 5.70 12.6 12.6 Units Notes only SLIMO Mode Trimmed 3.3V operation using factory trim values. Figure 2-1b, SLIMO Mode Trimmed 3.3V operation using factory trim values. Figure 2-1b, SLIMO Mode
FIMO6
6.30
DCIMO TRAMP TXRST
Table 2.7V Chip Level Specifications Symbol FCPU1 F32K1 FIMO12 Description Frequency (2.7V Nominal) Internal Speed Oscillator Frequency Internal Main Oscillator Stability (Commercial Temperature)[7] Internal Main Oscillator Stability (Commercial Temperature) Duty Cycle Supply Ramp Time External Reset Pulse Width 0.75 11.0 3.25 12.9 Units Notes
FIMO6
5.60
6.40
Trimmed 2.7V operation using factory trim values. Figure 2-1b, SLIMO Mode Trimmed 2.7V operation using factory trim values. Figure 2-1b, SLIMO Mode
DCIMO TRAMP TXRST
Table 2.7V Chip Level Specifications Symbol FCPU1 F32K1 FIMO12 Description Frequency (2.7V Minimum) 0.75 Internal Speed Oscillator Frequency Internal Main Oscillator Stability 11.0 (Commercial Temperature)[7] 12.9 Units Notes
Trimmed 2.7V operation using factory trim values. Figure 2-1b, SLIMO Mode
Note ambient,
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Table 2.7V Chip Level Specifications (continued) Symbol FIMO6 Description Internal Main Oscillator Stability (Commercial Temperature) Duty Cycle Supply Ramp Time External Reset Pulse Width 5.60 6.40 Units Notes Trimmed 2.7V operation using factory trim values. Figure 2-1b, SLIMO Mode
DCIMO TRAMP TXRST
General Purpose Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V GPIO Specifications Symbol Description FGPIO GPIO Operating Frequency TRise023 Rise Time, Strong Mode, Cload Ports TRise1 Rise Time, Strong Mode, Cload Port TFall Fall Time, Strong Mode, Cload Ports Units Notes Normal Strong Mode, Port 3.6V 4.75V 5.25V, 3.6V, 3.6V 4.75V 5.25V,
Table 2.7V GPIO Specifications Symbol Description FGPIO GPIO Operating Frequency TRise023 Rise Time, Strong Mode, Cload Ports TRise1 Rise Time, Strong Mode, Cload Port TFall Fall Time, Strong Mode, Cload Ports Units Notes Normal Strong Mode, Port 3.0V, 3.0V, 3.0V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRise023 TRise1
TFall
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Comparator Amplifier Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Operational Amplifier Specifications Symbol TCOMP Description Comparator Response Time, Overdrive Units Notes 3.0V. 2.4V 3.0V.
Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Analog Specifications
Symbol Switch Rate Description 3.17 Units Notes
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C. These design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC.
External Clock Specifications Table Table Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.750 12.6 5300 Units Notes
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Table 3.3V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.750 12.6 Units Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements.
High Period with Clock divide Period with Clock divide Power Switch
41.7 41.7
5300
Table 2.7V (Nominal) External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.750 3.080 Units Notes Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.15
6.35
High Period with Clock divide Period with Clock divide Power Switch
5300
Table 2.7V (Minimum) External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.750 6.30 Units Notes Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.15
12.6
High Period with Clock divide Period with Clock divide Power Switch
5300
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units Notes
Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V Specifications Symbol FSPIM FSPIS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width Negated Between Transmissions 2.05 Units Notes Output clock frequency half input clock rate
Table 2.7V Specifications Symbol FSPIM FSPIS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width Negated Between Transmissions 3.15 1.025 Units Notes Output clock frequency half input clock rate
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Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard Mode Fast Mode Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time 100[8] Setup Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter Description Units Notes
Note Fast Mode device used Standard Mode system requirement tSU; met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU; 1000 1250 (according Standard Mode specification) before line released.
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Table 2.7V Characteristics Pins (Fast Mode Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard Mode Fast Mode Clock Frequency. Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock. HIGH Period Clock Setup Time Repeated START Condition. Data Hold Time. Data Setup Time. Setup Time STOP Condition. Free Time Between STOP START Condition. Pulse Width spikes suppressed input filter. Description Units Notes
Figure Definition Timing Fast/Standard Mode
LOWI2C SUDATI2C HDSTAI2C
SPI2C BUFI2C
HDSTAI2C HDDATI2C HIGHI2C SUSTAI2C SUSTOI2C
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Packaging Dimensions
This section illustrates packaging specifications CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC devices along with thermal impedances each package. important note that emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions Figure 16-Pin (3x3 MAX)
001-09116
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Figure 24-Pin (4x4
001-13937
Figure 28-Lead (210-Mil) SSOP
51-85079
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Figure 32-Pin (5x5 0.60 MAX)
001-06392
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Figure 48-Pin (7x7
001-12919
information preferred dimensions mounting packages, following Application Note important note that pinned vias thermal conduction required power 24-, 32-, 48-pin PSoC devices.
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Thermal Impedances
Table Thermal Impedances Package Package QFN[10] SSOP[10] QFN[10] QFN[10] Typical oC/W oC/W oC/W oC/W
line code. Users work directly with application objects such LEDs, switches, sensors, fans. PSoC Express available free charge PSoC Programmer PSoC Programmer flexible enough used bench development also suitable factory programming. PSoC Programmer works either standalone programming application operates directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge CY3202-C iMAGEcraft Compiler CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. available Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page click PSoC (Programmable System-on-Chip) view current list available items.
Solder Reflow Peak Temperature
Table illustrates minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package Minimum Peak Temperature [11] 240oC 240oC 240oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC
SSOP 240oC
Development Kits
development kits sold Cypress Online Store. CY3215-DK Basic Development
Development Tool Selection Software
PSoC DesignerAt core PSoC development software suite PSoC Designer. This used thousands PSoC developers. This robust software facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under DESIGN RESOURCES Software Drivers. PSoC ExpressAs latest addition PSoC development software suite, PSoC Express first visual embedded system design tool that enables user create entire PSoC project generate schematic, BOM, datasheet without writing single
CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface enables users run, halt, single step processor view content specific memory locations. PSoC Designer supports advance emulation features also. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
Notes Power achieve thermal impedance specified package, center thermal soldered ground plane. Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules, more. includes:
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
PSoC Express Software Express Development Board Four Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
Evaluation Tools
evaluation tools sold Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 enables user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Device Programmers
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
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CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production programming environment. Note that CY3207ISSP needs special software compatible with PSoC Programmer. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part Number CY8C20234-12LKXI CY8C20334-12LQXI CY8C20534-12PVXI CY8C20434-12LKXI Third Party Tools Several tools specially designed following third party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards. Package SOIC SSOP Flex-Pod [12] CY3250-20334QFN CY3250-20434QFN Foot [13] CY3250-16QFN-FK CY3250-24QFN-FK CY3250-28SSOP-FK CY3250-32QFN-FK Prototyping Module CY3210-0X34 CY3210-0X34 CY3210-0X34 CY3210-0X34 Adapter [14] AS-24-28-01ML-6 AS-32-28-03ML-6
Build PSoC Emulator into Your Board details emulating circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323"
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
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Ordering Information
Table lists CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC device's package features ordering codes. Table PSoC Device Features Ordering Information Package 16-Pin (3x3 0.60 MAX) 16-Pin (3x3 0.60 MAX) (Tape Reel) 24-Pin (4x4 0.60 MAX) 24-Pin (4x4 0.60 MAX) (Tape Reel) Ordering Code CY8C20234-12LKXI Flash (Bytes) SRAM (Bytes) Digital CapSense Blocks Blocks Digital Pins Analog Inputs
[15]
Analog Outputs
XRES
13[15] 13[15]
CY8C20234-12LKXIT
CY8C20334-12LQXI
20[15] 20[15]
CY8C20334-12LQXIT
28-Pin (210-Mil) SSOP CY8C20534-PVXI 28-Pin (210-Mil) SSOP CY8C20534-PVXIT (Tape Reel) 32-Pin (5x5 0.60 MAX) 32-Pin (5x5 0.60 MAX) (Tape Reel) 48-Pin QFN[16] CY8C20434-12LKXI
28[15] 28[15]
CY8C20434-12LKXIT
CY8C20000-12LFXI
28[15]
Figure Ordering Code Definitions xxx- Package Type: Thermal Rating: PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended Pb-Free LKX/LQX Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
Notes Dual function Digital Pins also connect common analog mux. This part used in-circuit debugging. available production.
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Document History Page
Document Title: CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC® Mixed-Signal Array Document Number: 001-05356 Revision 404571 418513 Orig. Change Description Change silicon document (Revision **). Updated Electrical Specifications, including Storage Temperature Maximum Input Clock Frequency. Updated Features Analog System Overview. Modified 32-pin E-PAD dimensions. Added 32-pin QFN. High Output Drive indicator P1[x] pinouts. Updated trademarks. Made datasheet "Final". Added Development Tool section. Added pinout package diagram. Added 16-pin QFN. Updated 24-pin 32-pin package diagrams 0.60 thickness. Changed from commercial industrial temperature range. Updated Storage Temperature specification notes. Updated thermal resistance data. Added development tool part numbers. Finetuned features electrical specifications. Added CapSense requirement reference. Added Power Comparator (LPC) AC/DC electrical specifications tables. Added 2.7V minimum specifications. Updated figure standards. Updated Technical Training paragraph. Added package clarifications dimensions. Updated ECN-ed Amkor dimensioned package diagram revisions.
490071
788177
1356805
HMT/SFVTMP Updated 24-pin Theta Added External Reset Pulse Width, TXRST, specification. 3/HCL/SFV Fixed 48-pin QFN.vsd. Updated table introduction high output voltage description section two. sentence: "Exceeding maximum ratings shorten battery life device." does apply data sheets. Therefore, word "battery" changed "useful." Took tabs after table figure numbers titles added hard spaces. Updated section, General Purpose Specifications page with text. Updated VOH5 VOH6 say, "High Output Voltage, Port Pins with 3.0V Regulator Enabled." Updated VOH7 VOH8 with text, "maximum source current IOs."Added 28-pin SSOP part, pinout, package. Updated specs. Modified dev. tool part numbers.
Cypress Semiconductor Corporation, 2005-2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
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PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations.Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.All products company names mentioned this document trademarks their respective holders.
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Power CapSense Block Configurable Capacitive Sensing Elements Supports

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