20-, 40-, 60-Bit Expander with EEPROM CY8C95xxA multi-port expand

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20-, 40-, 60-Bit Expander with EEPROM CY8C95xxA multi-port expand

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CY8C9520A, CY8C9540A CY8C9560A
20-, 40-, 60-Bit Expander with EEPROM
CY8C95xxA multi-port expander with board user available EEPROM several outputs. devices this family operate identically differ pins, number PWMs, internal EEPROM size. CY8C95xxA operates slave devices. first device multi port expander (single address access ports through registers). second device serial EEPROM. Dedicated configuration registers used disable EEPROM. EEPROM uses 2-byte addressing support Kbyte EEPROM address space. selected device defined most significant bits address specific register addressing. expander's data pins independently assigned inputs, outputs, quasi-bidirectional input/outputs ouputs. individual data pins configured open drain collector, strong drive source, sink), resistively pulled down, high impedance. factory default configuration pulled internally. system master writes configuration registers through bus. Configuration output register settings storable user defaults dedicated section EEPROM. user defaults were stored EEPROM, they restored ports power While this device share with SMBus devices, only communicate with masters. There dedicated that configured interrupt output (INT) connected interrupt logic system master. This signal inform system master that there incoming data ports that output state changed.
GPort
Cinterface logic electrically compatible with SMBus (CY8C9520A), (CY8C9540A), (CY8C9560A) data pins independently configurable inputs, outputs, bi-directional input/outputs, outputs 4/8/16 sources with 8-bit resolution Extendable Soft Addressingalgorithm allowing flexible I2C-address configuration Internal 3-/11-/27-Kbyte EEPROM User default storage, port settings internal EEPROM Optional EEPROM Write Disable (WD) input Interrupt output indicates input level changes Pulse Width Modulator (PWM) state changes Internal Power Reset (POR) Internal configurable Watchdog timer
Level Block Diagram
EEPROM User Settings Area User Available Area
Clocks
GPort
93.75 Divider (1-255)
GPort
A4-A6 A1-A3,
EEPROM byte readable supports byte-by-byte writing. configured EEPROM Write Disable (WD) input that blocks write operations when high. configuration registers also disable EEPROM operations. CY8C95xxA fixed address (A0) additional pins (A1-A6), which allow devices share common wire data bus. Extendable Soft Addressing algorithm provides option choose number pins needed assign desired address. Pins used address bits available GPIO pins. There (CY8C9520A), (CY8C9540A), (CY8C9560A) independently configurable 8-bit PWMs. These PWMs listed PWM0-PWM15. Each clocked available clock sources. details configure I2C, Application Note "Communication Port Expander with Flash Storage AN2304"
Control Unit
GPort
GPort
Power-on-Reset
Cypress Semiconductor Corporation Document Number: 38-12036 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised August 2007
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CY8C9520A, CY8C9540A CY8C9560A
Architecture
"Top Level Block Diagram" page illustrates device block diagram. main blocks include control unit, PWMs, EEPROM, ports. control unit executes commands received from transfers data between other devices master device. chip EEPROM separated conventionally into regions. first region designed store data available byte wide read/writes through bus. possible prevent write operations setting high. EEPROM operations blocked configuration register settings. second region allows user store port default settings using special commands. These defaults automatically reloaded processed after device power number lines sources listed table Table GPIO Availability Port GPort GPort GPort GPort GPort GPort GPort GPort PWMs CY8C9520A bita bita CY8C9540A 5-8bita 0-4ita CY8C9560A bita bita
Figure Logical Structure Port
GPortx
Drive Mode Registers Output Register
DriveMode Pull-Up
Data
DriveMode High
PWMs
Select
Interrupt Status Input Register Interrupt Mask
Direction
Inversion
This port contains configuration-dependant GPIO lines A1-A6 lines.
There four pins GPort three GPort that used general purpose EEPROM Write Disable (WD) I2C-address input (A1-A6), depending configuration settings. figure titled "Logical Structure Port" shows single port logical structure. Port Drive Mode register gives option select seven available modes each separately: pulled up/down, open drain high/low, strong drive fast/slow, high-impedance. default these configuration registers store values setting pins pulled Invert register allows inversion logic Input registers separately each pin. Select register assigns pins outputs. these configuration registers read/writable using corresponding commands multi-port device.
Port Input Output registers separated. When Output register written, data sent external pins. When Input register read, external logic levels captured transferred. result, read data different from written Output register data. This allows implementation quasi-bidirectional input-output mode, when corresponding binary digit configured pulled up/down output. Each port Interrupt Mask register Interrupt Status register. Each high Interrupt Status register signals that there been change corresponding input line since last read that Interrupt Status register. Interrupt Status register cleared after each read. Interrupt Mask register enables/disables activation line when input levels changed. Each high Interrupt Mask register masks (disables) interrupt generated from corresponding input line.
Applications
Each GPIO used monitor control various board level devices, including LEDs system intrusion detection devices. board EEPROM used store information such error codes board manufacturing data read-back application software diagnostic purposes.
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Device Access Addressing
Following start condition, master device sends byte address slave. This address accesses device CY8C95xx. default there possible address formats binary representation: 010000A0X 101000A0X. first used access multi port device second access EEPROM. additional address lines (A1-A6) used then Device Addressing. Table defines device addresses. This addressing method uses technique called Extendable Soft AddressingTM, described "Extendable Soft AddressingTM" page Table Device Addressing Multi-Port Device
EEPROM write sequence. available EEPROM space reached, then further writes responded with NAK. Refer Figure "Memory Reading Writing," page which illustrates memory reading writing procedures EEPROM device.
Multi Port Device
This device allows user configurations operations through internal registers. Each data transfer preceded command byte. This byte used pointer register that receives transmits data. Available registers listed Table "The Device Register Address Map," page
EEPROM Device
Document Conventions
Acronyms
Table lists acronyms that used this document. Table Acronyms Acronym EEPROM GPIO direct current electrically erasable programmable read-only memory (E2) general purpose input/output most-significant power reset pulse width modulator Description alternating current
When address lines A1-A6 used, device being accessed defined first byte following address write transaction. most significant (MSb) this byte `0', this byte treated command (register address) byte multi-port device. `1', this byte first 2-byte EEPROM address. this case, device masks determine EEPROM address.
Serial EEPROM Device
EEPROM reading writing operations require bytes, ALO, which indicate memory address use. read more bytes, master device addresses unit with write cycle send followed ALO, readdresses unit with read cycle reads more data bytes. Each data byte read increments internal address counter EEPROM address space. read write beyond EEPROM address space must result response Port Expander. write data EEPROM, master device performs write cycle, with first bytes being followed ALO. This followed more data bytes. case block writing advisable starting address beginning 64-byte boundary, example 01C0h 0080h, this mandatory. When 64-byte boundary crossed EEPROM, clock stretched while device performs
Units Measure
units measure table located Electrical Specifications section. Table "Units Measure," page lists abbreviations used Section
Numeric Naming
Hexidecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexidecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (e.g., 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
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Pinouts
CY8C95xxA device available variety packages, which listed illustrated following tables.
28-Pin Part Pinout
Table 28-Pin Part Pinout (SSOP)
Name GPort0_Bit0_PWM3 GPort0_Bit1_PWM1 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM3 GPort0_Bit5_PWM1 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 Serial Clock (SCL) Serial Data (SDA) GPort2_Bit3_PWM3/A1 GPort2_Bit2_PWM0/WD GPort2_Bit1_PWM0/A2 GPort2_Bit0_PWM2/A3 XRES GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM0/A6 GPort1_Bit4_PWM2 GPort1_Bit3_PWM0 GPort1_Bit2_PWM2 GPort1_Bit1_PWM0 GPort1_Bit0_PWM2 Description Port Port Port Port Port Port Port Port Ground connection. Clock. Data. Port Address Address Ground connection. Port Write Disable. Port Address Port Address Active high external reset with internal pull down. Port Address Port Address Port Address Port Port Port Port Port Supply voltage.
Figure CY8C9520A 28-Pin Device
GPort0_Bit0_PWM3 GPort0_Bit1_PWM1 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM3 GPort0_Bit5_PWM1 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 Serial Clock (SCL) Serial Clock (SDA) GPort2_Bit3_PWM3/A1
SSOP
GPort1_Bit0_PWM2 GPort1_Bit1_PWM0 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 GPort1_Bit4_PWM2 GPort1_Bit5_PWM0/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 XRES GPort2_Bit0_PWM2/A3 GPort2_Bit1_PWM0/A2 GPort2_Bit2_PWM0/WD
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48-Pin Part Pinout
Table 48-Pin Part Pinout (SSOP)
Name GPort0_Bit0_PWM7 GPort0_Bit1_PWM5 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 GPort3_Bit4_PWM7 GPort3_Bit5_PWM5 GPort3_Bit6_PWM3 GPort3_Bit7_PWM1 GPort5_Bit2_PWM3 GPort5_Bit3_PWM1 Serial Clock (SCL) Serial Data (SDA) GPort2_Bit3_PWM3/A1 GPort2_Bit2_PWM0/WD GPort2_Bit1_PWM4/A2 GPort2_Bit0_PWM6/A3 GPort5_Bit1_PWM0 GPort5_Bit0_PWM2 GPort4_Bit7_PWM0 GPort4_Bit6_PWM2 GPort4_Bit5_PWM4 GPort4_Bit4_PWM6 XRES GPort4_Bit3_PWM0 GPort4_Bit2_PWM2 GPort4_Bit1_PWM4 GPort4_Bit0_PWM6 GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM4/A6 GPort1_Bit4_PWM6 GPort1_Bit3_PWM0 GPort1_Bit2_PWM2 GPort1_Bit1_PWM4 GPort1_Bit0_PWM6 Description Port Port Port Port Port Port Port Port Port Port Port Port Ground connection. Port Port Port Port Port Port Clock. Data. Port Address Address Ground connection. Port Write Disable. Port Address Port Address Port Port Port Port Port Port Active high external reset with internal pull down. Port Port Port Port Port Address Port Address Port Address Port Port Port Port Port Supply voltage.
Figure CY8C9540A 48-Pin Device
GPort0_Bit0_PWM7 GPort0_Bit1_PWM5 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 GPort3_Bit4_PWM7 GPort3_Bit5_PWM5 GPort3_Bit6_PWM3 GPort3_Bit7_PWM1 GPort5_Bit2_PWM3 GPort5_Bit3_PWM1 Serial Clock (SCL) Serial Data (SDA) GPort2_Bit3_PWM3/A1
SSOP
GPort1_Bit0_PWM6 GPort1_Bit1_PWM4 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 GPort1_Bit4_PWM6 GPort1_Bit5_PWM4/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 GPort4_Bit0_PWM6 GPort4_Bit1_PWM4 GPort4_Bit2_PWM2 GPort4_Bit3_PWM0 XRES GPort4_Bit4_PWM6 GPort4_Bit5_PWM4 GPort4_Bit6_PWM2 GPort4_Bit7_PWM0 GPort5_Bit0_PWM2 GPort5_Bit1_PWM0 GPort2_Bit0_PWM6/A3 GPort2_Bit1_PWM4/A2 GPort2_Bit2_PWM0/WD
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100-Pin Part Pinout
Table 100-Pin Part Pinout (TQFP)
Name Description Name Description
GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 GPort3_Bit4_PWM15 GPort3_Bit5_PWM13 GPort3_Bit6_PWM11 GPort3_Bit7_PWM9 GPort5_Bit7_PWM15 GPort5_Bit6_PWM13 GPort5_Bit2_PWM11 GPort5_Bit3_PWM9 Serial Clock (SCL) Serial Data (SDA) GPort2_Bit3_PWM11/A1 GPort7_Bit7_PWM15 GPort7_Bit6_PWM14 GPort7_Bit5_PWM13 GPort7_Bit4_PWM12 GPort7_Bit3_PWM11 GPort7_Bit2_PWM10 GPort7_Bit1_PWM9 GPort7_Bit0_PWM8 GPort2_Bit2_PWM8/WD GPort2_Bit1_PWM12/A2 GPort2_Bit0_PWM14/A3
Use; leave floating. Use; leave floating. Port Port Port Port Port Port Port Port Port Use; leave floating. Use; leave floating. Use; leave floating. Ground connection. Port Port Port Port Port Port Port Port Clock. Use; leave floating. Use; leave floating. Use; leave floating. Data. Port Address Address Use; leave floating. Supply voltage. Use; leave floating. Ground connection. Use; leave floating. Port Port Port Port Port Port Port Port Port Write Disable. Port Address Port Address Use; leave floating. Use; leave floating. Use; leave floating.
GPort5_Bit1_PWM8 GPort5_Bit0_PWM10 GPort5_Bit4_PWM12 GPort5_Bit5_PWM14 GPort4_Bit7_PWM8 GPort4_Bit6_PWM10 GPort4_Bit5_PWM12 GPort4_Bit4_PWM14 XRES GPort4_Bit3_PWM0 GPort4_Bit2_PWM2 GPort4_Bit1_PWM4 GPort4_Bit0_PWM6 GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM4/A6 GPort1_Bit4_PWM6 GPort1_Bit3_PWM0 GPort1_Bit2_PWM2 GPort1_Bit1_PWM4 GPort1_Bit0_PWM6 GPort6_Bit0_PWM0 GPort6_Bit1_PWM1 GPort6_Bit2_PWM2 GPort6_Bit3_PWM3 GPort6_Bit4_PWM4 GPort6_Bit5_PWM5 GPort6_Bit6_PWM6 GPort6_Bit7_PWM7 GPort0_Bit0_PWM7 GPort0_Bit1_PWM5 GPort0_Bit2_PWM3
Use; leave floating. Port Port Port Port Port Port Port Port Use; leave floating. Use; leave floating. Active high external reset with internal pull down. Port Port Ground connection. Port Port Port Address Port Address Port Address Use; leave floating. Port Use; leave floating. Port Use; leave floating. Use; leave floating. Port Use; leave floating. Port Use; leave floating. Port Supply voltage. Supply voltage. Ground connection. Ground connection. Port Port Port Port Port Port Port Port Use; leave floating. Port Use; leave floating. Port Use; leave floating. Port Use; leave floating.
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Figure CY8C9560A 100-Pin Device
GPort0_Bit2_PWM3 GPort0_Bit1_PWM5 GPort0_Bit0_PWM7 GPort6_Bit7_PWM7 GPort6_Bit6_PWM6 GPort6_Bit5_PWM5 GPort6_Bit4_PWM4 GPort6_Bit3_PWM3 GPort6_Bit2_PWM2 GPort6_Bit1_PWM1 GPort6_Bit0_PWM0 GPort1_Bit0_PWM6 GPort1_Bit1_PWM4 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 GPort1_Bit4_PWM6 GPort1_Bit5_PWM4/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 GPort4_Bit0_PWM6 GPort4_Bit1_PWM4 GPort4_Bit2_PWM2 GPort4_Bit3_PWM0 XRES GPort4_Bit4_PWM14 GPort4_Bit5_PWM12 GPort4_Bit6_PWM10 GPort4_Bit7_PWM8 GPort5_Bit5_PWM14 GPort5_Bit4_PWM12 GPort5_Bit0_PWM10 GPort5_Bit1_PWM8
Serial Data (SDA) GPort2_Bit3_PWM11/A1
Use; leave floating.
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GPort7_Bit7_PWM15 GPort7_Bit6_PWM14 GPort7_Bit5_PWM13 GPort7_Bit4_PWM12 GPort7_Bit3_PWM11 GPort7_Bit2_PWM10 GPort7_Bit1_PWM9 GPort7_Bit0_PWM8 GPort2_Bit2_PWM8/WD GPort2_Bit1_PWM12/A2 GPort2_Bit0_PWM14/A3
DNUa GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 GPort3_Bit4_PWM15 GPort3_Bit5_PWM13 GPort3_Bit6_PWM11 GPort3_Bit7_PWM9 GPort5_Bit7_PWM15 GPort5_Bit6_PWM13 GPort5_Bit2_PWM11 GPort5_Bit3_PWM9 Serial Clock (SCL)
TQFP
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Descriptions
Extendable Soft Addressingline defines corresponding address. This must pulled down. strong pull strong pull down (wired through less resistor Vss), then that only address line being specified A1-A6 lines used GPIO. weak pull weak pull down (connected through 75K- 200K resistor), then only externally defined address bit. There assigned needed. This pulled pulled down strong weak with resistor. with type pull determines whether address last externally defined address bit. Differently from dedicated address pin. only used only address externally defined. There also predefined pins that only used addressing needed. last address chain pulled strong. That way, only number pins needed assign address desired part allocated address pins, pins used address bits used GPIO pins. Table "Device Addressing," page defines resulting device address.
Working with PWMs
There four independent PWMs CY8C9520A, eight CY8C9540A sixteen CY8C9560A. Each configured output writing corresponding Select register (see Table "Output Select Registers Logic," page 11). next step configuration clock source selection using Config registers. There available clock sources: (default), MHz, MHz, 93.75 kHz, 367.6 previous output. (see Figure Figure Clock Sources
93.75 Divider (1-255) 367.6 93.75
Interrupt (INT)
interrupt output enabled) activated these events occurs:
default, selected clock. Period registers used output period:
GPIO port pins changes state corresponding Interrupt Mask register low. When driven slowest clock source (367.6 assigned changes state pin's corresponding Interrupt Mask register low.
Period
Allowed values between FFh. Pulse Width register sets duration output pulse. Allowed values between zero (Period-1) value. duty cycle ratio computed using thsi equation:
interrupt line deactivated when master device performs read from corresponding Interrupt Status register.
Write Disable (WD)
this feature enabled, allows writes EEPROM blocks memory writes. This checked immediately before performing write memory. Enable register (EEPROM disabled) EERO (EEPROM read-only) then line level ignored. Note that this line blocks commands that perform operations with EEPROM (see Table "Available Commands," page 13). This line enabled/disabled Enable register (2Dh): enables function, disables.
DutyCycle PulseWidth -Period
External Reset (XRES)
full device reset caused pulling XRES high. XRES always-on pull down resistor, does require external pull down operation. tied directly ground left open. Behavior after XRES similar POR.
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Figure Memory Reading Writing
Slave Address Memory Address
Start High(Addr) Low(Addr)
data(Addr) data(Addr+1)
Stop
from Slave
from Slave
from Slave
from Slave
from Master
from Master
from Master
Reading from EEPROM
Slave Address
Memory Address
Address Space
Start High(Addr) Low(Addr) data data
Stop
from Slave
from Slave
from Slave current address crosses 64-byte block boundary, then device performs real writing EEPROM
Writing EEPROM
Figure Port Reading Writing Multi-Port Device
Slave Address Register Address Reading from GPort this moment, device performs reading from GPort Start data from GPort1 data from GPort Stop
from Slave
from Slave
from Master
from Master
Reading from GPort
Slave Address
Register Address this moment, device performs output GPort
Output GPort
Output GPort
Stop data from GPort1 data from GPort data from GPort from Slave
Start
from Slave
from Slave
from Slave
Writing from GPort
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Register Mapping Table
register address auto-incrementing. master device writes reads data from register then continues data transfer same transaction, sequential bytes written read from following registers. example, first byte sent Output Port register, then next bytes written Output Port Output Port Output Port etc. first byte each write transaction treated register address. read data from seires registers, master device must write starting register address byte then perform start series read transactions. address sent, reads start from address read specific register address, master device must write register address byte, then perform start read transaction. Figure "Port Reading Writing Multi-Port Device," page device's register mapping listed Table Table Device Register Address Address Register Input Port Input Port Input Port Input Port Input Port Input Port Input Port Input Port Output Port Output Port Output Port Output Port Output Port Output Port Output Port Output Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Interrupt Status Port Port Select Default Register Value None None None None None None None None
Table Device Register Address (continued) Address Register Interrupt Mask Inversion Direction Input/Output Drive Mode Pull Drive Mode Pull Down Drive Mode Open Drain High Drive Mode Open Drain Drive Mode Strong Drive Mode Slow Strong Drive Mode High-Z Reserved Reserved Reserved Reserved Select Config Period Pulse Width Programmable Divider Enable WDE, EEE, EERO Device ID/Status Watchdog Command Default Register Value None None None None 20h/40h/60h
Select Port Output
Register Descriptions
registers CY8C95xx described sections that follow. Note that registers located addresses 2Bh.
Input Port Registers (00h 07h)
These registers represent actual logical levels pins used port reading operations. They read only. Inversion registers changes state reads these ports.
Output Port Registers (08h 0Fh)
These registers used writing data GPIO ports. default, ports pull mode allowing quasi-bidirectional allow input operations without reconfiguration, these registers have store '1's. Output register data also affects states when PWMs enabled. Table Output Select Registers Logic details.
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Figure page illustrates port read/write procedures. Inversion registers have effect these ports.
Input registers' logic presented Table These registers have effect outputs PWMs. Table Inversion Register Logic State Invert Input
Int. Status Port Registers (10h 17h)
Each these registers signals that there change corresponding input line since last read that Interrupt Status register. Each Interrupt (Int.) Status register cleared only after read that register. assigned pin, then state changes sets corresponding Interrupt Status register. pin's interrupt mask cleared slowest possible rate allowed (driven programmable clock source with divide register FFh), then line also drives state change.
Port Direction Register (1Ch)
Each port configurable either input output. perform this configuration, Port Direction register (1Ch) used GPort selected Port Select register (18h). this register (written with '1'), corresponding port enabled input. this register cleared (written with '0'), corresponding port enabled output.
Port Select Register (18h)
This register configures GPort. Write value this register select port program with registers 19h-23h.
Interrupt Mask Port Register (19h)
Interrupt Mask register enables disables activation line when GPIO input levels changed. Each Interrupt Mask register masks (disables) interrupts generated from corresponding input line GPort selected Port Select register (18h).
Drive Mode Registers (1Dh-23h)
Each port's data pins separately seven available modes: pull down, open drain high/low, strong drive fast/slow, high-impedance input. perform this configuration, seven drive mode registers used GPort selected Port Select register (18h). Each written this register changes corresponding line drive mode. Registers through have last register priority meaning that high which last register written overrides those that came before. Reading these registers reflects actual setting, what originally written. Table Drive Mode Register Settings Reg. State Resistive Pull Description Resistive High, Strong (default) Slow Strong High, High Slow Strong Low, High High Strong High, Strong Low, Fast Output Mode Strong High, Strong Low, Slow Output Mode High
Select Register (1Ah)
This register allows each port output. default, ports configured GPIO lines. Each this register connects corresponding GPort selected Port Select register (18h) output. Output register data also affects state when enabled. Table Note that used output must configured appropriate drive mode. Table page more information. Table describes logic Output Select registers. Table Output Select Registers Logic Output Select State Current
Resistive Pull Down Strong High, Resistive Open Drain High Open Drain Strong Drive Slow Strong Drive High Impedance
Inversion Register (1Bh)
This register invert logic input ports. Each written this register inverts logic corresponding Input register GPort selected Port Select register (18h).
Select Register (28h)
This register configures PWM. Write value 00h-0Fh this register select program with registers 29h-2Bh.
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Config (29h)
This register selects clock source selected Select register (28h) interrupt logic. There available clock sources: (default), MHz, MHz, 93.75 kHz, 367.6 previous output. 367.6 clock user programmable. divides 93.75 clock source divisor stored Divider register (2Ch). default divide ratio 255. (see Table details). default, PWMs clocked from kHz. Table Clock Sources Config xxxxx000b xxxxx001b xxxxx010b xxxxx011b xxxxx100b xxxxx101b 93.75 367.6 (programmable) Previous Clock Source (default)
Divider Register (2Ch)
This register sets frequency output programmable divider:
Frequency
93.75 Divider
Allowed values between 255.
Enable Register (2Dh)
configures write disable operate either GPIO also enables/disables EEPROM operations (EEE bit) makes EEPROM read-only (EERO bit). assignments shown Table page Table Enable Register Function Default EERO
Reserved Reserved
Each generate interrupt rising falling edge output pulse. There limitation clock source generate interrupt. Only slowest speed source (programmed 367.6 with divider equal allows interrupt generation. Consequently, create interrupt, necessary choose programmable divider output clock source (write xxxxx100b Config register (29h)), write Divide register (2Ch), select output (1Ah). Interrupt status reflected Interrupt Status registers (10h-17h) cause line activation enabled corresponding mask Interrupt Mask register:
Each enables corresponding feature, disables. Writes this register differ from other registers. write sequence modify Enable register follows: Send device address with Send register address 2Dh. Send unlock sequence three bytes: 43h, 4Dh, 53h; ('C', 'M', ASCII bytes). Send Enable register value. This write sequence secures register from accidental changes. register read without unlock key. default, EERO EEPROM (EEE bit) disabled line (WDE bit) GPIO disabled).
Period Register (2Ah)
Table Period Register Config xxxx0xxxb xxxx1xxxb Interrupt Falling pulse edge (default) Rising pulse edge
When performing burst write operation that crosses this register, data written this register ignored address increments 2Eh.
Device ID/Status Register (2Eh)
This register sets period counter. Allowed values between FFh. effective output waveform period
tOUT Period tCLK
Pulse Width Register (2Bh)
This register sets pulse width output. Allowed values between zero (Period value. duty cycle ratio computed using following equation:
This register stores device identifiers (2xh/4xh/6xh) reflects which settings were loaded during startup, either factory defaults (FD) user defaults (UD). default during startup, device attempts load user default block. corrupted then factory defaults loaded nibble this register high inform which active. high nibble always equal CY8C9520A, CY8C9540A, CY8C9560A. This register read-only. Table Device Status Register Reserved FD/UD
DutyCycle
PulseWidth Period
Function Device Family 4,or
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Write Defaults (03h)
This command sends power defaults CY8C95xx without changing current settings unless command issued afterwards. This command followed data bytes according Table calculated data bytes (00h-91h). check fails incomplete block sent, then slave responds with data does saved EEPROM. define defaults user must:
Watchdog Register (2Fh)
This register controls internal Watchdog timer. This timer trigger device reset device responding requests misconfiguration. Device operation affected when Watchdog register master writes zero value Watchdog register, countdown mechanism activated each second register decremented. Upon transition from device rebooted, which restores user defaults. After reboot, Watchdog register value reset zero. transaction (addressing Expander) resets Watchdog register previously stored value. device reboot (caused Watchdog) sets Watchdog register zero (turns Watchdog feature). Watchdog timer disabled writing zero Watchdog register (2Fh) using Reconfigure Device (07h). Note Watchdog timer intended track precise time intervals. timer's frequency vary range between -50% +100%. This variation must taken into account when selecting appropriate value Watchdog register.
Write command Write data bytes with values registers Write byte calculated previous data bytes.
Content data block described Table Table Defaults Data Structure Offset Output Port Interrupt mask Port Select Port Inversion Port Direction Port Resistive pull Drive Mode Port Resistive pull down Drive Mode Port Open drain high Drive Mode Port Open drain Drive Mode Port Strong drive Drive Mode Port Slow strong drive Drive Mode Port High impedance Drive Mode Port Drive Modes Port Drive Modes Port Drive Modes Port Drive Modes Port Drive Modes Port Drive Modes Port Drive Modes Port Config setting PWM0 Period setting PWM0 Pulse Width setting PWM0 PWM1 settings PWM15 settings Divider Enable Value
Command Register (30h)
This register sends commands device, including current configuration defaults, restore factory defaults, define defaults, read defaults, write device configuration, read device configuration, reconfigure device with stored defaults. command presented Table Note Registers restored parallel. assume particular order restoration process. Table Available Commands Command Description Store device configuration EEPROM defaults Restore Factory Defaults Write EEPROM defaults Read EEPROM defaults Write device configuration Read device configuration Reconfigure device with stored defaults
Commands Description
Store Config Defaults (01h)
current ports settings (drive modes output data) other configuration registers saved EEPROM using store configuration command (Cmd). These settings automatically loaded after next device power command issued.
Restore Factory Defaults (02h)
This command replaces saved user configuration with factory default configuration. Current settings unaffected this command. settings loaded after next device power command issued.
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Read Defaults (04h)
This command reads settings stored EEPROM. read defaults user must:
read device configuration user must:
Write command Read data bytes (see Table 16). Read byte.
Write command Read data bytes (see Table Read byte.
Reconfigure Device (07h)
This command immediately reconfigures device with actual defaults from EEPROM. same effect registers POR.
Write Device Config (05h)
This command sends device configuration CY8C95xx. followed data bytes according Table calculated data bytes (00h-91h). check fails incomplete block sent, then slave responds with device does data. This gives user `flat-address-space' access device settings. current device configuration user must:
Write command Write data bytes with values registers Write byte calculated previous data bytes.
check passes, then device uses settings immediately. Content data block described Table
Read Device Config (06h)
This command reads current device configuration. gives user `flat-address-space' access device settings.
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Electrical Specifications
This section lists electrical specifications CY8C95xxA device. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC, except where noted. Table lists units measure that used this section. Table Units Measure Symbol Vrms
Unit Measure degree Celsius kilohertz megahertz microsecond microvolts microvolts root-mean-square
Symbol
Unit Measure milli-ampere nanoampere nanosecond picofarad volts
Absolute Maximum Ratings
Table Absolute Maximum Ratings Symbol TSTG Description Storage temperature +100 Units
Notes Higher storage temperatures reduces data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrades reliability.
VIOZ IMIO
Ambient temperature with power applied Supply voltage relative input voltage voltage applied tri-state Maximum current into port Electro Static Discharge Voltage Latch current
-0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient temperature Junction temperature +100 Units
Notes temperature rise from ambient junction package specific. "Thermal Impedances Package" page user must limit power consumption comply with this requirement.
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Electrical Characteristics
Chip-Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table CY8C9520A Chip-Level Specifications Symbol Description Supply voltage Supply current IDD3 Supply current 3.3V 3.00 5.25 Units Notes Conditions 5.0V, Conditions 3.3V,
Table CY8C9540A Chip-Level Specifications Symbol Description Supply voltage Supply current IDD3 Supply current 3.3V 3.00 5.25 Units Notes Conditions 5.0V, Conditions 3.3V,
Table CY8C9560A Chip-Level Specifications Symbol Description Supply voltage Supply current IDD3 Supply current 3.3V 3.00 5.25 Units Notes Conditions 5.0V, Conditions 3.3V,
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol FlashENPB FlashENT FlashDR
Description Flash (EEPROM) endurance block) 10,000 Flash endurance (total)a 1,800,000 Flash data retention
Units Years
Notes Erase/write cycles block. Erase/write cycles.
maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles).
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General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications Symbol Description High output level Units Notes pin, 4.75 5.25V. maximum combined GPort0; GPort2_Bit3; GPort3; GPort5_Bit2, GPort6. maximum combined GPort1; GPort2_Bit0, GPort4; GPort5_Bit0, GPort7. maximum combined IOH. pin, 4.75 5.25V. maximum combined GPort0; GPort2_Bit3; GPort3; GPort5_Bit2, GPort6. maximum combined GPort1; GPort2_Bit0, GPort4; GPort5_Bit0, GPort7. maximum combined IOL. 5.5. 5.5. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
output level
0.75
COUT
Input level Input high level Input leakage (absolute value) Capacitive load pins input Capacitive load pins output
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Electrical Characteristics
General Purpose Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only unless otherwise specified. Table GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise time, normal strong mode, Cload Fall time, normal strong mode, Cload Rise time, slow strong mode, Cload Fall time, slow strong mode, Cload Units Notes Normal Strong Mode 4.75 5.25V, 4.75 5.25V, 5.25V, 5.25V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Output Jitter Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only unless otherwise specified. Table Output Jitter Specifications Symbol Description Jitter24MHzPWM based peak-to-peak period jitter Jitter32kHzPWM kHz-based peak-to-peak period jitter Units Notes MHz, MHz, 93.75 367.6 (programmable) sources. clock source.
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Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only unless otherwise specified. Table Characteristics Pins Symbol Description Standard Mode Fast Mode 1003 Units Notes
clock frequency FSCLI2C THDSTAI2C Hold time (repeated) START condition. After this period, first clock pulse generated. TLOWI2C period clock HIGH period clock THIGHI2C TSUSTAI2C Setup time repeated START condition THDDATI2C Data hold time TSUDATI2C Data setup time TSUSTOI2C Setup time STOP condition free time between STOP START TBUFI2C Condition TSPI2C Pulse width spikes suppressed input filter.
Figure Definition Timing Fast/Standard Mode
LOWI2C SUDATI2C THDSTAI2C
SPI2C BUFI2C
HDSTAI2C HDDATI2C HIGHI2C TSUSTAI2C SUSTOI2C
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Packaging Dimensions
This section illustrates packaging specifications CY8C95xxA device, along with thermal impedances each package, typical package capacitance crystal pins, solder reflow peak temperature. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions Figure 28-Pb (210-Mil) SSOP
51-85079
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Figure 48-Pb (300-Mil) SSOP
51-85061
Figure 100-Pb TQFP
51-85048
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Thermal Impedances
Table Thermal Impedances Package Package SSOP SSOP TQFP
POWER
Typical 101oC/W 69oC/W 48oC/W
Solder Reflow Peak Temperature
Table lists minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP SSOP TQFP Minimum Peak Temperaturea 240oC 220oC 220oC Maximum Peak Temperature 260oC 260oC 260oC
Higher temperatures required based solder melting point. Typical temperatures solder 220+/-5oC with Sn-Pb 245+/-5oC with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Features Ordering Information
Table lists CY8C95xxA device's package features ordering codes. definition ordering number code follows. Table CY8C95xxA Device Features Ordering Information Configurable Pins Page Temperature Range EEPROM (Bytes) Ordering Code Package Sources
(210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SSOP (300 Mil) SSOP (Tape Reel) TQFP TQFP (Tape Reel)
CY8C9520A-24PVXIa CY8C9520A-24PVXIT1 CY8C9540A-24PVXI1 CY8C9540A-24PVXIT1 CY8C9560A-24AXI1 CY8C9560A-24AXIT1
-40oC +85oC -40oC +85oC -40oC +85oC -40oC +85oC -40oC +85oC -40oC +85oC
after existing port expander part number indicates device firmware.
Ordering Code Definitions
xxx-SPxx
Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free Pb-Free Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Thermal Rating: Commercial Industrial Extended
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Document History Page
Document Title: CY8C9520A, CY8C9540A, CY8C9560A, 20-, 40-, 60-Bit Expander with EEPROM Document Number: 38-12036 Revision
346754 392484 1336984
Orig. Change
HMT/AESA silicon, document.
Description Change
Correct TQFP. Output Jitter spec. table. Upgrade Perform logo update code trademarks. Update typical recommended Storage Temperature industrial specs. Update copyright trademarks. Watchdog timer details. existing part numbers indicate firmware. errors. Implement template.
Distribution: External/Public Posting: None
Cypress Semiconductor Corporation, 2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 38-12036 Rev.
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PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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