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ISL28278, ISL28478

Data Sheet July 11, 2007 FN6145.2

ISL28278, ISL28478
Data Sheet July 11, 2007 FN6145.2
Dual and Quad Micropower Single Supply Rail-to-Rail Input and Output (RRIO) Op-Amp
Features
· Low power 120µA typical supply current (ISL28278) · 225V max offset voltage · 30pA max input bias current · 300kHz typical gain-bandwidth product · 105dB typical PSRR · 100dB typical CMRR · Single supply operation down to 2.4V · Input is capable of swinging above V+ and below V(ground sensing) · Rail-to-rail input and output (RRIO) · Enable Pin (ISL28278 only) · Pb-free plus anneal available (RoHS compliant)
Applications
· Battery- or solar-powered systems · 4mA to 25mA current loops
Pinouts
ISL28278 (16 LD QSOP) TOP VIEW
· Handheld consumer products · Medical devices · Thermocouple amplifiers · Photodiode pre-amps · pH probe amplifiers
Ordering Information
PART NUMBER (Note) ISL28278FAZ ISL28478FAZ PART MARKING 28278FAZ 28478FAZ PACKAGE (Pb-Free) 16 Ld QSOP 16 Ld QSOP PKG. DWG. # MDP0040 MDP0040
ISL28478 (16 LD QSOP) TOP VIEW
ISL28278, ISL28478
Thermal Information
Thermal Resistance JA (°C / W) 16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com / pbfree / Pb-FreeReflow.asp
Operating Junction
Electrical Specifications
PARAMETER DC SPECIFICATIONS VOS V OS -------T IOS IB CMIR CMRR PSRR AVOL
DESCRIPTION
Maximum Output Voltage Swing
IS, ON
Quiescent Supply Current, Enabled
ISL28278, All channels enabled. ISL28478, All channels enabled.
IS, OFF
Quiescent Supply Current, Disabled
All channels disabled. ISL28278
FN6145.2 July 11, 2007
ISL28278, ISL28478
Electrical Specifications
PARAMETER IO+ IOVSUPPLY VENH VENL IENH IENL
DESCRIPTION Short Circuit Sourcing Capability Short Circuit Sinking Capability Supply Operating Range EN Pin High Level EN Pin Low Level EN Pin Input High Current EN Pin Input Low Current
kHz µVP-P nV / Hz pA / Hz dB dB dB
FN6145.2 July 11, 2007
10k FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
120 80 GAIN GAIN (dB) 40 0 PHASE -40 -80 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)
80 40 PHASE (°) GAIN (dB) 0 -40 -80 -120 10M
100 80 PHASE 60 40
200 150 100 50 0 PHASE (°)
-50 -100 -150 1M
FREQUENCY (Hz)
FIGURE 3. AVOL vs FREQUENCY @ 100k LOAD
FIGURE 4. AVOL vs FREQUENCY @ 1k LOAD
10 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90
PSRR +
FREQUENCY (Hz)
FIGURE 5. PSRR vs FREQUENCY
FIGURE 6. CMRR vs FREQUENCY
FN6145.2 July 11, 2007
1k VOLTAGE NOISE (nV / Hz) CURRENT NOISE (fA / Hz) 1 10 100 FREQUENCY (Hz) 1k 10k 1k
10 1 10 100 FREQUENCY (Hz) 1k 10k
FIGURE 7. VOLTAGE NOISE vs FREQUENCY
FIGURE 8. CURRENT NOISE vs FREQUENCY
FIGURE 9. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 10. SMALL SIGNAL TRANSIENT RESPONSE
VOLTS (V)
0 VOUT
0 10µs / DIV TIME (µs)
FIGURE 11. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 12. ISL28278 ENABLE TO OUTPUT DELAY TIME
FN6145.2 July 11, 2007
FIGURE 13. INPUT OFFSET VOLTAGE vs COMMON MODE INPUT VOLTAGE
FIGURE 14. INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE
280 270 260 CURRENT (µA) 250 240 230 220 210 200 190 -40
FN6145.2 July 11, 2007
MIN 80 100 120
TEMPERATURE (°C)
IBIAS+ (pA)
IBIAS- (pA)
MEDIAN
MIN -1200 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FN6145.2 July 11, 2007
MEDIAN
20 40 60 80 TEMPERATURE (°C)
PSRR (dB)
MEDIAN
20 40 60 80 TEMPERATURE (°C)
FN6145.2 July 11, 2007
TEMPERATURE (°C)
- OUTPUT SHORT CIRCUIT CURRENT (mA)
TEMPERATURE (°C)
FN6145.2 July 11, 2007
ISL28278, ISL28478 Pin Descriptions
V+ LOGIC PIN VCIRCUIT 2 CIRCUIT 3 V+
CAPACITIVELY COUPLED ESD CLAMP
DESCRIPTION
V+ ININ+ V-
V+ OUT V-
VCIRCUIT 4
CIRCUIT 1
Applications Information
Introduction
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an
Input Protection
All input terminals have internal ESD protection diodes to the positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. There is an additional pair of back-to-back diodes across the input terminals. For applications where the input differential voltage is expected to exceed 0.5V, external series resistors must be used to ensure the input currents never exceed 5mA.
FN6145.2 July 11, 2007
ISL28278, ISL28478
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. Both parts, with a 100k load, will typically swing to within 4mV of the positive supply rail and within 3mV of the negative supply rail. form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.
HIGH IMPEDANCE INPUT IN V+
Enable / Disable Feature
FIGURE 37. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
Example Application
Using Only One Channel
The ISL28278 and ISL28478 are dual and quad channel op amps. If the application only requires one channel when using the ISL28278 or less than 4 channels when using the ISL28478, the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 36).
R4 100k R3 R2 K TYPE THERMOCOUPLE 10k 10k V+ + ISL28X78 V-
410µV / °C + 5V
R1 100k
FIGURE 38. THERMOCOUPLE AMPLIFIER
+ 1 / 2 ISL28278 1 / 4 ISL28478
Current Limiting
The ISL28278 and ISL28478 have no internal currentlimiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.
FIGURE 36. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28278 and ISL28478, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 37 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should
Power Dissipation
It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1:
FN6145.2 July 11, 2007
ISL28278, ISL28478
where: · PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) · PDMAX for each amplifier is calculated in Equation 2:
FN6145.2 July 11, 2007
ISL28278, ISL28478 Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
e C SEATING PLANE 0.004 C 0.007 C A B b
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and / or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6145.2 July 11, 2007