X9530 November 2005 FN8211.1 Temperature Compensated Laser D
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Data Sheet X960
X9530
November 2005 FN8211.1
Temperature Compensated Laser Diode Controller
FEATURES Compatible with Popular Fiber Optic Module Specifications such Xenpak, SFF, SFP, GBIC Package TSSOP Programmable Current Generators -±1.6 max. -8-bit (256 Step) Resolution Integrated Converter Temperature Compensation -Internal External Sensor -40°C +100°C Range -2.2°C/step Resolution -EEPROM Look-up Tables Pluggable 2176-bit EEPROM Pages Bytes Page Write Protection Circuitry -Intersil BlockLock-Logic Controlled Protection -2-wire with Slave Address Bits 5.5V, Single Supply Operation Pb-Free Plus Anneal Available (RoHS Compliant) LASER DIODE BIAS CONTROL APPLICATIONS SONET Transmission Systems Ethernet, Fibre Channel Laser Diode Driver Circuits
DESCRIPTION X9530 highly integrated laser diode bias controller which incorporates digitally controlled Programmable Current Generators, temperature compensation with dedicated look-up tables, supplementary EEPROM array. functions device controlled 2-wire digital serial interface. temperature compensated Programmable Current Generators, vary output current with temperature according contents associated nonvolatile look-up table. look-up table programmed with arbitrary data user, 2-wire serial port, either internal external temperature sensor used control output current response. These temperature compensated pro-grammable currents maybe used control modulation current bias current laser diode. integrated General Purpose EEPROM included product data storage used transceiver module information storage laser diode applications.
PART NUMBER X9530V14I* X9530V14IZ* (Note) PART MARKING X9530V X9530V TEMP RANGE (°C)
PACKAGE LEAD TSSOP LEAD TSSOP (Pb-free)
*Add "T1" suffix tape reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CONFIGURATION VRef VSense
TSSOP
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. Rights Reserved other trademarks mentioned property their respective owners.
X9530
TYPICAL APPLICATION
GBIC Module High Speed Data Input Laser Diode Driver Circuit
X9530 MOD_DEF(0) MOD_DEF(1) IPINSET/IBIASSET IMODSET
IMON
BLOCK DIAGRAM
Voltage Reference VRef VSense Temperature Sensor Look-up Table Look-up Table Control Status General Purpose Memory
2-Wire Interface
DEVICE DESCRIPTION X9530 combines Programmable Current Generators, integrated EEPROM with Block Lockprotection, package. Programmable Current Generators ideal fiber optic Modulation Current require temperature control. combination X9530 functionality Intersil's Chip-Scale package lowers system cost, increases reliability, reduces board space requirements. on-chip Programmable Current Generators independently programmed either sink source current. maximum current generated determined using externally connected programming resistor, selecting three
predefined values. Both current generators have maximum output ±1.6 controlled absolute resolution 0.39% (256 steps bit). Both current generators driven using onboard temperature sensor, external sensor, Control Registers. internal temperature sensor operates over very broad temperature range (-40°C +100°C). sensor output (internal external) drives 6-bit converter, whose output selects bytes from each nonvolatile look-up table (LUT). contents selected (8-bit wide) drives input 8-bit converter, which generates output current. control setup parameters X9530, including look-up tables, programmable 2-wire serial port.
FN8211.1 November 2005
X9530
general purpose memory portion device CMOS serial EEPROM array with Intersil's Block Lockprotection. This memory used store fiber optic module manufacturing data, serial numbers, various other system parameters. ASSIGNMENTS TSSOP
EEPROM array internally organized bits with 16-Byte pages, utilizes Intersil's proprietary Direct Writecells, providing minimum endurance 100,000 Page Write cycles minimum data retention years.
Name
Description
Device Address Select This determines device address required communicate using 2-wire interface. on-chip pull-down resistor. Device Address Select This determines intermediate device address required communicate using 2-wire interface. on-chip pull-down resistor. Device Address Select This determines device address required communicate using 2-wire interface. on-chip pull-down resistor. Supply Voltage. Write Protect Control Pin. This CMOS compatible input. When LOW, Write Protection enabled preventing "Write" operation. When HIGH, various areas memory protected using Block Lock bits BL0. on-chip pull-down resistor, which enables Write Protection when this left floating. Serial Clock. This compatible input pin. This input 2-wire interface clock controlling data input output pin. Serial Data. This 2-wire interface data into device. compatible when used input, Open Drain when used output. This requires external pull resistor. Current Generator Output. This sinks sources current. magnitude direction current fully programmable adaptive. resolution bits. Current Programming Resistor resistor between this maximum output current available resistor used, maximum current must selected using control register bits. Current Programming Resistor resistor between this maximum output current available resistor used, maximum current must selected using control register bits. Ground. Sensor Voltage Input. This voltage input used drive input on-chip converter. Reference Voltage Input Output. This configured either Input Output. Input, voltage this provided external source. Output, voltage this buffered output voltage on-chip bandgap reference circuit. both cases, voltage this reference converter converters. Current Generator Output. This sinks sources current. magnitude direction current fully programmable adaptive. resolution bits.
VSense VRef
FN8211.1 November 2005
X9530
PRINCIPLES OPERATION CONTROL STATUS REGISTERS Control Status Registers provide user with mechanism changing reading value various parameters X9530. X9530 contains seven Control, Status, several Reserved registers, each being Byte wide (See Figure Control registers through located memory addresses through respectively. Status register memory address 87h, Reserved registers memory address through 8Fh. bits Control register always power-up logic state "0". bits Control registers through power-up logic state value kept their corresponding nonvolatile memory cells. nonvolatile bits register retain their stored values even when X9530 powered down, then powered back nonvolatile bits Control through Control registers preprogrammed logic state factory. Bits indicated "Reserved" ignored when read, must written "0", Write operation performed their registers. detailed description function each Control Status register bits follows: Control Register This register accessed performing Read Write operation address memory. BL1, BL0: BLOCK LOCK PROTECTION BITS (NON-VOLATILE) These bits used inhibit write operation certain addresses within memory array. protected region memory determined values bits shown table below: Protected Addresses (Size)
None (Default) (128 bytes) (192 bytes) 10Fh (256 bytes)
Notice that Write Protect (WP) input X9530 active (LOW), then write operation memory inhibited, irrespective Block Lock settings. VRM: VOLTAGE REFERENCE MODE (NON-VOLATILE) configures Voltage Reference (VRef) either input output. When (default), voltage VRef output from X9530's internal voltage reference. When "1", voltage reference VRef external. Figure ADCIN: CONVERTER INPUT SELECT (NON-VOLATILE) ADCIN selects input on-chip converter. When ADCIN (default), output on-chip temperature sensor input converter. When ADCIN "1", input converter voltage VSense pin. Figure ADCFILTOFF: FILTERING CONTROL (NON-VOLATILE) When this "1", status register updated after every conversion ADC. When this (default), status register updated after four consecutive conversions with same result. NV1234: CONTROL REGISTERS VOLATILITY MODE SELECTION (NON-VOLATILE) When NV1234 (default), bytes written Control registers stored volatile cells, their content lost when X9530 powered down. When NV1234 "1", bytes written Control registers stored both volatile nonvolatile cells, their value doesn't change when X9530 powered down powered back "Writing Control Registers" page I1DS: CURRENT GENERATOR DIRECTION SELECT (NON-VOLATILE) I1DS sets polarity Current Generator DAC1. When this (default), Current Generator X9530 configured Current Source. Current Generator configured Current Sink when I1DS "1". Figure
Partition array locked
None (Default)
GPM, LUT1 GPM, LUT1, LUT2
user attempts perform write operation protected region memory, operation aborted without changing data array.
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X9530
Figure Control Status Register Format
Byte Address Non-Volatile I2DS I1DS NV1234
Control Volatility Volatile Nonvolatile
ADCfiltOff
filtering
Voltage Reference Mode Internal External
Register Name
ADCIN
Input Internal External
Control
Direction Source Sink
Block Lock None Locked Locked GPM, LUT1, Locked GPM, LUT1, LUT2 Locked
Direct Access LUT1 Volatile Non-Volatile Reserved Reserved L1DA5 L1DA4 L1DA3 L1DA2 L1DA1 L1DA0 Control
Volatile Non-Volatile
Direct Access LUT2 Reserved Reserved L2DA5 L2DA4 L2DA3 L2DA2 L2DA1 L2DA0 Control
Direct Access DAC1 Volatile Non-Volatile D1DA7 D1DA6 D1DA5 D1DA4 D1DA3 D1DA2 D1DA1 D1DA0 Control
Direct Access DAC2 Volatile Non-Volatile D2DA7 D2DA6 D2DA5 D2DA4 D2DA3 D2DA2 D2DA1 D2DA0 Control
Non-Volatile
D2DAS
Direct Access DAC2 Disabled Enabled
L2DAS
Direct Access LUT2 Disabled Enabled
D1DAS
Direct Access DAC1 Disabled Enabled
L1DAS
Direct Access LUT1 Disabled Enabled
I2FSO1
I2FSO0
I1FSO1
I1FSO0
Control
Selection External Internal Middle Internal High Internal
Selection External Internal Middle Internal High Internal
Volatile
Write Enable Latch Write Disabled Write Enabled
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Control
Output Volatile Reserved Reserved Status
Registers byte addresses through reserved.
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X9530
I2DS: CURRENT GENERATOR DIRECTION SELECT (NON-VOLATILE) I2DS sets polarity Current Generator DAC2. When this (default), Current Generator X9530 configured Current Source. Current Generator configured Current Sink when I2DS "1". Figure Control Register This register accessed performing Read Write operation address memory. This byte's volatility determined NV1234 Control register L1DA5 L1DA0: LUT1 DIRECT ACCESS BITS When L1DAS (bit Control register "1", LUT1 addressed these bits, addressed output on-chip converter. When L1DAS "0", these bits ignored X9530. Figure value between (0010) (6310) written these register bits, select corresponding LUT1. written value added base address LUT1 (90h). Control Register This register accessed performing read write operation address memory. This byte's volatility determined NV1234 Control register L2DA5 L2DA0: LUT2 DIRECT ACCESS BITS When L2DAS (bit Control register "1", LUT2 addressed these bits, addressed output on-chip converter. When L2DAS "0", these bits ignored X9530. Figure value between (0010) (6310) written these register bits, select corresponding LUT2. written value added base address LUT2 (D0h). Control Register This register accessed performing Read Write operation address memory. This byte's volatility determined NV1234 Control register D1DA7 D1DA0: DIRECT ACCESS BITS When D1DAS (bit Control register "1", input converter content bits D1DA7 D1DA0, LUT1. When D1DAS (default) these eight bits ignored X9530. Figure Control Register This register accessed performing Read Write operation address memory. This byte's volatility determined NV1234 Control register D2DA7 D2DA0: DIRECT ACCESS BITS When D2DAS (bit Control register "1", input converter content bits D2DA7 D2DA0, LUT2. When D2DAS (default) these eight bits ignored X9530. (See Figure Control Register This register accessed performing Read Write operation address memory. I1FSO1 I1FSO0: CURRENT GENERATOR FULL SCALE OUTPUT BITS (NON-VOLATILE) These bits used full scale output current Current Generator pin, both bits (default), external resistor connected between Vss, determines full scale output current available other three options indicated table below. direction this current I1DS Control register Figure I1FSO1 I1FSO0 Full Scale Output Current externally (Default) ±0.4mA* ±0.85 ±1.3
external resistor should connected these cases between VSS.
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X9530
I2FSO1-I2FSO0: CURRENT GENERATOR FULL SCALE OUTPUT CURRENT BITS (NON-VOLATILE) These bits used full scale output current Current Generator pin, both bits (default), external resistor connected between Vss, determines full scale output current available other three options indicated table below. direction this current I2DS Control Register I2FSO1
D2DAS: DIRECT ACCESS SELECT (NONVOLATILE) When D2DAS (default), input converter LUT2. When D2DAS "1", that input content Control register Control Register This register accessed performing Read Write operation address memory. WEL: WRITE ENABLE LATCH (VOLATILE) controls Write Enable status entire X9530 device. This must before other Write operation (volatile nonvolatile). Otherwise, proceeding Write operation memory aborted issued after Data Byte. volatile latch that powers state (disabled). enabled writing 100000002 Control register Once enabled, remains until X9530 powered down, then again, until reset writing 000000002 Control register Write operation that modifies value will cause change other bits Control register Status Register Output This register accessed performing Read operation address memory. AD0: CONVERTER OUTPUT BITS (READ
ONLY)
I2FSO0
Full Scale Output Current
externally (Default) ±0.4mA* ±0.85 ±1.3
external resistor should connected these cases between VSS.
L1DAS: LUT1 DIRECT ACCESS SELECT (NONVOLATILE) When L1DAS (default), LUT1 addressed output on-chip converter. When L1DAS "1", LUT1 addressed bits L1DA5 L1DA0. D1DAS: DIRECT ACCESS SELECT (NONVOLATILE) When D1DAS (default), input converter LUT1. When D1DAS "1", that input content Control register L2DAS: LUT2 DIRECT ACCESS SELECT (NONVOLATILE) When L2DAS (default), LUT2 addressed output on-chip converter. When L2DAS "1", LUT2 addressed bits L2DA5 L2DA0.
These bits binary output on-chip converter. output 0000002 minimum input 1111112 full scale input.
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X9530
VOLTAGE REFERENCE voltage reference converters X9530, driven from on-chip voltage reference, from external source VRef pin. Control Register selects between options (See Figure default value "0", which selects internal reference. When internal reference selected, it's output voltage also output VRef with nominal value 1.21 external voltage reference preferred, Control Register must "1". Figure Voltage Reference Structure
VRM: Control register
default these output bits used select look-up tables associated with X9530's Current Generators. When ADCfiltOff (default), bits AD[5:0] updated each time performs four consecutive conversions with same exact result. When ADCfiltOff "1", these bits updated after every conversion. block diagram converter shown Figure voltage reference input (see "VOLTAGE REFERENCE" details), sets maximum amplitude ramp generator output. converter input signal (see "A/D Converter Input Select" below details) compared ramp generator output. control encode logic produces binary encoded output, with minimum value (010), full scale output value (6310). converter input voltage range (VINADC) from V(VRef). Converter Input Select input signal converter X9530, output on-chip temperature sensor, external source VSense pin. ADCIN Control register selects between options (See Figure It's default value "0", which selects internal temperature sensor. external source intended input converter, ADCIN Control register must "1".
VRef
On-chip Voltage Reference Converter Converters reference
CONVERTER X9530 contains general purpose, on-chip, 6-bit Analog Digital (A/D) converter whose output available Status Register bits AD[5:0]. Figure Converter Block Diagram
Comparator Converter Input From VRef Ramp Generator Conversion Reset Control Encode Logic Converter Output LUTs Status Register)
Clock
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X9530
Figure Converter Input Select Structure
ADCIN: Control register VSense On-chip Temperature Sensor
LOOK-UP TABLES X9530 memory array contains 64-byte look-up tables. associated I1's output current generator other I2's output current generator, through their corresponding converters. output each look-up table byte contained selected row. default these bytes inputs converters driving pins byte address selected obtained adding look-up table base address (90h LUT1, LUT2) appropriate selection bits. Figure default look-up table selection bits 6-bit output converter. Alternatively, converter bypassed selection bits LSBs Control Registers LUT1 LUT2 respectively. selection between these options illustrated Figure described "I2DS: Current Generator Direction Select (Non-volatile)" page "Control Register page CURRENT GENERATOR BLOCK Current Generator pins outputs independent current mode converters. Converter Operation Block Diagram each converters shown Figure input byte converter selects voltage non-inverting input operational amplifier. output amplifier drives gate FET, whose source connected ground resistor This node also back inverting input amplifier. drain connected output current (I1) "polarity select" circuit block.
Converter Input
VRef
Converter Range From Figure that operating range converter input depends voltage reference. from Figure that internal temperature Sensor output also varies with voltage reference (VRef). table below summarizes voltage range restrictions VSense VRef pins different configurations VSense VRef ranges VRef
Internal Internal External
Converter Input
Internal Temp. Sensor VSense VSense
Ranges
Applicable V(VSense) V(VRef) V(VRef) V(VSense) V(VRef) Valid Case
External
Internal Temp. Sensor
voltages referred Vss.
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X9530
Figure Converter Block Diagram
I1DS I2DS: bits Control register
Polarity Select Circuit
VRef DAC1 DAC2 Input byte
Voltage Divider
I1FSO[1:0] I2FSO[1:0] bits Control register R1_High_Current R2_High_Current
R1_Middle_Current R2_Middle_Current
R1_Low_Current R2_Low_Current
R1_External R2_External Optional external resistor
Figure Look-up Table (LUT) Operation
D2DA[7:0] Control register LUT2 Selection bits LUT2 10Fh Select D2DAS: Control register D1DA[7:0] Control register LUT1 Selection bits LUT1 Select D1DAS: Control register Input Byte Input Byte
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X9530
examining block diagram Figure that maximum current through fixing values V(VRef) output current then varied changing data byte converter input. general, magnitude current converter output pins (I1, calculated (V(VRef) (384 Rx)) where decimal representation input byte corresponding converter. value resistor 1,2) determines full scale output current that converter sink source. full scale output current maximum value ±1.6 which obtained using resistance This resistance connected externally X9530, selected from three internal values. Bits I1FSO1 I1FSO0 select full scale output current setting described "I1FSO1 I1FSO0: Current Generator Full Scale Output Bits (Non-volatile)" page Bits I2FSO1 I2FSO0 select maximum current setting described "I2FSO1-I2FSO0: Current Generator Full Scale Output Current Bits (Non-volatile)" page When internal resistor selected then resistor should connected externally corresponding pin. Bits I1DS I2DS Control Register select direction currents through pins independently (See "I1DS: Current Generator Direction Select (Non-volatile)" page "Control Status Register Format" page Converter Output Current Response When converter input data byte changes arbitrary number bits, output current changes from intial current level (Ix) some final level Ix). transition monotonic glitchless. Converter Control data byte inputs converters controlled three ways: With converter through look-up tables (default), Bypassing converter directly accessing look-up tables, Bypassing both converter look-up tables, directly setting converter input byte.
Figure Look-Up Table Addressing
Voltage Reference L2DA[5:0]: Control Register
LUT2 Selection bits
Select Voltage Input L2DAS: Control register L1DA[5:0]: Control Register
AD[5:0] Status Register
Select
LUT1 Selection bits
L1DAS: Control register
options summarized following tables:
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X9530
Converter Access Summary L1DAS
POWER-ON RESET When power applied X9530, device undergoes strict sequence events before current outputs converters enabled. When voltage becomes larger than power-on reset threshold voltage (VPOR), device recalls control bits from non-volatile memory into volatile registers. Next, analog circuits powered When voltage becomes larger than second voltage threshold (VADCOK), enabled. default case, after performs four consecutive conversions with same exact result, output used select byte from each look-up table. Those bytes become input DACs. During previous sequence input both DACs 00h. ADCfiltOff "1", only conversion necessary. Bits D1DAS, D2DAS, L1DAS, L2DAS, also modify DACs accessed first time after power-up, described "Control Register page X9530 pluggable device. Voltage distrubances handled poweron reset circuit, allowing proper operation during plug-in applications. SERIAL INTERFACE Serial Interface Conventions device supports bidirectional oriented protocol. protocol defines device that sends data onto transmitter, receiving device receiver. device controlling transfer called master device being controlled called slave. master always initiates data transfers, provides clock both transmit receive operations. X9530 operates slave applications.
D1DAS
Control Source
converter through LUT1 (Default) Bits L1DA5 L1DA0 through LUT1 Bits D1DA7 D1DA0
Don't Care Condition (May either "0")
Converter Access Summary L2DAS
D2DAS
Control Source
converter through LUT2 (Default) Bits L2DA5 L2DA0 through LUT2 Bits D2DA7 D2DA0
Don't Care Condition (May either "0")
converter shared between current generators look-up tables, converters, control bits, selection bits completely independently. Bits D1DAS D2DAS used bypass converter look-up tables, allowing direct access inputs converters with bytes control registers respectively. Figure descriptions control bits. Bits I1DS I2DS Control Register select direction currents through pins independently Figure descriptions control bits.
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X9530
Figure Converter Power-on Reset Response Voltage VADCOK
Current
Time
TIME
Time device responds with after recognition START condition followed valid Slave Address byte. valid Slave Address byte must contain Device Type Identifier 1010, Device Address bits matching logic state pins Figure write operation selected, device responds with after receipt each subsequent eight-bit word. read mode, device transmits eight bits data, releases line, then monitors line ACK. device continues transmitting data detected. device terminates further data transmissions detected. master must then issue STOP condition place device into known state. X9530 acknowledges incoming data address bytes except: "Slave Address Byte" when "Device Identifier" "Device Address" wrong; "Data Bytes" when "WEL" "0", with exception "Data Byte" addresses location 86h; "Data Bytes" following "Data Byte" addressed locations 80h, 85h, 86h.
Serial Clock Data Data states line change only while LOW. state changes while HIGH reserved indicating START STOP conditions. Figure power-up X9530, input mode. Serial Start Condition commands preceded START condition, which HIGH transition while HIGH. device continuously monitors lines START condition does respond command until this condition been met. Figure Serial Stop Condition communications must terminated STOP condition, which HIGH transition while HIGH. STOP condition also used place device into Standby power mode after read sequence. STOP condition only issued after transmitting device released bus. Figure Serial Acknowledge (Acknowledge), software convention used indicate successful data transfer. transmitting device, either master slave, releases after transmitting eight bits. During ninth clock cycle, receiver pulls line acknowledge reception eight bits data. Figure
FN8211.1 November 2005
X9530
Figure Valid Start Stop Conditions
START STOP
Figure Valid Data Changes
Data Stable Data Change Data Stable
Figure Acknowledge Response From Receiver
from Master Output from Transmitter
Output from Receiver START
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X9530
X9530 Memory X9530 contains 2176 array mixed volatile nonvolatile memory. This array split into four distinct parts, namely: (Refer Figure 12.) General Purpose Memory (GPM) Look-up Table (LUT1) Look-up Table (LUT2) Control Status Registers nonvolatile EEPROM, located memory addresses 7Fh. Figure X9530 Memory
Address 10Fh Look-up Table (LUT2) Look-up Table (LUT1) Control Status Registers General Purpose Memory (GPM) Bytes Bytes Size
Addressing Protocol Overview Serial Interface operations must begin with START, followed Slave Address Byte. Slave address selects X9530, specifies Read Write operation performed. should noted that Write Enable Latch (WEL) must first order perform Write operation other bit. (See "WEL: Write Enable Latch (Volatile)" page Also, communication X9530 over 2-wire serial conducted sending each byte data first. Even though 2176 memory consists four differing functions, physically realized contiguous array, organized pages bytes each. X9530 2-wire protocol provides address byte, therefore, only bytes addressed directly. next sections explain access different areas reading writing. Figure Slave Address (SA) Format
Bytes Device Type Identifier Device Address Read Write
Bytes
Control Status registers X9530 used test setup device system. These registers realized combination both volatile nonvolatile memory. These registers reside memory locations through 8Fh. reserved bits within registers through 86h, must written writing them, should ignored when reading. reserved registers, from through 8Fh, must written, their content should ignored. Both look-up tables LUT1 LUT2 realized nonvolatile EEPROM, extend from memory locations 90h-CFh D0h-10Fh respectively. These look-up tables dedicated storing data solely purpose setting outputs Current Generators respectively. bits both look-up tables preprogrammed factory.
Slave Address Bit(s)
Description
Device Type Identifier Device Address Read Write Operation Select
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X9530
Slave Address Byte Following START condition, master must output Slave Address Byte (Refer Figure 13.). This byte includes three parts: four MSBs (SA7 SA4) Device Type Identifier, which must always 1010 order select X9530. next three bits (SA3 SA1) Device Address bits (AS2 AS0). access part X9530's memory, value bits AS2, AS1, must correspond logic levels pins respectively. (SA0) bit. This defines operation performed device being addressed. When "1", then Read operation selected. selects Write operation (Refer Figure 13.) Nonvolatile Write Acknowledge Polling After nonvolatile write command sequence correctly issued (including final STOP condition), X9530 initiates internal high voltage write cycle. Figure Acknowledge Polling Sequence
Byte load completed issuing STOP. Enter Polling
This cycle typically requires During this time, Read Write command ignored X9530. Write Acknowledge Polling used determine whether high voltage write cycle completed. During acknowledge polling, master first issues START condition followed Slave Address Byte. Slave Address Byte contains X9530's Device Type Identifier Device Address. Slave Address (R/W) either this case. device busy within high voltage cycle, then returned. high voltage cycle completed, returned master then proceed with Read Write operation. (Refer Figure 14.). Byte Write Operation order perform Byte Write operation memory array, Write Enable Latch (WEL) Control Register must first "1". (See "WEL: Write Enable Latch (Volatile)" page Byte Write operation, X9530 requires Slave Address Byte, Address Byte, Data Byte (See Figure 15). After each them, X9530 responds with ACK. master then terminates transfer generating STOP condition. this time, data bits volatile, X9530 ready next read write operation. some bits nonvolatile, X9530 begins internal write cycle nonvolatile memory. During internal nonvolatile write cycle, X9530 does respond requests from master. output high impedance. Byte Write operation access bytes locations through directly, when setting Address Byte through respectively. Setting Address Byte accesses byte location 100h. other sixteen bytes, locations 101h through 10Fh only accessed using Page Write operations. byte location only written using "Page Write" operation. Writing Control bytes which located byte addresses through special case described section "Writing Control Registers".
Issue START
Issue Slave Address Byte (Read Write)
Issue STOP
returned?
High Voltage complete. Continue command sequence. Continue normal Read Write command sequence
Issue STOP
PROCEED
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X9530
Figure Byte Write Sequence
Write Signals from Master Slave Address Address Byte Data Byte
Signal Signals from Slave
Page Write Operation 2176-bit memory array physically realized contiguous array, organized pages bytes each. order perform Page Write operation memory array, Write Enable Latch (WEL) Control register must first (See "WEL: Write Enable Latch (Volatile)" page Page Write operation initiated same manner byte write operation; instead terminating write cycle after first data byte transferred, master transmit bytes (See Figure 16). After receipt each byte, X9530 responds with ACK, internal byte address counter incremented one. page address remains constant. When counter reaches page, "rolls over" goes back first byte same page. example, master writes bytes 16-byte page starting location (decimal), first bytes written locations through while last bytes written locations through within that page. Afterwards, address counter would point location master supplies more than bytes data, then data overwrites previous data, byte time (See Figure 17).
master terminates loading Data Bytes issuing STOP condition, which initiates nonvolatile write cycle. with Byte Write operation, inputs disabled until completion internal write cycle. Page Write operation cannot performed page locations through 8Fh. Next section describes special cases within that page. Page Write operation starting with byte address FFh, accesses page between locations 100h 10Fh. first data byte such operation written location 100h. Writing Control Registers byte location 80h, bytes locations through written using Byte Write operations. They cannot written using Page Write operation. Control bytes through locations through respectively, written during single operation (See Figure 18). sequence must START, followed Slave Address byte, with equal "0", followed Address Byte, then followed exactly four Data Bytes, STOP condition. first data byte written location 81h, second 82h, third 83h, last 84h.
Figure Page Write Operation
Write Signals from Master Slave Address Address Byte Data Byte Data Byte
Signal Signals from Slave
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X9530
Figure Example: Writing bytes 16-byte page starting location
bytes
bytes bytes
Address=0
Address=6 Address=7 Address Pointer Ends Here
Address=11 Address=15
four registers Control through have nonvolatile volatile cell each bit. power-up, content nonvolatile cells automatically recalled written volatile cells. content volatile cells controls X9530's functionality. NV1234 Control register "1", Write operation these registers writes both volatile nonvolatile cells. NV1234 Control register "0", Write operation these registers only writes volatile cells. both cases newly written values effectively control X9530, second case, those values lost when part powered down. NV1234 "0", Byte Write operation Control registers causes value nonvolatile cells Control registers through recalled into their corresponding volatile cells, during power-up. This doesn't happen when LOW, because Write Protection enabled. generally recommended configure Control registers before writing Control registers through
When reading control registers Data Bytes always content corresponding nonvolatile cells, even NV1234 (See "Control Status Register Format"). Read Operation Read operation consist three byte instruction followed more Data Bytes (See Figure 19). master initiates operation issuing following sequence: START, Slave Address byte with "0", Address Byte, second START, second Slave Address byte with "1". After each three bytes, X9530 responds with ACK. Then X9530 transmits Data Bytes long master responds with during cycle following eigth each byte. master terminates read operation (issuing STOP condition) following last last Data Byte (See Figure 19).
Figure Writing Control Registers
Write Slave Address Address Byte Four Data Bytes Data Byte Control Data Byte Control
Signals from Master
Signal
Signals from Slave
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X9530
Figure Read Sequence
Signals from Master Slave Address with Slave Address with
Address Byte
Signal Signals from Slave
First Read Data Byte Last Read Data Byte
Data Bytes from memory location indicated internal pointer. This pointer initial value determined Address Byte Read operation instruction, increments during transmission each Data Byte. After reaching memory location 10Fh pointer "rolls over" 00h, device continues output data each received. Read operation internal pointer start memory location from through FEh, when Address Byte through respectively. starts location 100h Address Byte FFh. When reading control registers Data Bytes always content corresponding nonvolatile cells, even NV1234 (See "Control Status Register Format").
Data Protection There four levels data protection designed into X9530: Write device first requires setting Control register; Block Lock prevent Writes certain regions memory; Write Protection disables writing X9530; proper clock count, data sequence, STOP condition required order start nonvolatile write cycle, otherwise X9530 ignores Write operation. Write Protection When Write Protection (WP) active (LOW), Write operations X9530 disabled, except writing bit.
FN8211.1 November 2005
X9530
APPLICATIONS INFORMATION Temperature Sensing X9530's on-chip temperature sensor functions similarly other semiconductor temperature sensors. surface mount package (TSSOP) Chip Scale Package both allow good thermal conduction from board die, X9530 will provide accurate measure temperature board. there ambient movement over device package board, then measured temperature will very close that board. there movement over package temperature substantially different from that board, then measured temperature will value between that board air. X9530 intended sense temperature particular component board, X9530 should located close possible that component minimize contributions from other devices differential temperatures across board. X9530 LASER DIODE BIAS APPLICATION EXAMPLE X9530 ideally suited control temperature sensitive parameters fiber optic applications. Figure shows typical topology laser driver circuit used many fiber optic transceiver modules. This example uses common anode connected Laser Diode (LD), conjunction with Monitor PhotoDiode (MPD). laser diode current (ILD) summation Bias Current (IBIAS), Modulation Current (IMOD) Automatic Power Control (APC) error signal current (IMON). circuit uses current (IMON) input, ensures that constant average optical power output maintaned. modulation circuitry driven external high speed data source. Typical control parameters driver circuit such shown Figure IMODSET Sets IMOD level, IBIASSET Sets IBIAS level, IPINSET: Sets average optical power output. Figure shows X9530 used control these parameters while providing accurate temperature compensation. this example output X9530 drives IMODSET input laser diode circuit. loading appropriate values into look-up table (LUT1) device, dynamically change modulation current driver circuit. This used compensate effect reduced laser light output elevated temperatures. Depending upon type driver circuit used, output X9530 used control either IBIASSET IPINSET parameters. example Figure uses control IPINSET parameter, while IBIASSET fixed value using Intersil Digital potentiometer. Similar control modulation current, used compensate changes IMON over temperature. loading appropriate values into look-up table (LUT2) device, this would have effect dynamically controlling average optical power output (via circuit) over temperature. lookup table values this fiber optic application could determined ways. well-defined data monitor photo diode drift over temperature, calculate appropriate values needed each temperature setting. Another test assembled module over temperature load values into tables each setting. This will require on/off control determine each MODSET value. Intersil application note AN156 full design analysis with driver application. design requirements such that temperature compensation necessary average optical power output then output could used bias current. IBIASET driver circuit controlled X9530, same current level could with control register. This would provide constant (temperature independant) setting bias current. previously described, X9530 also contains general purpose EEPROM memory which accessed wire serial bus. case pluggable fiber optic applications such GBIC, this memory used storage transceiver module parameters.
FN8211.1 November 2005
X9530
Figure Typical Laser Driver Circuit Topology
Laser Diode Driver Circuit High Speed Data Input IMODSET Bias Currrent Generation IBIASSET IPINSET IBIASMAX Modulation Currrent Generation IMOD IBIAS
IMON
IAPC (Error Signal) Automatic Power Control (APC)
Figure X9530 Application Example Block Diagram
GBIC Module High Speed Data Input IBIASSET INTERSIL XDCP MOD_DEF(0) MOD_DEF(1) X9530 IPINSET IMODSET Laser Diode Driver Circuit IMON
FN8211.1 November 2005
X9530
ABSOLUTE MAXIMUM RATINGS voltages referred Vss. Temperature under bias -65°C +100°C Storage temperature -65°C +150°C Voltage every except -1.0V Voltage 5.5V D.C. Output Current D.C. Output Current pins VRef VSense. -0.50 D.C. Output Current pins Lead temperature (soldering, 10s) 300°C OPERATING CONDITIONS Parameter
Temperature Temperature while writing memory Voltage Voltage other
COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification) implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Min. -0.3
Max. +100
Units
ELECTRICAL CHARACTERISTICS typical values 25°C ambient temperature Vcc. Maximum minimum specifications over recommended operating conditions. voltages referred voltage unless otherwise specified. bits control registers unless otherwise specified. 510, 0.1%, resistor connected between Vss, another between unless otherwise specified. 400kHz input unless otherwise specified. pulled through external resistor unless otherwise specified. 2-wire interface "standby" (see notes page 22), unless otherwise specified. floating unless otherwise specified. VRef unloaded, unless otherwise specified. Symbol
Iccstby Iccfull
Parameter
Standby current into Full operation current into
Unit
Test Conditions Notes
floating, VRef unloaded. 2-wire interface reading from memory, both connected Vss, input bytes: FFh, VRef unloaded. Average from START condition until after STOP condition Vcc, floating, VRef unloaded. V(WP), V(A0), V(A1), V(A2) from
Iccwrite
Nonvolatile Write current into
IPLDN VILTTL VIHTTL IINTTL VOLSDA IOHSDA VILCMOS
On-chip pull down current A1,and SDA, input voltage SDA, input High voltage input current output voltage output High current input voltage
voltage between Vcc, input. I(SDA) V(SDA)
FN8211.1 November 2005
X9530
ELECTRICAL CHARACTERISTICS (CONTINUED) typical values 25°C ambient temperature Vcc. Maximum minimum specifications over recommended operating conditions. voltages referred voltage unless otherwise specified. bits control registers unless otherwise specified. 510, 0.1%, resistor connected between Vss, another between unless otherwise specified. 400kHz input unless otherwise specified. pulled through external resistor unless otherwise specified. 2-wire interface "standby" (see notes page 22), unless otherwise specified. floating unless otherwise specified. VRef unloaded, unless otherwise specified. Symbol
VIHCMOS VRefout RVref TCOref VRef Range TSenseRange VPOR VccRamp VADCOK
Parameter
input High voltage Output Voltage VRef 25°C VRef input resistance Temperature coefficient VRef output voltage Voltage range when VRef input Temperature sensor range Current from Power-on reset threshold voltage Ramp Rate enable minimum voltage
1.205 -100
Unit
ppm/°
Test Conditions Notes
1.21
1.215 +100 1600
I(VRef) "1", 25°C note note note
Figure
Notes: device goes into Standby: after STOP, except those that initiate nonvolatile write cycle. goes into Standby after STOP that initiates nonvolatile write cycle. also goes into Standby clock cycles after START that followed correct Slave Address Byte. time from valid STOP condition write sequence self-timed internal nonvolatile write cycle. minimum cycle time allowed nonvolatile write user, unless Acknowledge Polling used. this range V(VRef) full scale sink mode current follows V(VRef) with linearity error smaller than These parameters periodically sampled 100% tested. TCOref [Max V(VREF) V(VREF)] 106/(1.21V 140°C)
FN8211.1 November 2005
X9530
CONVERTER CHARACTERISTICS typical values 25°C ambient temperature Vcc. Maximum minimum specifications over recommended operating conditions. voltages referred voltage unless otherwise specified. bits control registers unless otherwise specified. 510, 0.1%, resistor connected between Vss, another between unless otherwise specified. 400kHz input unless otherwise specified. pulled through external resistor unless otherwise specified. 2-wire interface "standby" (see notes page 22), unless otherwise specified. floating unless otherwise specified. Symbol
IFS00 IFS01 IFS10 IFS11 OffsetDAC FSErrorDAC DNLDAC INLDAC
Parameter
full scale current, with external resistor setting full scale current, with internal current setting option full scale current, with internal middle current setting option full scale current, with internal high current setting option converter offset error converter full scale error converter Differential Nonlinearity converter Integral Nonlinearity with respect straight line through full scale value Sink Voltage Compliance Source Voltage Compliance overshoot Converter data byte transition undershoot Converter data byte transition rise time Converter data byte transition; Temperataure coefficient output current when using internal resistor setting
1.56 0.64 -0.5
1.58 0.85
1.06
Unit
Test Conditions Notes
input Byte FFh, Source sink mode, V(I1) V(I2) 1.2V source mode 1.2V sink mode. notes
VISink VISource IOVER IUNDER trDAC TCOI1I2
Vcc-1.2
ppm/
this range current vary this range current vary input byte changing from vice versa, V(I1) V(I2) 1.2V source mode 1.2V sink mode. note Figure Bits I1FSO[1:0] Bits I2FSO[1:0] 002, VRMbit
±200
Notes: defined
V(VRef)]
divided resistance between Vss.
OffsetDAC: Offset defined deviation between measured ideal output, when input 01h. expressed LSB. FSErrorDAC: Full Scale Error defined deviation between measured ideal output, when input FFh. expressed LSB. OffsetDAC subtracted from measured value before calculating FSErrorDAC. DNLDAC: Differential Non-Linearity defined deviation between measured ideal incremental change output DAC, when input changes code step. expressed LSB. measured values adjusted Offset Full Scale Error before calculating DNLDAC. INLDAC: Integral Non-Linearity defined deviation between measured ideal transfer curves, after adjusting measured transfer curve Offset Full Scale Error. expressed LSB. These parameters periodically sampled 100% tested.
FN8211.1 November 2005
X9530
CONVERTER CHARACTERISTICS
typical values 25°C ambient temperature Vcc. Maximum minimum specifications over recommended operating conditions. voltages referred voltage unless otherwise specified. bits control registers unless otherwise specified. 510, 0.1%, resistor connected between Vss, another between unless otherwise specified. 400kHz input unless otherwise specified. pulled through external resistor unless otherwise specified. 2-wire interface "standby" (see notes page 22), unless otherwise specified. floating unless otherwise specified.
Symbol
ADCTIME
Parameter
converter conversion time
Unit
Test Conditions Notes
Proportional converter input voltage. This value maximum full scale input converter. ADCfiltOff VSense input, ADCIN VSense input, ADCIN "1", Frequency note This Converter Dynamic Range. ADCIN notes
RINADC CINADC
VSense input resistance VSense input capacitance
VINADC OffsetADC FSErrorADC DNLADC INLADC TempStepADC
VSense input signal range converter offset error converter full scale error Converter Differential Nonlinearity converter Integral Nonlinearity Temperature step causing step increment output output 25°C
-0.25 -0.5 -0.5
V(VRef) 0.25
Out25ADC
0111012
Notes: "LSB" defined V(VRef)/63, "Full Scale" defined V(VRef). 31/2 V(VRef) OffsetADC: ideal converter, first transition transfer curve occurs above zero. Offset error amount deviation between measured first transition point ideal point. V(VRef) FSErrorADC: ideal converter, last transition transfer curve occurs .Full Scale Error amount deviation between measured last transition point ideal point, after subtracting Offset from measured curve. DNLADC: defined difference between ideal measured code transitions successive code outputs expressed LSBs. measured transfer curve adjusted Offset Fullscale errors before calculating DNL. INLADC: deviation measured transfer function converter from ideal transfer function. error also defined errors starting from code code where measurement desired. measured transfer curve adjusted Offset Fullscale errors before calculating INL. These parameters periodically sampled 100% tested.
FN8211.1 November 2005
X9530
2-WIRE INTERFACE A.C. CHARACTERISTICS Symbol
fSCL
Parameter
Clock Frequency Pulse width Suppression Time inputs Data Valid Time free before start transmission Clock Time Clock High Time Start Condition Setup Time Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Output Hold Time Rise Time Fall Time Setup Time Hold Time Capacitive load each line
1(3)
Units
Test Conditions Notes
"2-Wire Interface Test Conditions" (below), Figure Figure Figure
tAA(4) tBUF(4) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO
1300 +0.1Cb(1) +0.1Cb(1) 1200(3) 1200(3)
tF(4) tSU:WP(4) tHD:WP Cb(4)
2-WIRE INTERFACE TEST CONDITIONS
Input Pulse Levels Input Rise Fall Times, between Input Output Timing Threshold Level External Load 1.4V
NONVOLATILE WRITE CYCLE TIMING Symbol
Parameter
Nonvolatile Write Cycle Time
Units
Test Conditions Notes
Figure
Notes: total capacitance line (SDA SCL) time from valid STOP condition write sequence self-timed internal nonvolatile write cycle. minimum cycle time allowed nonvolatile write user, unless Acknowledge Polling used. minimum frequency requirement applies between START STOP condition. These parameters periodically sampled 100% tested.
FN8211.1 November 2005
X9530
TIMING DIAGRAMS Figure Timing
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW
tBUF
Figure Timing
START STOP
tSU:WP tHD:WP
Figure Non-Volatile Write Cycle Timing
last byte
Stop Condition Start Condition
FN8211.1 November 2005
X9530
14-Lead Plastic, TSSOP, Package Code
.025 (.65)
.169 (4.3) .252 (6.4) .177 (4.5)
.193 (4.9) .200 (5.1)
.041 (1.05) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane .019 (.50) .029 (.75) Detail (20X) Seating Plane
.031 (.80) .041 (1.05) Detail
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
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Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN8211.1 November 2005
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