Data Sheet April 2007 FN2810.9 12-Bit Numerically Controlled Osci

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Data Sheet April 2007 FN2810.9 12-Bit Numerically Controlled Osci

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HSP45102
Data Sheet April 2007 FN2810.9
12-Bit Numerically Controlled Oscillator
Intersil HSP45102 Numerically Controlled Oscillator (NCO12) with 32-bit frequency resolution 12-bit output. With over 69dB spurious free dynamic range worst case frequency resolution 0.009Hz, NCO12 provides significant accuracy frequency synthesis solutions competitive price. frequency generated selected from frequency control words. single control selects which word used determine output frequency. Switching from frequency another occurs clock cycle, with clock pipeline delay from time that control word loaded until t4-he frequency appears output. pins, P0-1, provided phase modulation. They encoded added bits phase accumulator offset phase increments. 13-bit output Phase Offset Adder mapped sine wave amplitude Sine ROM. output data format offset binary simplify interfacing converters. Spurious frequency components output sinusoid less than -69dBc. NCO12 applications Direct Digital Synthesizer modulator cost digital radios, satellite terminals, function generators.
Features
33MHz, 40MHz Versions 32-Bit Frequency Control BFSK, QPSK Modulation Serial Frequency Load 12-Bit Sine Output Offset Binary Output Format 0.009Hz Tuning Resolution 40MHz Spurious Frequency Components <-69dBc Fully Static CMOS Cost Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Direct Digital Synthesis Modulation Communications Related Products HI5731 12-Bit, 100MHz Converter
Ordering Information
PART NUMBER HSP45102SC-33 HSP45102SC-33Z (Note) HSP45102SC-40 HSP45102SC-40Z (Note) HSP45102SI-3396 HSP45102SI-33Z (Note) PART MARKING HSP45102SC-33 HSP45102SC-33Z HSP45102SC HSP45102SC-40Z HSP45102SI HSP45102SI-33Z TEMP. RANGE (°C) PACKAGE SOIC (300 mil) SOIC (300 mil) (Pb-free) SOIC (300 mil) SOIC (300 mil)(Pb-free) SOIC (300 mil) (Tape Reel) SOIC (300 mil) (Pb-free) PKG. DWG. M28.3 M28.3 M28.3 M28.3 M28.3 M28.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005, 2007. Rights Reserved other trademarks mentioned property their respective owners.
HSP45102 Block Diagram
PO-1 MSB/LSB SFTEN SCLK FREQUENCY CONTROL SECTION LOAD TXFR ENPHAC SEL_L/M PHASE ACCUMULATOR PHASE OFFSET ADDER SINE OUT0-11
Pinout
HSP45102 LEAD SOIC) VIEW
OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 SEL_L/M SFTEN MSB/LSB ENPHAC SCLK OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 LOAD TXFR
FN2810.9 April 2007
HSP45102 Description
NAME P0-1 SCLK SEL_L/M SFTEN MSB/LSB ENPHAC TXFR TYPE power supply pin. Ground Phase modulation inputs (become active after pipeline delay four clocks). phase shift 90°, 180°, 270° selected shown Table clock. (CMOS level) This clocks frequency control shift register. high this input selects least significant bits 64-bit frequency register input phase accumulator; selects most significant bits. active input enables shifting frequency register. This input selects shift direction frequency register. this input shifts data first; high shifts data first. This pin, when low, enables clocking Phase Accumulator. This input pipeline delay four clocks. Data this shifted into frequency register rising edge SCLK when SFTEN low. This active input clocked onto chip becomes active after pipeline delay four clocks. When low, frequency control word selected SEL_L/M transferred from frequency register phase accumulator's input register. This input becomes active after pipeline delay five clocks. When low, feedback phase accumulator zeroed. Output data. OUT0 LSB. Unsigned. DESCRIPTION
LOAD OUT0-11
inputs level, with exception CLK. Overline designates active signals.
FN2810.9 April 2007
HSP45102
PHASE OFFSET ADDER R.P0-1 P0-1 ENPHAC TXFR LOAD 4-DLY R.P0-1 R.ENPHAC R.TXFR R.LOAD MSBs
SINE
2-DLY
OUT0-11
FREQUENCY CONTROL SECTION 64-BIT SHIFT SCLK SFTEN MSB/LSB SEL_L/M FRCTRL 0-31 FRCTRL 32-63
R.LOAD ACCUMULATOR INPUT REGISTER R.TXFR
R.ENPHAC
(HIGH SELECTS FRCTRL0-31, SELECTS FRCTRL32-63) PHASE ACCUMULATOR
FIGURE NCO-12 FUNCTIONAL BLOCK DIAGRAM
Functional Description
NCO12 produces 12-bit sinusoid whose frequency phase digitally controlled. frequency sine wave determined 32-bit words. Selection active word made SEL_L/M. phase output controlled two-bit input P0-1, which used select phase offset 90°, 180°, 270°. shown Block Diagram, NCO12 consists Frequency Control Section, Phase Accumulator, Phase Offset Adder Sine ROM. Frequency Control section serially loads frequency control word into frequency register. Phase Accumulator Phase Offset Adder compute phase angle using frequency control word phase modulation inputs. Sine generates sine computed phase angle. format 12-bit output offset binary.
phase modulation bits P0-1. architecture shown Figure most significant bits 32-bit phase accumulator summed with two-bit phase offset generate 13-bit phase input Sine Rom. value corresponds value 1000 hexadecimal corresponds value 180°. phase accumulator advances phase amount programmed into frequency control register. output frequency equal
(EQ.
(EQ.
Frequency Control Section
Frequency Control Section shown Figure serially loads frequency data into 64-bit, bidirectional shift register. shift direction selected with MSB/LSB input. When this input high, frequency control word input shifted into register first. When MSB/LSB data shifted first. register shifts rising edge SCLK when SFTEN low. timing these signals shown Figures bits frequency register sent Phase Accumulator Section where bits selected control frequency sinusoidal output.
where bits frequency control word that programmed. integer computation. example, control word 20000000 hexadecimal clock frequency 30MHz, then output frequency would fCLK/8, 3.75MHz. frequency control multiplexer selects least significant bits from 64-bit frequency control register when SEL_L/M high, most significant bits when SEL_L/M low. When only frequency word desired, SEL_L/M MSB/LSB must either both high both low. This fact that when frequency control word loaded into shift register first, enters through most significant register. After bits have been shifted they will reside most significant bits 64-bit register. When TXFR asserted, bits selected frequency control multiplexer clocked into phase accumulator
FN2810.9 April 2007
Phase Accumulator Section
phase accumulator phase offset adder compute phase sine wave from frequency control word
HSP45102
input register. each clock, contents this register summed with current contents accumulator step phase. phase accumulator stepping inhibited holding ENPHAC high. phase accumulator loaded with value input register asserting LOAD, which zeroes feedback phase accumulator. phase adder sums encoded phase modulation bits P0-1 output phase accumulator offset phase 90°, 180° 270°. bits encoded produce phase mapping shown Table This phase mapping provided direct connection in-phase quadrature data bits QPSK modulation.
TABLE PHASE MAPPING P0-1 CODING PHASE SHIFT (DEGREES)
Section
section generates 12-bit sine value from 13-bit output phase adder. output format offset binary ranges from hexadecimal, centered around hexadecimal.
SCLK
SFTEN
MSB/LSB
FIGURE FREQUENCY LOADING ENABLED SFTEN
SCLK
SFTEN MSB/LSB
FIGURE FREQUENCY LOADING CONTROLLED SCLK
LOAD TXFR ENPHAC SEL_L/M OUT0-11
DATA
FIGURE TIMING
FN2810.9 April 2007
HSP45102
Absolute Maximum Ratings +25°C
Supply Voltage. +6.0V Input, Output Voltage Applied -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (°C/W) SOIC Package Maximum Junction Temperature +150°C Maximum Storage Temperature Range .-65°C +150°C Pb-free reflow profile .see link below
Operating Conditions
Operating Voltage Range (Commercial, Industrial) +4.75V +5.25V Operating Temperature Range (Commercial) +70°C Operating Temperature Range (Industrial) .-40°C +85°C
Characteristics
Backside Potential
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output HIGH Voltage Output Voltage Input Leakage Current Standby Power Supply Current Operating Power Supply Current SYMBOL VIHC VILC ICCSB ICCOP TEST CONDITIONS 5.25V 4.75V 5.25V 4.75V -400A, 4.75V +2.0mA, 4.75V GND, 5.25V GND, 5.25V, Note 33MHz, 5.25V, Notes UNITS
Capacitance +25°C, Note
PARAMETER Input Capacitance Output Capacitance NOTES: Power supply current proportional operating frequency. Typical rating ICCOP 3mA/MHz. tested, characterized initial design major process/design changes. Output load test load circuit with switch open 40pF. SYMBOL TEST CONDITIONS FREQ 1MHz, Open. measurements referenced device ground UNITS
FN2810.9 April 2007
HSP45102
Electrical Specifications
5.0V ±5%, +70°C, -40°C +85°C (Note (33MHz) PARAMETER Clock Period Clock High Clock SCLK High/Low Setup Time SCLK Going High Hold Time from SCLK Going High Setup Time SFTEN, MSB/LSB SCLK Going High Hold Time SFTEN, MSB/LSB from SCLK Going High Setup Time SCLK High Going High Setup Time P0-1 Going High Hold Time P0-1 from Going High Setup Time LOAD, TXFR, ENPHAC, SEL_L/M Going High Hold Time LOAD, TXFR, ENPHAC, SEL_L/M from Going High Output Delay Output Rise, Fall Time NOTES: testing performed follows: Input levels (CLK Input) 4.0V Input levels (all other inputs) 3.0V; Timing reference levels (CLK) 2.0V; others 1.5V. Output load test load circuit with switch closed 40pF. Output transition measured 1.5V 1.5V. TXFR active, care must taken violate setup hold times data from shift registers have settled before occurs. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. SYMBOL Note Note NOTES (40MHz) UNITS
Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP 1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
FN2810.9 April 2007
HSP45102 Waveforms
P0-1
LOAD, TXFR, ENPHAC, SEL_L/M
OUT0-11
SCLK
MSB/LSB, SFTEN
FIGURE
FN2810.9 April 2007
HSP45102 Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M28.3 (JEDEC MS-013-AE ISSUE
LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 NOTES Rev. 12/93
0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016
0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050
0.10(0.004)
0.05
1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch) Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN2810.9 April 2007

Data Sheet April 2007 FN2810.9 12-Bit Numerically Controlled Osci

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