Data Sheet 2007 FN4156.4 Numerically Controlled Oscillator/ Modul

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Data Sheet 2007 FN4156.4 Numerically Controlled Oscillator/ Modul

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HSP45116A
Data Sheet 2007 FN4156.4
Numerically Controlled Oscillator/ Modulator
Intersil HSP45116A combines high performance quadrature numerically controlled oscillator (NCO) high speed 16-bit Complex Multiplier/Accumulator (CMAC) single This combination functions allows complex vector multiplied internally generated (cos, sin) vector quadrature modulation demodulation. shown Block Diagram, HSP45116A divided into three main sections. Phase/ Frequency Control Section (PFCS) Sine/Cosine Section together form complex NCO. CMAC multiplies output Sine/ Cosine Section with external complex vector. inputs Phase/Frequency Control Section consist microprocessor interface individual control lines. phase resolution PFCS bits, which results frequency resolution better than 0.013Hz 52MHz. output PFCS argument sine cosine. spurious free dynamic range complex sinusoid greater than 90dBc. output vector from Sine/Cosine Section inputs Complex Multiplier/Accumulator. CMAC multiplies this (cos, sin) vector external complex vector accumulate result. resulting complex vectors available through 20-bit output ports which maintain 90dB spectral purity. This result accumulated internally implement accumulate dump filter. quadrature down converter implemented loading center frequency into Phase/Frequency Control Section. signal down converted Vector Input CMAC, which multiplies data rotating vector from Sine/Cosine Section. resulting complex output down converted signal. position widths outputs CMAC Complex Accumulator (ACC) programmable.
Features
CMAC Chip 52MHz Version 32-Bit Frequency Control 16-Bit Phase Modulation 16-Bit CMAC 0.013Hz Tuning Resolution 52MHz Programmable Rounding Option Spurious Frequency Components -90dBc Fully Static CMOS Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Frequency Synthesis Modulation PSK, FSK, Demodulation, Phase Shifter Polar Cartesian Conversions
Ordering Information
PART NUMBER HSP45116AVC-52 PART MARKING HSP45116AVC-52 TEMP. RANGE (°C) PACKAGE MQFP (28mmx28mm) MQFP (28mmx28mm) (Pb-free) PKG. DWG. Q160.28x28 Q160.28x28
HSP45116AVC-52Z (Note) HSP45116AVC-52Z
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. Rights Reserved other trademarks mentioned property their respective owners.
HSP45116A Block Diagram
VECTOR INPUT SINE/ COSINE ARGUMENT
MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS
PHASE/ FREQUENCY CONTROL SECTION
SINE/ COSINE SECTION CMAC
VECTOR OUTPUT
FN4156.4 2007
HSP45116A Pinout
HSP45116A (160 MQFP) VIEW
IMIN1 IMIN2 IMIN3 IMIN4 IMIN5 IMIN6 IMIN7 IMIN8 IMIN9 IMIN10 IMIN11 IMIN12 IMIN13 IMIN14 IMIN15 IMIN16 IMIN17 IMIN18 IO19 IO18 IO17 IO16 IO15 IO14 IO13 IO12 IO11 IO10
IMIN0 RIN18 RIN17 RIN16 RIN15 RIN14 RIN13 RIN12 RIN11 RIN10 RIN9 RIN8 RIN7 RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 RIN0 ENPHREG ENOFREG PEAK RBYTILD BINFMT TICO MOD1 MOD0 PACI LOAD PMSEL
RO19 RO18 RO17 RO16 RO15 RO14 RO13 RO12 RO11 RO10 DET1 DET0
CLROFR ENCFREG ENPHAC ENTIREG MODPI/2PI OUTMUX1 OUTMUX0 OEREXT OEIEXT PACO
FN4156.4 2007
HSP45116A Descriptions
NAME NUMBER 102, 111, 124, 132, 145, 108, 114, 119, 125, 131, 143, 54-61, 63-70 TYPE Power supply input. DESCRIPTION
Power supply ground input.
C0-15 AD0-1
Control input loading phase frequency data into PFCS. MSB. Address pins selecting destination C0-15 data. MSB. Chip select (active low). Write Enable. Data clocked into input register selected AD0-1 rising edge when line low. Clock. registers, except Control Registers clocked with clocked (when enabled) rising edge CLK. Phase Register Enable (active low). Registered chip CLK. When active low, after being clocked onto chip, ENPHREG enables clocking data into Phase Register. Frequency Offset Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENOFREG enables clocking frequency offset data into frequency offset register. Center Frequency Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENCFREG enables clocking data into Center Frequency Register. Phase Accumulator Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENPHAC enables clocking Phase Accumulator Register. Time Interval Control Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENTIREG enables clocking data into Time Accumulator Register. Real Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered chip CLK. When active, after being clocked onto chip, enables clocking data into real imaginary input data register. Modulo Select. When low, Sine Cosine ROMs addressed modulo (360 degrees). When high, most significant address held that ROMs addressed modulo (180 degrees). This input registered chip clock. This control included processing. Frequency Offset Register Output Zero (active low). Registered chip CLK. When active, after being clocked onto chip, CLROFR zeros data path from Frequency Offset Register frequency adder. data still clocked into Frequency Offset Register; CLROFR does affect contents register. Phase Accumulator Load Control (active low). Registered chip CLK. Zeroes feedback path phase accumulator without clearing Phase Accumulator Register. External Modulation Control Bits. When selected with PMSEL line, these bits 180, degree offset current phase phase accumulator. lower bits phase control path zero. These bits loaded into Phase Register when ENPHREG low. MOD1 MOD0 PHASE SHIFT (DEGREES)
ENPHREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
MODPI/2PI
CLROFR
LOAD
MOD0-1
FN4156.4 2007
HSP45116A Descriptions
NAME PMSEL (Continued) TYPE DESCRIPTION Phase Modulation Select Line. This line determines source data clocked into Phase Register. When high, Phase Control Register selected. When low, external modulation pins (MOD0-1) selected most significant bits least significant bits least significant bits zero. This control registered CLK. Bypass, Timer Load (active low). Registered CLK. This input bypasses sine/ cosine that phase adder output lower bits phase accumulator directly CMAC's sine cosine inputs, respectively. also enables loading Timer Accumulator Register zeroing feedback accumulator. Phase Accumulator Carry Input (active low). this causes phase accumulator increment addition values Phase Accumulator Register frequency adder. Phase Accumulator Carry Output. Active registered CLK. this output indicates that phase accumulator overflowed, i.e., sine/cosine cycle been reached. Time Interval Accumulator Carry Output. Active low, registered CLK. This output goes when carry generated time interval accumulator. This function provided time control events such synchronizing register clocking data timing. Real Input Data Bus. RIN18 MSB. This external real component into complex multiplier. clocked into real Input Data Register when asserted. Two's complement. Imaginary Input Data Bus. IMIN18 MSB. This external imaginary component into complex multiplier. clocked into real Input Data Register when asserted. Two's complement. Shift Control Inputs. These lines control input shifters inputs complex multiplier. shift controls common shifters both busses. SELECTED BITS RIN0-15, IMIN0-15 RIN1-16, IMIN1-16 RIN2-17, IMIN2-17 RIN3-18, IMIN3-18
NUMBER
RBYTILD
PACI
PACO
TICO
RIN0-18
2-6, 8-19,
IMIN0-18
138-142, 144, 146-156,
SH0-1
Accumulate/Dump Control. This input controls complex accumulators their holding registers. When high, accumulators accumulate holding registers disabled. When low, feedback accumulators zeroed cause accumulators load. holding registers enabled clock results accumulation. This input registered CLK.
BINFMT
This input used convert two's complement output offset binary (unsigned) applications using converters. When low, bits RO19 IO19 inverted from internal two's complement representation. This input registered CLK. This input enables peak detect feature block floating point detector. When high, maximum growth Output Holding Registers encoded output DET0-1 pins. When PEAK input asserted, block floating point detector output will track maximum growth holding registers, including data Holding Registers time that PEAK activated.
PEAK
FN4156.4 2007
HSP45116A Descriptions
NAME OUTMUX0-1 (Continued) TYPE DESCRIPTION These inputs select data output RO0-19 IO0-19.
NUMBER
RO16-19
RO0-15
IO16-19
IO0-15
Real CMAC Real CMAC Imag CMAC Imag CMAC 31-34 15-30 31-34 15-30 Real CMAC Real Imag CMAC Imag 31-34 CMAC 0-14 31-34 CMAC 0-14 Real 16-19 Reserved Real 0-15 Reserved Imag 16-19 Reserved Imag 0-15 Reserved
RO0-19
84-86, 88-91, 99-101, 103-107, 110, 112, 113, 115-118, 121-123, 126-130, 133-137
Real Output Data Bus. MSB. These three-state outputs controlled OEREXT. OUTMUX0-1 select data output bus.
IO0-19
Imaginary Output Data Bus. MSB. These three-state outputs controlled OEIEXT. OUTMUX0-1 select data output bus.
DET0-1
These output pins indicate number bits growth accumulators. While PEAK low, these pins indicate peak growth. detector examines bits 15-18, real imaginary accumulator holding registers bits 30-33 real imaginary CMAC Holding Registers. bits indicate largest growth four registers. NUMBER BITS GROWTH ABOVE
OEREXT OEIEXT
Three-state control bits RO0-15. Outputs enabled when line low. Three-state control bits RO16-19. Outputs enabled when line low. Three-state control bits IO0-15. Outputs enabled when line low. Three-state control bits IO16-19. Outputs enabled when line low. Round Enable. This input enables rounding output data precision from bits. This input active "low". This input must tied either high low.
FN4156.4 2007
HSP45116A Functional Description
Numerically Controlled Oscillator/Modulator (NCOM) produces digital complex sinusoid waveform whose amplitude, phase frequency controlled input command words. When used Numerically Controlled Oscillator (NCO), generates 16-bit sine cosine vectors maximum sample rate 40MHz. NCOM preprogrammed produce constant (CW) sine cosine output Direct Digital Synthesis (DDS) applications. Alternatively, phase frequency inputs updated real time produce PSK, FSK, modulated waveform. Complex Multiplier/ Accumulator (CMAC) used multiply this waveform input signal signals. stepping phase input, output becomes twiddle factor; when data input Vector Inputs (see Block Diagram), NCOM calculates butterfly. shown Block Diagram, NCOM consists three parts: Phase Frequency Control Section (PFCS), Sine/Cosine Generator, CMAC. PFCS stores phase frequency inputs uses them calculate phase angle rotating complex vector. Sine/Cosine Generator performs lookup this phase outputs appropriate values sine cosine. sine cosine form inputs CMAC, which multiplies them input vector form modulated output. outputs CMAC rounded different widths. Phase Accumulator Time Accumulator work same principle: 32-bit word added contents 32-bit accumulator register every clock cycle; when causes adder overflow, accumulation continues with bits adder going into Accumulator Register. overflow used output indicate timing accumulation overflows. Time Accumulator, overflow generates TICO, Time Accumulator carry (which only output Time Accumulator). Phase Accumulator, overflow inverted generate Phase Accumulator Carry Out, PACO. output Phase Accumulator goes Phase Adder, which adds offset bits phase. This 32-bit number forms argument sine cosine, which passed Sine/Cosine Generator. Both accumulators loaded bits time over C0-15 bus. Data C0-15 loaded into three input registers when low. data Most Significant Input Register Least Significant Input Register forms 32-bit word that input Center Frequency Register, Offset Frequency Register Time Accumulator. These registers loaded enabling proper register enable signal; example, load Center Frequency Register, data loaded into Input Registers, ENCFREG zero; next rising edge will pass registered version ENCFREG, R.ENCFREG, clock enable Center Frequency Register; this register then gets loaded following rising edge CLK. contents Input Registers will continuously loaded into Center Frequency Register long R.ENCFREG low. Phase Register loaded similar manner. Assuming PMSEL high, contents Phase Input Register loaded into Phase Register every rising clock edge that R.ENPHREG low. PMSEL low, MOD0-1 supply most significant bits into Phase Register (MOD1 MSB) least significant bits loaded with MOD0-1 used generate Quad Phase Shift Keying (QPSK) signal (Table
TABLE AD0-1 DECODING FUNCTION Load least significant bits frequency input. Load most significant bits frequency input. Load phase register. Reserved. Operation.
Phase Frequency Control Section
phase frequency internally generated sine cosine controlled PFCS (Figure PFCS generates 32-bit word that represents current phase sine cosine waves being generated: Sine/ Cosine Argument. Stepping this phase angle from through full scale (232 corresponds phase angle sinusoid starting advancing around unit circle counterclockwise. PFCS automatically increments phase preprogrammed amount every rising edge external clock. value phase step (which Center Offset Frequency Registers)
Signal Frequency Phase Step Clock Frequency
where Signal Frequency complement number. sign will output vector notation Upper Sideband (USB) lower Sideband (LSB) applications. PFCS divided into sections: Phase Accumulator uses data C0-15 compute phase angle, that input Sine/Cosine Section (Sine/ Cosine Argument); Time Accumulator supplies pulse mark passage preprogrammed period time.
FN4156.4 2007
HSP45116A
RIN(18:0) MOD(1:0) PHASE INPUT REGISTER C(15:0) PHEN ENCODE
PHASE REGISTER
R.ENPHREG
R.PMSEL
INPUT REGISTER
CENTER FREQUENCY REGISTER OFFSET FREQUENCY REGISTER
FREQUENCY ADDER SIN/COS ARGUMENT
MSEN
PHASE
INPUT REGISTER
R.ENCFREG
AD(1:0)
SINE/COSINE GENERATOR
DECODER
LSEN
R.ENOFREG
R.CLROFR R.PMSEL PMSEL ENPHREG ENCFREG ENOFREG CLROFR LOAD ENPHAC MODPI/2PI RBYTILD ENTIREG R.ENPHREG R.ENCFREG R.ENOFREG R.CLROFR R.LOAD R.ENPHAC R.MODPI/2PI R.RBYTILD R.ENTIREG PACO PHASE ACCUMULATOR
PHASE ADDER
PHASE ACCUMULATOR ADDER
PHASE ACCUMULATOR REGISTER
MSBs
R.ENPHAC LSBs R.LOAD PACI
PACI R.MODPI/2PI SH(1:0) PEAK BINFMT OEIEXT OEREXT OUTMUX(1:0) TIME ACCUMULATOR REGISTER CARRY TICO R.SH(1:0) R.ENI R.ACC R.PEAK R.BINFMT R.RBYTILD R.SH(1:0) R.ENI R.ACC R.PEAK R.BINFMT
ADDER
TIME INCREMENT
R.ENTIREG TIME ACCUMULATOR TICO PACO
FIGURE HSP45116A BLOCK DIAGRAM
FN4156.4 2007
HSP45116A
R.ENI
RIN0-18 SHIFTER
IMIN0-18 SHIFTER
R.SH(1:0)
PHASE
COMPLEX MULTIPLIER
ADDER R1.ACC
ADDER
R.RBYTILD
COMPLEX ACCUMULATOR
R2.ACC
ROUND
ADDER
ADDER
ROUND CMAC ACCUMULATOR
R1.ACC
R.PEAK R.PEAK
R.ACC
R.BINFMT R.SH(1:0) R.ENI OEIEXT OEREXT
R.BINFMT
R.ENI
OUTMUX(1:0)
RO(19-16)
RO(15:0)
DET(1:0)
IO(19-16)
IO(15:0)
FIGURE HSP45116A BLOCK DIAGRAM (Continued)
FN4156.4 2007
R.SH(1:0)
OUTMUX(1:0) TABLE
GROWTH DETECT
OUTMUX(1:0) TABLE
HSP45116A
Phase Accumulator consists registers adders that compute value current phase every clock. three inputs: Center Frequency, which corresponds carrier frequency signal; Offset Frequency, which deviation from Center Frequency; Phase, which 16-bit number that added current phase modulation schemes. These three values used Phase Accumulator Phase Adder form phase internally generated sine cosine. values Center Offset Frequency Registers corresponds desired phase increment (modulo 232) from clock next. example, loading both registers with zero will cause Phase Accumulator zero current output; output PFCS will remain current value; i.e., output NCOM will signal. hexadecimal 00000001 loaded into Center Frequency Control Register, output PFCS will increment after every clock. This will step through every location Sine/Cosine Generator, that output will lowest frequency above that generated NCOM, i.e., clock frequency divided 232. input Center Frequency Control Register 80000000, PFCS will step through Generator with half maximum step size, that frequency output waveform will half sample rate. operation Offset Frequency Control Register identical that Center Frequency Control Register; having separate registers allows user generate signal loading carrier frequency Center Frequency Control Register updating Offset Frequency Control Register with value frequency offset difference between carrier frequency frequency output signal. logic CLROFR disables output Offset Frequency Register without clearing contents register.
TABLE MOD0-1 DECODE MOD1 MOD0 PHASE SHIFT (DEGREES)
Phase Register adds offset output Phase Accumulator. Since Phase Register only bits, added bits Phase Accumulator. Time Accumulator consists register which incremented every clock. amount which increments loaded into Input Registers latched into Time Accumulator Register rising edges while ENTIREG low. output Time Accumulator accumulator carry out, TICO. TICO used timer enable periodic sampling output NCOM. number programmed into this register equals period/desired time interval. TICO disabled phase initialized zeroing feedback path accumulator with RBYTILD.
Sine/Cosine Section
Sine/Cosine Section (Figure converts output PFCS into appropriate values sine cosine. takes most significant bits PFCS output passes them through look table form 16-bit sine cosine inputs CMAC.
SIN/COS ARGUMENT SINE/COSINE GENERATOR
R.RBYTILD
FIGURE SINE/COSINE SECTION
20-bit word maps into radians that angular resolution 2/220. address zero corresponds radians address FFFFF corresponds (2/220) radians. outputs Generator Section complement sine cosine values. sine cosine outputs range from hexadecimal 8001, which represents negative full scale 7FFF, which represents positive full scale. Note that normal range two's complement numbers 8000 7FFF; output range SIN/COS generator scaled that symmetric about sine cosine values computed reduce amount needed. magnitude error computed value complex vector less than -90.2dB. error sine cosine alone approximately better. RBYTILD low, output PFCS goes directly inputs CMAC. real imaginary inputs CMAC programmed 7FFF respectively, then output PFCS will appear output bits
Initializing Phase Accumulator Register done putting LOAD line. This zeroes feedback path accumulator, that register loaded with current value phase increment summer next clock. final phase value going Generator adjusted using MODPI/2PI force range phase 180o (modulo 360o (modulo Modulo mode used modulation, demodulation, direct digital synthesis, etc. Modulo used calculate FFTs. This explained greater detail Applications Section.
FN4156.4 2007
HSP45116A
through NCOM, with output multiplexers bring most significant bits CMAC output (OUTMUX 00). most significant bits PFCS appears IOUT0-15 least significant bits come ROUT0-15.
TABLE OUTPUT MULTIPLEXER SELECTION
RO16-19
RO0-15
IO16-19
IO0-15
Complex Multiplier/Accumulator
CMAC (Figure performs types functions: complex multiplication/accumulation modulation demodulation digital signals, operations necessary implement butterfly. Modulation demodulation implemented using complex multiplier associated accumulator; rest circuitry this section, i.e., complex accumulator, input shifters growth detect logic used along with complex multiplier/accumulator FFTs. complex multiplier performs complex vector multiplication output Sine/Cosine Section vector represented real imaginary inputs IIN. vectors combined following manner: ROUT IOUT latched into Input Registers passed through shift stages. Clocking Input Registers enabled with ENI. amount shift latched data programmed with SH0-1 (Table output shifters sent CMAC auxiliary accumulators.
TABLE INPUT SHIFT SELECTION SELECTED BITS RIN0-15, IMIN0-15 RIN1-16, IMIN1-16 RIN2-17, IMIN2-17 RIN3-18, IMIN3-18
Real CMAC Real CMAC Imag CMAC Imag CMAC 31-34 15-30 31-34 15-30 Real CMAC Real Imag CMAC Imag 31-34 CMAC 0-14 31-34 CMAC 0-14 Real 16-19 Reserved Real 0-15 Reserved Imag 16-19 Reserved Imag 0-15 Reserved
Complex Accumulator duplicates accumulator CMAC. input comes from data shifters, 20-bit complex output goes Multiplexer. controls whether accumulator enabled not. OUTMUX0-1 determines whether accumulator output appears ROUT IOUT. Growth Detect circuitry outputs value that signifies amount growth data CMAC Complex Accumulator. output, DET0-1, encoded shown Table PEAK low, highest value DET0-1 latched Growth Detect Output Register. relative weighting bits inputs outputs CMAC shown Figure Note that binary point sine, cosine, right most significant bit, while binary point right fifth most significant bit. These CMAC external input output busses aligned with each other facilitate cascading NCOMs applications.
TABLE GROWTH ENCODING NUMBER BITS GROWTH ABOVE
33-bit real imaginary outputs Complex Multiplier latched Multiplier Registers then through Accumulator Section CMAC. line high, feedback accumulators enabled; zeroes feedback path, that next real imaginary data complex multiplier stored CMAC Output Registers. data CMAC Output Registers goes Multiplexer, output which determined OUTMUX0- lines (Table BINFMT controls whether output Multiplexer presented two's complement unsigned format; BINFMT inverts ROUT19 IOUT19 unsigned output, while BINFMT selects two's complement.
FN4156.4 2007
HSP45116A
SIN/COS INPUT 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN) 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, OUTMUX 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, OUTMUX 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30
COMPLEX ACCUMULATOR OUTPUT (RO, OUTMUX 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point FIGURE WEIGHTING
FN4156.4 2007
HSP45116A Rounding
operation HSP45116A identical HSP45116 with exception programmable rounding option added data outputs. added functionality achieved using HSP45116's reserved Configuration Registers specify rounding precision replacing with round enable (RND) input. When "high", rounding disabled, HSP45116A functions pin-for-pin equivalent HSP45116. When active "low" rounding enabled. input replaces Lead MQFP package seen Pinout Diagram. Round Control Register loaded placing round control value C15-0, setting AD1-0 setting forcing high transition input. rounding operation determined least significant bits loaded into Control Register shown Table least significant four bits (C3-0) loaded into register govern rounding real imaginary outputs Complex Accumulator (ACC). next more significant four bits (C7-4) govern rounding complex outputs complex multiply accumulator (CMAC). real imaginary outputs from CMAC rounded same precision. rounding perform adding "one" position below least significant desired output. example, configuration that rounds most significant bits CMAC output, "one" would added position 2-14 (See Figure output weightings).
TABLE ROUNDING CONTROL ROUND CONTROL REGISTER C15-8 C7-4 CMAC ROUNDING 0000 0001 C3-0 ROUNDING 0000 0001 Rounding CMAC outputs rounded most significant bits, positions 2-15 outputs rounded most significant bits, positions 2-15 CMAC outputs rounded most significant bits, positions 2-14 outputs rounded most significant bits, positions 2-14 CMAC outputs rounded most significant bits, positions 2-13 outputs rounded most significant bits, positions 2-13 CMAC outputs rounded most significant bits, positions 2-12 outputs rounded most significant bits, positions 2-12 CMAC outputs rounded most significant bits, positions 2-11 outputs rounded most significant bits, positions 2-11 CMAC outputs rounded most significant bits, positions 2-10 outputs rounded most significant bits, positions 2-10 CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions CMAC outputs rounded most significant bits, positions outputs rounded most significant bits, positions Undefined
UNUSED XXXXXXXX XXXXXXXX
ROUNDING OPERATION
XXXXXXXX
0010
0010
XXXXXXXX
0011
0011
XXXXXXXX
0100
0100
XXXXXXXX
0101
0101
XXXXXXXX
0110
0110
XXXXXXXX
0111
0111
XXXXXXXX
1000
1000
XXXXXXXX
1001
1001
XXXXXXXX
1010
1010
XXXXXXXX
1011
1011
XXXXXXXX
1100
1100
XXXXXXXX
1101-1111
1101-1111
FN4156.4 2007
HSP45116A Applications
NCOM used Amplitude, Phase Frequency modulation, well variations combinations these techniques, such QAM. most effective applications requiring multiplication rotating complex sinusoid external vector. These include modulators digital receivers. NCOM implements modulation single chip, element demodulation, where performs complex down conversion. combined with Intersil HSP43220 Decimating Digital Filter form front digital receiver. Phase/Frequency Control Section, frequency tuning resolution equals clock frequency divided 232. example, 25MHz clock gives tuning resolution 0.006Hz.
IMIN CENTER FREQUENCY NCOM SINE/COSINE GENERATOR PFCS CMAC
Modulation/Demodulation
Figure shows block diagram modulator. this example, phase increment carrier frequency loaded into Center Frequency Register, modulating input clocked into real input CMAC, with imaginary input modulated output obtained real output CMAC. With sixteen bit, two's complement signal input, output will 16-bit real number, ROUT0-15 (with OUTMUX 00).
SIGNAL INPUT CENTER FREQUENCY XMTR
FIGURE QUADRATURE AMPLITUDE MODULATION (QAM)
SINE/COSINE GENERATOR
PFCS
CMAC
NCOM also works with HSP43220 Decimating Digital Filter implement down conversion pass filtering digital receiver (Figure NCOM performs complex down conversion wideband input signal multiplying input vector internally generated complex sinusoid. resulting signal components twice center frequency HSP43220s, each real imaginary outputs HSP45116A, perform pass filtering decimation down converted data, resulting complex baseband signal.
HSP45116A NCOM (wt) HSP43220
NCOM MODULATED OUTPUT XMTR
FIGURE AMPLITUDE MODULATION
replacing real input with complex vector, similar setup generate signals (Figure this case, carrier frequency loaded into Center Frequency Register before, modulating vector carries both amplitude phase information. Since input vector internally generated sine cosine waves both bits, number states only limited characteristics transmission medium analog electronics transmitter receiver. phase amplitude resolution Sine/Cosine Section (16-bit output), delivers spectral purity greater than 90dBc. This means that unwanted spectral components phase uncertainty (phase noise) will greater than 90dB below desired output (dBc, decibels below carrier). With 32-bit phase accumulator
SAMPLED INPUT DATA
(wt)
INPUT
NCOM OUTPUT
OUTPUT
10MHz
20MHz
FIGURE CHANNELIZED RECEIVER CHIP
FN4156.4 2007
HSP45116A
Absolute Maximum Ratings
Supply Voltage +7.0V Input, Output Voltage Applied -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (°C/W) MQFP Package 38.0 Maximum Junction Temperature +150°C Maximum Storage Temperature Range .-65°C +150°C Pb-free reflow profile .see link below
Operating Conditions
Voltage Range +4.75V +5.25V Temperature Range +70°C
Characteristics
Gate Count 26,000 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical Input Voltage Logical Zero Input Voltage Logical Input Voltage: Logical Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance NOTES:
5.0V ±5%, +70°C SYMBOL ICCOP ICCSB VIHC COUT TEST CONDITIONS Max, Frequency 52.6MHz Notes Max, Outputs Loaded Max, Input Max, Input -5mA, 5mA, Frequency 1MHz measurements referenced GND. +25°C, Note UNITS
Power supply current proportional frequency. Typical rating 3.5mA/MHz. Output load test circuit 40pF. tested, characterized initial design major process/design changes.
Electrical Specifications
PARAMETER Period High High Setup Time AD0-1, Hold Time AD0-1, from Setup Time C0-15 Hold Time C0-15 from
5.0V ±5%, +70°C (Note 52.6MHz (-52) SYMBOL tAWS tAWH tCWS tCWH NOTES UNITS
FN4156.4 2007
HSP45116A
Electrical Specifications
PARAMETER Setup Time Setup Time MOD0-1 Hold Time MOD0-1 from Setup Time PACI Hold Time PACI from Setup Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD Hold Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from Setup Time RIN0-18, IMIN0-18 Hold Time RIN0-18, IMIN0-18 from Output Delay RO0-19, IO0-19 Output Delay DET0-1 Output Delay PACO Output Delay TICO Output Enable Time OER, OEI, OEREXT, OEIEXT Output Enable Time OUTMUX0-1 Output Disable Time Output Rise, Fall Time NOTES: tests performed with 40pF, 2.0mA, -0.4mA. Input reference level 2.0V, other inputs 1.5V. Test 3.0V, VIHC 4.0V, 1.5V, 1.5V. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. Applicable only when outputs being monitored ENCFREG, ENPHREG ENTIREG active. always asynchronous when active. 5.0V ±5%, +70°C (Note (Continued) 52.6MHz (-52) SYMBOL tMCS tMCH tPCS tPCH tECS NOTES UNITS
tECH
tDEO
Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP 1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
FN4156.4 2007
HSP45116A Waveforms
tMCS MOD0-1 tPCS PACI tECS CONTROL INPUTS RIN0-19 IIN0-19 ROUT0-19 IOUT0-19 tDEO DET0-1 PACO TICO tECH tPCH tMCH
FIGURE INPUT OUTPUT TIMING
tAWS tAWS AD0-1 tCWS C0-15
tAWH
tAWH
tCWH
FIGURE CONTROL TIMING
FN4156.4 2007
HSP45116A Waveforms
(Continued)
OEREXT OEIEXT
1.5V
OUTMUX0-1 1.5V RO0-19 HIGH IMPEDANCE IO0-19
RO0-19 IO0-19
HIGH IMPEDANCE
1.7V 1.3V
FIGURE OUTPUT ENABLE, DISABLE TIMING
FIGURE MULTIPLEXER TIMING
2.0V 0.8V
FIGURE OUTPUT RISE FALL TIMES
FN4156.4 2007
HSP45116A Metric Plastic Quad Flatpack Packages (MQFP)
Q160.28x28 (JEDEC MS-022DD-1 ISSUE
LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL
SEATING PLANE 0.076 0.003
MILLIMETERS 0.25 3.20 0.22 0.22 31.08 27.88 31.10 27.90 0.73 0.65 4.10 3.60 0.38 0.33 31.32 28.12 31.30 28.10 1.03 NOTES Rev. 4/99
0.010 0.126 0.009 0.009 1.223 1.097 1.224 1.098 0.029
0.161 0.142 0.015 0.013 1.233 1.107 1.232 1.106 0.040
0.026
NOTES: Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. dimensions tolerances ANSI Y14.5M-1982. Dimensions determined seating plane Dimensions determined datum plane Dimensions include mold protrusion. Allowable protrusion 0.25mm (0.010 inch) side. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total. number terminal positions.
0.40 0.016 0o-7o
12o-16o 0.20 0.008
0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 0.13/0.23 0.005/0.009
12o-16o
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FN4156.4 2007

Data Sheet 2007 FN4156.4 Numerically Controlled Oscillator/ Modul

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