SMBus System Clock Buffer Mobile Applications output buffers high

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SMBus System Clock Buffer Mobile Applications output buffers high

Datasheet Thumbnail

Top Searches for this datasheet

SC660E
SMBus System Clock Buffer Mobile Applications
output buffers high clock fanout applications Each output internally disabled power consumption reduction. Separate power supply each group clock outputs mixed voltage application. 250ps skew between output clocks. 28-pin SSOP package minimum board space Single output Tristate testability
Product Description
device high fanout system clock distributor. primary application create large quantity clocks needed support wide range clock loads that referenced single existing clock. Loads supported. Primary application this component where long traces used transport clocks from their generating devices their loads. creation degradation waveform rise fall times greatly reduced running single reference clock trace this device then using regenerate clock that drives shorter traces using SC660 generate clocks target devices therefore minimized board real estate saved.
Block Diagram
VDDB
Configuration
SDRAM(0:1)
SDRAM(2:3)
SDRAM4 SDRAM5
SDATA SCLOCK
SDRAM(6:7) SDRAM(8:9)
VDDB SDRAM0 SDRAM1 VDDB SDRAM2 SDRAM3 VDDB SDRAM4 SDATA
VDDB SDRAM9 SDRAM8 VDDB SDRAM7 SDRAM6 VDDB SDRAM5 SCLOCK
1.0, December 2006
2200 Laurelwood Road, Santa Clara, 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page
www.SpectraLinear.com
SC660E
Description
2,3,6,7,11,18,22,23 ,26,27 Name Sdram(0:9) VddB Type BUF1 Description This connected input reference clock. This clock must range 10.0 100.0 Mhz. skew output clocks. Buffer Output Enable pin. This used place output clocks (CLK1:10) state condition. This feature facilitates production board level testing easily implemented clocks that this device produces. internal pull-up resistor. Serial Data SMBus control interface. This receives data streams from SMBus outputs acknowledge valid data. Serial Clock SMBus control interface. Ground pins clock output buffers. These pins must returned same potential reduce output clock skew. Power output clock buffers. device core logic.
Sdata
Sclock VddB
Maximum Ratings[1]
Input Voltage Relative VSS:.VSS-0.3V Input Voltage Relative VDDQ AVDD: VDD+0.3V Storage Temperature: Operating Temperature:. Maximum Power Supply: 3.5V This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Note: voltage input cannot exceed power during power-up. Power supply sequencing required.
1.0, December 2006
Page
SC660E
2-Wire SMBus Control Interface
2-wire control interface implements write only slave interface. device cannot read back. Sub-addressing supported, thus preceding bytes must sent order change control bytes. 2-wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with Read/Write LSB. Data transferred first. device will respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. device will respond other control interface conditions. Previously control registers retained.
Serial Control Registers
Following acknowledge Address Byte, additional bytes must sent: "Command Code byte, "Byte Count" byte. Although data (bits) command considered "don't care"; must sent will acknowledged. After Command Code Byte Count have been acknowledged, sequence (Byte Byte Byte described below will valid acknowledged.
Byte Function Select Register enable, Stopped)
@Pup Pin# reserved reserved reserved reserved SDRAM3 (Active Forced SDRAM2 (Active Forced SDRAM1 (Active Forced SDRAM0 (Active Forced Description
Byte Clock Register enable, Stopped)
@Pup Pin# Description SDRAM9 (Active Forced SDRAM8 (Active Forced SDRAM7 (Active Forced SDRAM6 (Active Forced reserved reserved reserved reserved
Byte Clock Register enable, Stopped
@Pup Pin# Description
SDRAM5 (Active Forced
SDRAM4 (Active Forced Used Used Used Used Used Used
1.0, December 2006
Page
SC660E
Electrical Characteristics
Parameter Idd66 Idd100 Isdd Static Supply Current Short Circuit Current Input Rise Time Description Input Voltage Input High Voltage Input Current Input High Current Output Voltage 40mA Output High Voltage 30mA Tri-State leakage Current Dynamic Supply Current Min. Typ. Max. Units Input frequency outputs load Input frequency outputs load outputs disabled input clock output time seconds volts Outputs (see buffer spec) Outputs Using 3.3V Power (see buffer spec) Conditions
VDD1 thru VDD5 =3.3V
Switching Characteristics
Parameter tSKEW tSKEW TJCC Description Output Duty Cycle Buffer out/out Skew Buffer Outputs Buffer input output Skew Jitter Cycle Cycle Jitter Absolute (Peak Peak)[2] Min. Typ. Max. Units loading loading Conditions Measured 1.5V (50/50 Load Measured 1.5V
VDD1 thru VDD5 =3.3V
TB40_ Type Buffer Characteristics (All Clock Outputs)
Parameter IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Description Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise/Fall Time Between Rise/Fall Time Between Min. Typ. Max. 1.33 1.33 Units Ohms Vout 1.5V Vout Vout 1.2V Load Load Conditions Vout
VDD1 thru VDD5 =3.3V
Note: This jitter additive input clock's jitter.
1.0, December 2006
Page
SC660E
Ordering Information
Part Number SC660EYB 28-pin SSOP Package Type Product Flow Commercial,-40
Package Diagrams
28-Lead (5.3 Shrunk Small Outline Package
1.14 1.14 DIA.
1.14 7.50 8.10
DIMENSIONS MILLIMETERS MIN. MAX.
10.00 10.40
SEATING PLANE 0.65 BSC.
.235 MIN. GAUGE PLANE 2.00 MAX. 1.65 1.85 0.05 0.21 0.25
MIN.
0.10
0.22 0.38
5.00 5.60 1.25 REF. 0.55 0.95
0°-8°
51-85079-*C
While reviewed information herein accuracy reliability, Spectra Linear Inc. assumes responsibility circuitry infringement patents other rights third parties which would result from each use. This product intended normal commercial applications warranted intended life support, critical medical instruments, other application requiring extended temperature range, high reliability, other extraordinary environmental requirements unless pursuant additional processing Spectra Linear Inc., expressed written agreement Spectra Linear Inc. Spectra Linear Inc. reserves right change circuitry specification without notice.
1.0, December 2006
Page

SMBus System Clock Buffer Mobile Applications output buffers high

Top Searches for this datasheet

Other recent searches