TAXITM-compatible HOTLink® Transceiver Second-generation HOTLink®
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CY7C9689A
TAXITM-compatible HOTLink® Transceiver
Second-generation HOTLink® technology AMDAM7968/7969 TAXIchipTM-compatible 8-bit 4B/5B 10-bit 5B/6B NRZI encoded data transport 10-bit 12-bit NRZI pre-encoded (bypass) data transport Synchronous parallel interface Embedded/bypassable 256-character Transmit Receive FIFOs 200-MBaud serial signaling rate Internal phase-locked loops (PLLs) with external components Dual differential PECL-compatible serial inputs outputs Compatible with fiber-optic modules copper cables Built-In Self-Test (BIST) link testing Link Quality Indicator Single +5.0V ±10%supply 100-pin TQFP Pb-Free package option available FIFO encoded using embedded 4B/5B 5B/6B encoders improve serial transmission characteristics. These encoded characters then serialized, converted NRZI, output from PECL-compatible differential transmission line drivers bit-rate either times input reference clock 8-bit 10-bit bypass) mode, times reference clock 10-bit 12-bit bypass) mode. receive section CY7C9689A HOTLink accepts serial bit-stream from PECL compatible differential line receivers and, using completely integrated Clock Synchronizer, recovers timing information necessary data reconstruction. recovered stream converted from NRZI NRZ, deserialized, framed into characters, 4B/5B 5B/6B decoded, checked transmission errors. recovered 10-bit decoded characters then written internal Receive FIFO, presented destination host system. integrated 4B/5B 5B/6B encoder/decoder bypassed (disabled) systems that present externally encoded scrambled data parallel interface. With encoder bypassed, pre-encoded parallel data stream converted from serial NRZI stream. embedded FIFOs also bypassed (disabled) create reference-locked serial transmission link. those systems requiring even greater FIFO storage capability, external FIFOs directly coupled CY7C9689A through parallel interface without need additional glue-logic. parallel interface configured either FIFO (configurable depth expansion through external FIFOs) pipeline register extender. FIFO configurations optimized transport time-independent (asynchronous) 10-bit character-oriented data across link. Built-In Self-Test (BIST) pattern generator checker allows testing high-speed serial data paths both transmit receive sections, across interconnecting links. HOTLink devices ideal variety applications where parallel interfaces replaced with high-speed, point-to-point serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, video transmission equipment.
Functional Description
CY7C9689A HOTLink Transceiver point-to-point communications building block allowing transfer data over high-speed serial links (optical fiber, balanced, unbalanced copper transmission lines) speeds ranging between MBaud. transmit section accepts parallel data selectable widths converts serial data, while receiver section accepts serial data converts parallel data selectable widths. Figure illustrates typical connections between independent host systems corresponding CY7C9689A parts. CY7C9689A provides enhanced technology, increased functionality, higher level integration, higher data rates, lower power dissipation over AM7968/7969 TAXIchip products. transmit section CY7C9689A HOTLink configured accept either 10-bit data characters each clock cycle, stores parallel data into internal synchronous Transmit FIFO. Data read from Transmit
Figure HOTLink System Connections
Decoder 4B/5B, 5B/6B
Encoder 4B/5B, 5B/6B
Framer Deserializer
Serializer
FIFO Receive
Data Receive System Host Control Status
Serial Link
Transmit FIFO
Transmit Data System Host
CY7C9689A Encoder 4B/5B, 5B/6B Serializer FIFO Transmit
CY7C9689A Decoder 4B/5B, 5B/6B Deserializer Framer Receive FIFO
Control Status Receive Data
Data Transmit
Serial Link
Cypress Semiconductor Corporation Document 38-02020 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised September 2006
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CY7C9689A
TAXIHOTLink Transceiver Logic Block Diagram
STATUS TXDATA/TXCMD CONTROL Mode Control TXCLK MODE REFCLK Output Register STATUS RXDATA/RXCMD RXCLK
Output Register
Flags Mode
Input Register
Receive FIFO Flags Transmit FIFO Transmit Clock Multiplier
Pipeline Register
CONTROL TXEN RXEN TXHALT TXRST RXRST RFEN TXBISTEN RXBISTEN RESET MODE RANGESEL SPDSEL RXMODE[1:0] FIFOBYP EXTFIFO ENCBYP BYTE8/10 TEST Clock Divider RXSTATUS RXEMPTY RXHALF RXFULL STATUS TXEMPTY TXHALF TXFULL
Pipeline Register
Receive Control State Machine
BIST LFSR 4B/5B, 5B/6B Decoder
BIST LFSR 4B/5B, 5B/6B Encoder
Transmit Control State Machine
Deserializer Framer
Serial Shifter
Clock Routing Matrix
Receive Clock/Data Recovery
Clock
Signal Validation
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OUTA OUTB CURSETB CURSETA
CARDET Page
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CY7C9689A
Configuration
RXBISTEN CURSETB CURSETA CARDET OUTB+ OUTB- OUTA+ OUTA-
VDDA
VDDA
VDDA
VDDA
VDDA
VSSA
VSSA
VDDA
VSSA
VSSA
VSSA
VSSA
INA+
INB+
INA-
TEST VLTN TXBISTEN RXCLK TXHALT RXFULL REFCLK TXRST TXEN RXHALF TXSC/D RXEMPTY TXDATA[0] RXDATA[11]/RXCMD[1] RXMODE[1] RXMODE[0]
INB-
VSSA
SPDSEL RANGESEL RFEN TXFULL TXHALF RXEN TXCLK RXRST RXSC/D RXDATA[0] TXEMPTY RXDATA[1] TXCMD[1] TXCMD[0] TXDATA[9]/TXCMD[2] RXDATA[2] RESET
CY7C9689A
RXDATA[9]/RXCMD[2]
RXDATA[8]/RXCMD[3]
RXDATA[10]/RXCMD[0]
TXDATA[8]/TXCMD[3]
RXDATA[7]
RXDATA[6]
RXDATA[5]
RXDATA[4]
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RXDATA[3]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
BYTE8/10
FIFOBYP
ENCBYP
EXTFIFO
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CY7C9689A
Descriptions
Name TXCLK Characteristics clock input Internal Pull-up Signal Description Transmit FIFO Clock. Used sample Transmit FIFO related interface signals. Transmit Path Signals
TXDATA[7:0]
input, sampled Parallel Transmit DATA Input. TXCLK REFCLK When selected TXEN asserted), information these inputs Internal Pull-up processed DATA when TXSC/D ignored otherwise. When encoder bypassed (ENCBYP LOW), TXDATA[7:0] functions least significant eight bits 12-bit pre-encoded transmit character. When Transmit FIFO enabled (FIFOBYP HIGH), these inputs sampled rising edge TXCLK. When Transmit FIFO bypassed (FIFOBYP LOW) these inputs captured rising edge REFCLK. input, sampled Parallel Transmit DATA COMMAND Input. TXCLK REFCLK When selected, BYTE8/10 HIGH, encoder enabled (ENCBYP Internal Pull-up HIGH), information these inputs processed TXCMD[2:3] TXSC/D HIGH ignored otherwise. When selected, BYTE8/10 LOW, encoder enabled (ENCBYP HIGH), information these inputs processed TXDATA[9:8] TXSC/D ignored otherwise. When encoder bypassed (ENCBYP LOW), TXDATA[9:8] functions 10th bits 12-bit pre-encoded transmit character. When Transmit FIFO enabled (FIFOBYP HIGH), these inputs sampled rising edge TXCLK. When Transmit FIFO bypassed (FIFOBYP LOW), these inputs captured rising edge REFCLK. input, sampled Parallel Transmit COMMAND Input. TXCLK REFCLK When selected encoder enabled (ENCBYP HIGH), information these inputs processed COMMAND when TXSC/D HIGH ignored Internal Pull-up otherwise. When BYTE8/10 HIGH encoder bypassed (ENCBYP LOW), TXCMD[1:0] inputs ignored. When BYTE8/10 when encoder bypassed (ENCBYP LOW), TXCMD[1:0] inputs function 11th 12th (MSB) bits 12-bit pre-encoded transmit character. When Transmit FIFO enabled (FIFOBYP HIGH), these inputs sampled rising edge TXCLK. When Transmit FIFO bypassed (FIFOBYP LOW), these inputs sampled rising edge REFCLK. input, sampled COMMAND DATA input selector. TXCLK REFCLK When selected, BYTE8/10 HIGH, encoder enabled (ENCBYP Internal Pull-up HIGH), this input selects DATA COMMAND inputs processed. TXSC/D HIGH, value TXCMD[3:0] captured sixteen possible COMMANDs, data TXDATA[7:0] bits ignored. TXSC/D LOW, information TXDATA[7:0] captured possible 8-bit DATA values, information TXCMD[3:0] ignored. When BYTE8/10 encoder enabled (ENCBYP HIGH) this input selects DATA COMMAND inputs processed. TXSC/D HIGH, information TXCMD[1:0] captured four possible COMMANDs, information TXDATA[9:0] bits ignored. TXSC/D LOW, information TXDATA[9:0] captured 1024 possible 10-bit DATA values, information TXCMD[1:0] ignored. When encoder bypassed (ENCBYP LOW) TXSC/D ignored
TXDATA[9:8]/ TXCMD[2:3]
TXCMD[1:0]
TXSC/D
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Descriptions (continued)
Name TXEN Characteristics Signal Description input, sampled Transmit Enable. TXCLK REFCLK TXEN sampled rising edge TXCLK REFCLK input enables Internal Pull-up parallel data write operations (when selected). device selected when TXEN asserted during clock cycle immediately following which sampled LOW. Depending level EXTFIFO, asserted state TXEN active HIGH active LOW. EXTFIFO LOW, then TXEN active data captured same clock cycle where TXEN sampled LOW. EXTFIFO HIGH, then TXEN active HIGH data captured clock cycle following clock edge when TXEN sampled HIGH. input, asynchronous Internal Pull-up Transmitter BIST Enable. When TXBISTEN LOW, transmitter generates 511-character repeating sequence that used validate link integrity. This 4B/5B BIST sequence generated regardless state other configuration inputs. transmitter returns normal operation when TXBISTEN HIGH. Transmit FIFO read operations suspended when BIST active.
TXBISTEN
TXRST
input, sampled Reset Transmit FIFO. When Transmit FIFO enabled (FIFOBYP HIGH), TXEN deasserted, TXCLK Internal Pull-up asserted (LOW), TXRST sampled TXCLK seven cycles, Transmit FIFO begins internal reset process. Transmit FIFO TXFULL flag asserted host interface counter address pointer zeroed. This reset propagates serial transmit side, remaining counters pointers. TXFULL flag asserted until both sides Transmit FIFO have reset. While TXRST remains asserted, Transmit FIFO remains reset TXFULL output remains asserted. When Transmit FIFO bypassed (FIFOBYP LOW), TXRST ignored. input, sampled Transmitter Halt Control Input. TXCLK When TXHALT asserted LOW, transmission data suspended HOTLink TAXI transmits SYNC characters. When TXHALT deasserted HIGH, Internal Pull-up normal data processing proceeds. Transmit FIFO enabled (FIFOBYP HIGH), interface allowed continue loading data into Transmit FIFO while TXHALT asserted. Three-state output, changes following TXCLK REFCLK Transmit FIFO Full Status Flag. When Transmit FIFO enabled (FIFOBYP HIGH) flags driven LOW), TXFULL asserted when four fewer characters written HOTLink Transmit FIFO. Transmit FIFO reset been initiated (TXRST sampled asserted minimum seven TXCLK cycles), TXFULL asserted enforce full/unavailable status Transmit FIFO during reset. When Transmit FIFO bypassed (FIFOBYP LOW), TXFULL output changes after rising edge REFCLK. TXFULL asserted when transmitter BUSY (not accepting data command characters) deasserted when characters accepted. When Transmit FIFO bypassed RANGESEL HIGH SPDSEL LOW, TXFULL toggles character rate provide character rate reference control-indication since REFCLK operating twice data rate. asserted state this output (HIGH LOW) determined state EXTFIFO input. When EXTFIFO LOW, TXFULL active LOW. When EXTFIFO HIGH, TXFULL active HIGH.
TXHALT
TXFULL
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Descriptions (continued)
Name TXHALF Characteristics Three-state output, changes following TXCLK Signal Description Transmit FIFO Half-full Status Flag. When Transmit FIFO enabled (FIFOBYP HIGH LOW) TXHALF asserted when HOTLink Transmit FIFO half full (128 characters half full). Transmit FIFO reset been initiated (TXRST sampled asserted minimum seven TXCLK cycles), TXHALF asserted enforce full/unavailable status Transmit FIFO during reset. When Transmit FIFO bypassed (FIFOBYP LOW), TXHALF remains deasserted, having logical function. TXHALF forced High-Z state only during "full-chip" reset (i.e., while RESET LOW). Transmit FIFO Empty Status Flag. When Transmit FIFO enabled (FIFOBYP HIGH LOW), TXEMPTY asserted when HOTLink Transmit FIFO data forward encoder. Transmit FIFO reset been initiated (TXRST sampled asserted minimum seven TXCLK cycles), TXEMPTY deasserted remains deasserted until Transmit FIFO reset operation complete. When Transmit FIFO bypassed (FIFOBYP LOW), TXEMPTY asserted indicate that transmitter accept data. TXEMPTY also used BIST progress indicator when TXBISTEN asserted. When TXBISTEN asserted LOW, TXEMPTY becomes transmit BIST-loop counter indicator (regardless logic state FIFOBYP). this mode TXEMPTY asserted TXCLK REFCLK period each transmitted BIST sequence. Note: During BIST operations, when Transmit FIFO enabled (FIFOBYP HIGH), necessary keep TXCLK operating, even though data loaded into Transmit FIFO TXEN never asserted, allow TXEMPTY flag respond BIST state changes. asserted state this output (HIGH LOW) determined state EXTFIFO input. When EXTFIFO LOW, TXEMPTY active LOW. When EXTFIFO HIGH, TXEMPTY active HIGH. sampled asserted (LOW), TXEMPTY driven active state. sampled deasserted (HIGH), TXEMPTY placed into High-Z state.
TXEMPTY
Three-state output, changes following TXCLK REFCLK
Receive Path Signals RXCLK Bidirectional clock Receive Clock. Internal Pull-up When Receive FIFO enabled (FIFOBYP HIGH), this clock Receive interface input clock used control Receive FIFO read reset, operations. When Receive FIFO bypassed (FIFOBYP LOW), this clock becomes recovered Receive character clock output which runs continuously character rate. Three-state output, changes following RXCLK Parallel Receive DATA Outputs. When decoder enabled (ENCBYP HIGH), low-order eight bits decoded DATA character presented RXDATA[7:0] outputs. COMMAND characters, when they received, disturb these outputs. When decoder bypassed, order eight bits non-decoded character presented RXDATA[7:0] outputs. When Receive FIFO disabled (FIFOBYP LOW), these outputs change rising edge RXCLK output. When Receive FIFO enabled (FIFOBYP HIGH), these outputs change rising edge RXCLK input. RXEN three-state control RXDATA[7:0].
RXDATA[7:0] 59,61
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Descriptions (continued)
Name Characteristics Three-state output, changes following RXCLK Signal Description Parallel Receive DATA COMMAND Output. When BYTE8/10 HIGH decoder enabled (ENCBYP HIGH) these outputs reflects value most recently received RXCMD[2:3]. When BYTE8/10 decoder enabled (ENCBYP HIGH) these outputs reflects value most recently received RXDATA[9:8]. When decoder bypassed (ENCBYP LOW), RXDATA[9:8] functions 10th bits 12-bit non-decoded receive character. When Receive FIFO disabled (FIFOBYP LOW), these outputs change rising edge RXCLK output. When Receive FIFO enabled (FIFOBYP HIGH), these outputs change rising edge RXCLK input. RXEN three-state control RXDATA[9:8]/RXCMD[2:3]. Parallel Receive COMMAND Outputs. When decoder enabled (ENCBYP HIGH) these outputs reflect value most recently received RXCMD[1:0]. When BYTE8/10 HIGH decoder bypassed (ENCBYP LOW), these outputs have meaning driven LOW. When BYTE8/10 decoder bypassed (ENCBYP LOW), RXCMD[1:0] functions 11th 12th (MSB) bits 12-bit non-decoded receive character. When Receive FIFO disabled (FIFOBYP LOW), this output changes rising edge RXCLK output. When Receive FIFO enabled (FIFOBYP HIGH), these outputs change rising edge RXCLK input. RXEN three-state control RXCMD[1:0]. Receive Enable Input. RXEN three-state control parallel data read operations. RXEN sampled rising edge RXCLK input output) enables parallel data read operations (when selected). device selected when RXEN asserted during RXCLK cycle immediately following which sampled LOW. parallel data pins driven active levels after rising edge RXCLK. When RXEN de-asserted (ending selection) parallel data pins High-Z after rising edge RXCLK. Depending level EXTFIFO, this signal active HIGH active LOW. EXTFIFO LOW, then RXEN active LOW. EXTFIFO HIGH, then RXEN active HIGH. Data delivered clock cycle following clock edge when RXEN active. COMMAND DATA Output Indicator. When BYTE8/10 HIGH decoder enabled (ENCBYP HIGH), this output indicates which group outputs have been updated. RXSC/D HIGH, RXCMD[3:0] contains COMMAND. DATA RXDATA[7:0] pins remain unchanged. RXSC/D LOW, RXDATA[7:0] contains DATA character. COMMAND output RXCMD[3:0] remain unchanged. When BYTE8/10 decoder enabled (ENCBYP HIGH), this output indicates which group outputs have been updated. RXSC/D HIGH, RXCMD[1:0] contains COMMAND DATA RXDATA[9:0] remain unchanged. RXSC/D LOW, RXDATA[9:0] contains DATA character COMMAND output RXCMD[1:0] remain unchanged. When decoder bypassed (ENCBYP LOW) RXSC/D used left unconnected. RXEN three-state control RXSC/D. RXDATA[9:8]/ RXCMD[2:3]
RXDATA[11:10 Three-state ]/RXCMD[1:0] output, changes following RXCLK
RXEN
input, sampled RXCLK Internal Pull-up
RXSC/D
Three-state output, changes following RXCLK
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Descriptions (continued)
Name VLTN Characteristics Three-state output, changes following RXCLK Internal Pull-down Signal Description Code Rule Violation Detected. VLTN asserted response detection 4B/5B 5B/6B character that does meet coding rules these characters. When VLTN asserted, values output DATA COMMAND buses remain unchanged. VLTN remains asserted RXCLK period. VLTN used report character mismatches when RXBISTEN driven LOW. VLTN driven when decoder bypassed (ENCBYP LOW). RXEN three-state control VLTN.
RXRST
input, sampled Receive FIFO Reset. Active LOW. When Receive FIFO enabled (FIFOBYP HIGH), RXEN deasserted, RXCLK Internal Pull-up asserted (LOW), RXRST sampled while asserted (LOW) RXCLK seven cycles, Receive FIFO begins internal reset process. Once reset operation started, RXEMPTY flag asserted interface counters address pointer zeroed. reset operation proceeds clear internal write pointers counters. RXEMPTY output remains asserted through reset operation remains asserted until data written Receive FIFO. While RXRST remains asserted, Receive FIFO remains reset cannot accept received characters. When Receive FIFO bypassed (FIFOBYP LOW), RXRST ignored. Receiver Discard Policy Mode Select. 00b-allows characters written into Receive FIFO output Receive data 01b-discards sync characters except "last" string sync characters. Single sync characters data stream included data written into Receive FIFO. 1Xb-discards sync characters. data stream written into Receive FIFO does include sync characters. Receiver BIST Enable. Active LOW. When LOW, receiver configured perform character-for-character match incoming data stream with 511-character BIST sequence. result character mismatches indicated VLTN pin. Completion each 511-character BIST loop accompanied assertion pulse RXFULL flag. state ENCBYP, FIFOBYP, BYTE8/10 have effect BIST operation. Reframe Enable. Used control when framer allowed adjust character boundaries based detection more framing characters data stream. When framing enabled (RFEN HIGH) receive framer realigns serial stream incoming 10-bit sync character BYTE8/10 HIGH) 12-bit sync character BYTE8/10 LOW). Framing disabled when RFEN LOW. deassertion RFEN freezes character boundary relationship between serial stream character clock. RFEN asynchronous input, sampled internal Receive character clock.
RXMODE[1:0] Static control input levels Normally wired HIGH
RXBISTEN
input, asynchronous Internal Pull-up
RFEN
input, asynchronous Internal Pull-up
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Descriptions (continued)
Name RXFULL Characteristics Three-state output, changes following RXCLK Signal Description Receive FIFO Full Flag. When Receive FIFO enabled (FIFOBYP HIGH) flags driven LOW), RXFULL asserted when space available four fewer characters written HOTLink Receive FIFO. RXCLK input continuous FIFO accessed rate slower than data being received, RXFULL also indicate that some data been lost because FIFO overflow. When Receive FIFO bypassed (FIFOBYP LOW), RXFULL deasserted indicate that valid data present. RXFULL also used BIST progress indicator, pulses once every pass through character BIST loop. When RXBISTEN asserted (LOW), RXFULL becomes receive BIST loop progress indicator (regardless logic state FIFOBYP). While RXBISTEN asserted, RXFULL asserted until receiver detects start BIST pattern. Then RXFULL deasserted duration BIST pattern, pulsing asserted RXCLK period last symbol each BIST loop. consecutive symbols received error, RXFULL returns asserted state until start BIST pattern again detected. asserted state this output (HIGH LOW) determined state EXTFIFO input. When EXTFIFO LOW, RXFULL active LOW. When EXTFIFO HIGH, RXFULL active HIGH. Receive FIFO Half-full Flag. When Receive FIFO enabled (FIFOBYP HIGH LOW) RXHALF asserted when HOTLink Receive FIFO half full (128 characters half full). Receive FIFO reset been initiated (RXRST sampled asserted minimum seven RXCLK cycles), RXHALF deasserted enforce empty/unavailable status Receive FIFO during reset. FIFOBYP LOW, RXHALF remains deasserted having logical function. RXHALF forced High-Z state only during "full-chip" reset (i.e., while RESET LOW). Receive FIFO Empty Flag. When Receive FIFO enabled (FIFOBYP HIGH) flags driven LOW), RXEMPTY asserted when HOTLink Receive FIFO data forward parallel interface. Receive FIFO reset been initiated (RXRST sampled asserted minimum seven RXCLK cycles), RXEMPTY asserted enforce empty/unavailable status Receive FIFO during reset. read operation occurring when RXEMPTY asserted results change FIFO status, data from last valid read remains RXDATA bus. When Receive FIFO bypassed decoder enabled, RXEMPTY used valid data indicator. When deasserted indicates that valid data present RXDATA RXCMD outputs indicated RXSC/D. When asserted indicates that SYNC character present RXCMD output pins. When Receive FIFO bypassed (FIFOBYP LOW), RXEMPTY deasserted whenever data ready. asserted state this output (HIGH LOW) determined state EXTFIFO input. When EXTFIFO LOW, RXEMPTY active LOW. When EXTFIFO HIGH, RXEMPTY active HIGH.
RXHALF
Three-state output, changes following RXCLK
RXEMPTY
Three-state output, changes following RXCLK
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Descriptions (continued)
Name Characteristics Signal Description Control Signals input sampled Chip Enable Input. Active LOW. TXCLK, RXCLK, When asserted sampled RXCLK, Receive FIFO status REFCLK flags driven their active states. When this input deasserted sampled RXCLK, Receive FIFO status flags placed High-Z state. When been sampled RXEN changes from deasserted asserted sampled RXCLK, RXSC/D, RXDATA[7:0], RXDATA[9:8]/RXCMD[2:3] VLTN output drivers enabled their driven levels. These pins remain driven until RXEN sampled deasserted. When Transmit FIFO enabled (FIFOBYP HIGH), asserted sampled TXCLK, Transmit FIFO status flags driven their active states. When this input deasserted sampled TXCLK, Transmit FIFO status flags placed High-Z state. When Transmit FIFO bypassed (FIFOBYP LOW), asserted sampled REFCLK, Transmit FIFO status flags driven their active states. When this input deasserted sampled REFCLK, Transmit FIFO status flags placed High-Z state. When Transmit FIFO enabled (FIFOBYP HIGH), been sampled LOW, TXEN changes from deasserted asserted sampled TXCLK, TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], TXCMD[1:0] inputs sampled passed Transmit FIFO. These inputs sampled consecutive TXCLK cycles until TXEN sampled deasserted. When Transmit FIFO bypassed (FIFOBYP LOW), been sampled LOW, TXEN changes from deasserted asserted sampled REFCLK, TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], TXCMD[1:0] inputs sampled passed encoder serializer directed other control inputs. These inputs sampled consecutive REFCLK cycles until TXEN sampled deasserted. clock input Frequency Reference Clock. This clock input used timing reference transmit receive PLLs. When Transmit FIFO bypassed (FIFOBYP HIGH), REFCLK also used clock parallel transmit interface. Speed Select. Used select from operating serial rates CY7C9689A. When SPDSEL HIGH, signaling rate between MBaud. When LOW, signaling rate between MBaud. Used combination with RANGESEL BYTE8/10 configure multipliers dividers. Range Select. Selects proper prescaler REFCLK input. RANGESEL LOW, REFCLK input passed directly Transmit clock multiplier. RANGESEL HIGH, REFLCK divided before being sent Transmit multiplier. When Transmit FIFO bypassed (FIFOBYP LOW), with RANGESEL HIGH SPDSEL LOW, TXFULL toggles half REFCLK rate provide character rate indication, show when data accepted. Master Reset Internal Logic. Pulsed more REFCLK cycles. FIFO Bypass Enable. When asserted, Transmit Receive FIFOs bypassed. this mode TXCLK used. Instead transmit data must synchronous REFCLK. Transmit FIFO status flags synchronized REFCLK. received data synchronous RXCLK output. Receive FIFO status flags synchronized RXCLK (the recovered Receive character clock). When asserted, Transmit Receive FIFOs enabled. this mode Transmit FIFO writes synchronized TXCLK, Receive FIFO reads synchronous RXCLK input. Page
REFCLK
SPDSEL
Static control input levels Normally wired HIGH Static control input levels Normally wired HIGH
RANGESEL
RESET FIFOBYP
Asynchronous input Static control input levels Normally wired HIGH
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Descriptions (continued)
Name BYTE8/10 Characteristics Static control input levels Normally wired HIGH Signal Description 8/10-bit Parallel Data Size Select. When 8-bit data (BYTE8/10 HIGH) encoder enabled (ENCBYP HIGH), 8-bit DATA characters 4-bit COMMAND characters captured TXDATA[7:0] TXCMD[3:0] inputs (selected TXSC/D input) passed Transmit FIFO enabled) encoder. Received characters decoded, passed through Receive FIFO enabled) presented either RXDATA[7:0] RXCMD[3:0] outputs indicated RXSC/D output. When 8-bit data (BYTE8/10 HIGH) encoder bypassed (ENCBYP LOW), internal data paths 10-bit characters. Each received character presented Receive FIFO enabled) passed RXDATA[9:0] outputs. When 10-bit data (BYTE8/10 LOW) encoder enabled (ENCBYP HIGH), 10-bit DATA characters 2-bit COMMAND characters captured TXDATA[9:0] TXCMD[1:0] inputs (selected TXSC/D input) passed Transmit FIFO enabled) encoder. Received characters decoded, passed through Receive FIFO enabled) presented either RXDATA[9:0] RXCMD[1:0] outputs indicated RXSC/D output. When 10-bit data (BYTE8/10 LOW) encoder bypassed (ENCBYP LOW), internal clock data paths 12-bit characters. Each received character presented Receive FIFO enabled) passed RXDATA[9:0] RXCMD[1:0] outputs. External FIFO Mode. EXTFIFO modifies active state RXEN TXEN inputs timing Transmitter Receiver data buses. When configured external FIFOs (EXTFIFO HIGH), TXEN assumed driven empty flag attached CY7C42X5 FIFO, RXEN assumed driven almost full flag attached CY7C42X5 FIFO. this mode active data transition clock following clock edge that "enables" data bus. When configured external FIFOs (EXTFIFO LOW), TXEN assumed driven pipeline register RXEN assumed driven controller pipeline register. this mode active data transition within same clock clock edge that "enables" data bus. EXTFIFO also modifies output state Receive Transmit FIFO flags. When configured external FIFOs (EXTFIFO HIGH), Full Empty FIFO flags active HIGH (the Half full flag always active LOW). When configured external FIFOs (EXTFIFO LOW), FIFO flags active LOW. Enable Encoder Bypass Mode. When asserted, both encoder decoder bypassed. Data transmitted without 4B/5B 5B/6B encoding (but with NRZI encoding), first. Received data presented parallel characters parallel interface without decoding. When deasserted, data passed through both encoder Transmit path decoder Receive path. Differential Serial Data Outputs. These PECL-compatible differential outputs capable driving terminated transmission lines commercial fiber-optic transmitter modules. minimize power dissipation unused outputs, outputs should left unconnected associated CURSETA CURSETB should connected VDD. Differential Serial Data Inputs. These inputs accept serial data stream deserialization decoding. Only serial stream time receive extract data content. This stream selected using input.
EXTFIFO
Static control input levels Normally wired HIGH
ENCBYP
Static control input levels Normally wired HIGH
Analog Control OUTA± OUTB± PECL compatible differential output
INA± INB±
PECL compatible differential input
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Descriptions (continued)
Name CURSETA Characteristics Analog Signal Description Current-set Resistor Input OUTA±. precision resistor connected between this input clean ground output differential amplitude currents OUTA± differential driver. Current-set Resistor Input OUTB±. precision resistor connected between this input clean ground output differential amplitude currents OUTB± differential driver. Carrier Detect Input. Used allow external device signify valid signal being presented high-speed PECL input buffers, typical Optical Module. When CARDET deasserted LOW, indicator asserts signifying Link Fault. This input tied HIGH copper media applications. Input Input Selector. When HIGH, input INA± selected, when LOW, INB± selected. Link Fault Indication Output. Active LOW. changes synchronous with RXCLK. This output driven when serial link currently selected suitable data recovery. This could because: Serial Data Amplitude below acceptable levels Input transition density sufficient clock recovery Input Data stream outside acceptable frequency range operation CARDET Diagnostic Loop Back Selector. When LOW, LOOP Mode OFF. Output transmitter shifter routed both OUTA± OUTB± serial input selected routed receive data recovery. When HIGH, Diagnostic Loopback Enabled. Output transmitter serial data routed receive data recovery. Primarily used System Diagnostic test. serial inputs ignored OUTA± OUTB± both active. Test Mode Select. Used force part into diagnostic test mode used factory test. This input must tied HIGH during normal operation. Power PECL-compatible signals internal circuits.
CURSETB
Analog
CARDET
PECL input, asynchronous
Asynchronous input output, changes following RXCLK
Asynchronous input
TEST
Asynchronous input normally wired HIGH
Power VDDA VSSA 4,11,
Ground PECL-compatible signals internal circuits.
Power signals internal circuits.
Ground signals internal circuits.
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CY7C9689A
CY7C9689A HOTLink Operation
Overview CY7C9689A designed move parallel data across both short long distances with minimal overhead host system intervention. This accomplished converting parallel characters into serial bit-stream, transmitting these serial bits high speed, converting received serial bits back into original parallel data format. CY7C9689A offers large feature set, allowing used wide range host systems. Some configuration options TAXIchip 4B/5B- 5B/6B-compatible encoder/decoder TAXIchip-compatible serial link TAXIchip parallel COMMAND DATA architecture 8-bit 10-bit character size User-definable data packet frame structure Two-octave data rate range Asynchronous (FIFOed) synchronous data interface Embedded bypassable FIFO data storage Encoded non-encoded Multi-PHY capability This flexibility allows CY7C9689A meet data transport needs almost system. Transmit Data Path Transmit Data Interface/Transmit Data FIFO transmit data interface host system configurable either asynchronous buffered (FIFOed) parallel interface synchronous pipeline register. itself configured operation with either 8-bit 10-bit character widths. When configured asynchronous operation (where host-bus interface clock operates asynchronous serial character stream clocks), host interface becomes that synchronous FIFO clocked TXCLK. this configuration internal 256-character Transmit FIFO enabled that allows host interface written rate from MHz. When configured synchronous operation, transmit interface clocked REFCLK operates synchronous internal character bit-stream clocks. input register written either 1/10 1/12 serial rate. This interface clocked when configured 8-bit data width, when configured 10-bit data width. Actual clock rate depends data rate well RANGESEL SPDSEL logic levels. Both asynchronous synchronous interface operations support user control over logical sense FIFO status flags. Full empty flags both transmitter receiver active HIGH active LOW. This facilitates interfacing with existing control logic external FIFOs with minimal external glue logic.
Encoder Data from host interface Transmit FIFO next passed Encoder block. CY7C9689A contains both 4B/5B 5B/6B encoders that used improve serial transport characteristics data. those systems that contain their encoder scrambler, this Encoder bypassed. Serializer/Line Driver data from Encoder passed Serializer. This Serializer operates times character rate. With internal FIFOs enabled, REFCLK character rate. With FIFOs bypassed, REFCLK operate character rate. serialized data output NRZI format from PECL-compatible differential line drivers configured drive transmission lines optical modules. Receive Data Interface Line Receiver/Deserializer/Framer Serial data received PECL-compatible differential line receivers. data passed both Clock Data Recovery Deserializer that converts NRZI serial data into parallel characters. Framer adjusts boundaries these characters match those original transmitted characters. Decoder parallel characters passed through pair 5B/4B 6B/5B decoders returned their original form. systems that make external decoding descrambling, decoder bypassed. Receive Data Interface/Receive Data FIFO Data from decoder passed either synchronous Receive FIFO passed directly output register. output register configured either 8-bit character 10-bit character operation. When configured asynchronous buffered (FIFOed) interface, data passed through 256-character Receive FIFO that allows data read rate from MHz. When configured synchronous operation (Receive FIFO bypassed) data clocked Receive Output register when configured 8-bit characters, 16.67 when configured 10-bit characters. receive interface also configurable FIFO flags with either HIGH status indication Oscillator Speed Selection CY7C9689A designed operate over two-octave range serial signaling rates, covering 200-MBaud range. cover this wide range, PLLs configured into various sub-regions using SPDSEL RANGESEL inputs, limited extent BYTE8/10 input. These inputs used configure various prescalers clock dividers used with transmit receive PLLs.
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CY7C9689A TAXI HOTLink Transceiver Block Diagram Description
Transmit Input/Output Register CY7C9689A provides synchronous interface data command inputs, instead TAXI's asynchronous strobed interface. Transmit Input Register, shown Figure captures data command processed HOTLink Transmitter, allows input timing made compatible with asynchronous synchronous host system buses. These buses take form external FIFOs, state machines, other control structures. Data command present TXDATA[9:0] TXSC/D inputs captured rising edge selected sample clock. transmit data bit-assignments vary depending data encoding bus-width selected. These bit-assignments shown Table list functional names these different signals. Note that function several these signals changes different operating modes. logical sense enable FIFO flag signals depends intended interface convention EXTFIFO pin. transmit interface supports both synchronous asynchronous clocking modes, each supporting both UTOPIA Cascade timing models. selection specific Table Transmit Input Signal
clocking mode determined RANGESEL SPDSEL inputs FIFO Bypass (FIFOBYP) signal. Figure Transmit Input Register TXDATA[7:0] REFCLK TXCMD[3:0] TXEN TXCLK TXSC/D
Transmit Input Register
Encoder Block
Transmit FIFO
Transmit Encoder Mode[1] TXDATA Input TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXDATA[8]/TXCMD[3] TXDATA[9]/TXCMD[2] TXCMD[1] TXCMD[0] Encoded 8-bit Character Stream[2] TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXCMD[3] TXCMD[2] TXCMD[1] TXCMD[0] TXD[0][4] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] Pre-encoded 10-bit Character Stream Encoded 10-bit Character Stream[3] TXSC/D TXDATA[0] TXDATA[1] TXDATA[2] TXDATA[3] TXDATA[4] TXDATA[5] TXDATA[6] TXDATA[7] TXDATA[8] TXDATA[9][3] TXCMD[1] TXCMD[0] TXD[0][5] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] TXD[10][5] TXD[11] Pre-encoded 12-bit Character Stream
Notes open cells ignored. When ENCBYP HIGH BYTE8/10 HIGH, transmitted order encoded form (MSB LSB) TXDATA[7,6,5,4] TXDATA[3,2,1,0] TXCMD[3,2,1,0] selected TXSC/D. When ENCBYP HIGH BYTE8/10 LOW, transmitted order encoded form (MSB LSB) TXDATA[8,7,6,5,4] TXDATA[9,3,2,1,0] TXCMD[1,0] selected TXSC/D. When ENCBYP BYTE8/10 HIGH, transmitted order (LSB MSB) TXD[0,1,2,3,4,5,6,7,8,9]. When ENCBYP BYTE8/10 LOW, transmitted order (LSB MSB) TXD[0,1,2,3,4,5,6,7,8,9,11,10].
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Synchronous Interface Synchronous interface clocking operates entire transmit data path synchronous REFCLK. enabled connecting FIFOBYP disable internal FIFOs. Asynchronous Interface Asynchronous interface clocking controls writing host data into Transmit FIFO. enabled setting FIFOBYP HIGH enable internal FIFOs. these configurations, writes Transmit Input Register, associated transfers Transmit FIFO, controlled TXCLK. remainder transmit data path clocked REFCLK synthesized derivatives REFCLK. Shared Timing Model Shared Timing Model allows multiple CY7C9689A transmitters accessed from common host bus. enabled setting EXTFIFO LOW. shared timing, TXEMPTY TXFULL outputs TXEN input active signals. CY7C9689A addressed asserting LOW, becomes "selected" when TXEN asserted LOW. Following selection, data command written into Transmit FIFO every clock cycle where TXEN remains LOW. Cascade Timing Model Cascade timing model variation shared timing model. Here TXEMPTY TXFULL outputs, TXEN input, active HIGH signals. Cascade timing makes same selection sequences shared timing, write data accesses delayed write. This delayed write necessary allow direct coupling external FIFOs, state machines that initiate write operation clock cycle before data available bus. Cascade timing enabled setting EXTFIFO HIGH. When used FIFO depth expansion, Cascade timing allows size internal Transmit FIFO expanded almost unlimited depth. allows CY7C42x5 series synchronous FIFO attached transmit interface without extra logic, shown Figure Figure External FIFO Depth Expansion CY7C9689A Transmit Data Path CY7C42x5 FIFO WEN* TXCLK WEN* WCLK REN* RCLK CY7C9689A TXEN TXFULL TXDATA TXSC/D TXCLK EXTFIFO
Transmit FIFO Transmit FIFO used buffer data command captured input register later processing transmission. This FIFO sized hold 14-bit characters. When Transmit FIFO enabled, Transmit FIFO write enabled (the device selected TXEN sampled asserted), data captured transmit input register stored into Transmit FIFO. Transmit FIFO write operations clocked TXCLK. Transmit FIFO presents Full, Half-Full, Empty FIFO flags. These flags provided synchronous TXCLK. When Transmit FIFO enabled, allows operation with Moore-type external controlling state machine. When configured Cascade timing, timing active levels these signals also designed support direct expansion Cypress CY7C42x5 synchronous FIFOs. Regardless width 10-bit characters) Transmit FIFO clocked rate from MHz. This gives Transmit FIFO maximum bandwidth million characters second. Since serial outputs only move million characters second their fastest operating rate, there ample time service multiple CY7C9689A HOTLinks with single controller. read port Transmit FIFO connected logic block that performs data formatting validation. data read operations from Transmit FIFO controlled Transmit Control State Machine that operates synchronous REFCLK. Encoder Block Encoder logic block performs primary functions: encoding data serial transmission generating BIST patterns allow at-speed link device testing. BIST LFSR Encoder logic block operates data stored register. This register accepts information directly from Transmit FIFO, Transmit Input Register from Transmit Control State Machine when inserts special characters into data stream. This same register converted into Linear Feedback Shift Register (LFSR) when BIST pattern generator enabled (TXBISTEN LOW). When enabled, this LFSR generates 511-character sequence that includes Data Special Character codes, including explicit violation symbols. This provides predictable pseudo-random sequence that matched identical LFSR Receiver. Encoder data passed through Transmit FIFO pipeline register, received directly from Transmit Input Register, seldom form suitable transmission across serial link. characters must usually processed transformed guarantee: minimum transition density allow serial receiver extract clock from data stream) allow remote receiver determine correct character boundaries (framing).
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CY7C9689A contains integrated 4B/5B encoder that accepts 8-bit data characters converts these into 10-bit transmission characters that have been optimized transport serial communications links. This 4B/5B encoding scheme compliant with ANSI X3T9.5 (FDDI) committee's 4B/5B code. CY7C9689A also contains 5B/6B encoder that accepts 10-bit data characters converts these into 12-bit transmission characters. 4B/5B, 5B/6B encoder bypassed those systems that operate with external 4B/5B 5B/6B encoders alternate forms encoding scrambling ensure good transmission characteristics. complete encoding tables listed Table Table When Encoder enabled, transmit data characters passed through Transmit FIFO pipeline register) converted either 10-bit 12-bit Data symbol 10-bit 12-bit Command Character, depending upon state TXSC/D input. TXSC/D HIGH, data command inputs encoded into Command Character shown Table TXSC/D LOW, data inputs encoded using Data Character encoding Table 4B/5B, 5B/6B coding function Encoder bypassed systems that include external coder scrambler function part controller host system. This performed setting ENCBYP LOW. With encoder bypassed, each 10-bit 12-bit character captured Transmit Input Register) passed directly Transmit Shifter Transmit FIFO) without modification. Transmit Shifter Transmit Shifter accepts 10-bit (BYTE8/10 HIGH) 12-bit (BYTE8/10 LOW) parallel data from Encoder block once each character time, shifts serial interface output buffers using PLL-multiplied bit-clock with NRZI encoding. This bit-clock runs 2.5, times REFCLK rate times when BYTE8/10 LOW) selected RANGESEL SPDSEL (see Table Timing parallel transfer controlled counter dividers Clock Multiplier affected signal levels timing input pins. Bits each character shifted first.
Routing Matrix Routing Matrix precision multiplexor that allows local diagnostic loopback. signal routing transmit serial outputs controlled input listed Table 2.in Table Transmit Data Routing Matrix DLB[0]
OUTB RECEIVE
Data Connections
TRANSMIT SHIFTER OUTA
TRANSMIT SHIFTER
OUTA
OUTB RECEIVE
Serial Line Drivers serial interface PECL Output Drivers (ECL referenced +5V) transmission line drivers serial media. OUTA± receives data directly from transmit shifter, while OUTB± receives data from Routing Matrix. These outputs (OUTA± OUTB±) capable direct connection optical modules, also directly drive AC-coupled transmission lines. PECL-compatible Output Drivers viewed programmable current sources. output voltage determined output current load impedance ZLOAD. desired output voltage swing therefore controlled current-set resistor RCURSET associated with that driver. Different RCURSET values required different line impedance/amplitude combinations. output swing designed center around VDD-1.33V. Each output must externally biased VDD-1.33V. This differential output-swing specified ways: either peak-to-peak voltage into single-end load, absolute differential voltage into differential load. When specified into single-ended load (one outputs switching into load), single output will both source sink current changes between HIGH levels. voltage difference between this HIGH level level determine peak-to-peak signal-swing output. This amplitude relationship controlled load impedance driver, resistance RCURSET resistor that driver, listed
LOAD CURSET
VOPP difference voltage levels output differential driver when that output driving HIGH Document 38-02020 Rev. Page
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LOW, ZLOAD that load seen output when sourcing sinking current. With known load impedance desired signal swing, possible calculate value associated CURSETA CURSETB resistor that sets this current. Unused differential output drivers should left open, reduce their power dissipation connecting their respective CURSETx input VDD. Transmit Clock Multiplier Transmit Clock Multiplier accepts external clock REFCLK input, multiples that clock 2.5, when BYTE8/10 encoder disabled) generate bit-rate clock transmit shifter. also provides character-rate clock used Transmit Controller state machine. clock multiplier accept REFCLK input between MHz, however, this clock range limited operation mode CY7C9689A selected SPDSEL RANGESEL inputs, limited extent, BYTE8/10 FIFOBYP signals. operating serial signalling rate allowable range REFCLK frequencies listed Table Transmit Control State Machine Transmit Control State Machine responds multiple inputs control data stream passed encoder. operates response Table Speed Select Range Select Settings SPDSEL HIGH HIGH RANGESEL HIGH[6] HIGH Serial Data Rate (MBaud) 50-100 50-100 100-200 100-200 REFCLK[7] Frequency (MHz) 10-20 20-40 10-20 20-40
asserted) then Transmit Control State Machine presents (when BYTE8/10 LOW) Command Character code Encoder maintain link synchronization. both Encoder Transmit FIFO bypassed data enabled into Input Register, Transmit Control State Machine injects (when BYTE8/10 LOW) into Serial Shifter Register this time slot. This also occurs Encoder bypassed, Transmit FIFO enabled, Transmit FIFO empty. External Control Data Flow Transmit Control State Machine supports halting data transmission TXHALT input. This control signal input only interpreted when Transmit FIFO enabled. TXHALT brought directly state machine without going through Transmit FIFO. assertion TXHALT causes character processing stop next FIFO character location. additional data read from Transmit FIFO until TXHALT deasserted. TXHALT used prevent remote FIFO overflow, which would result lost data. This back-pressure mechanism significantly improve data integrity systems that cannot guarantee full bandwidth host system times. Serial Line Receivers differential line receivers, INA± INB±, available accepting serial data streams, with active input selected using input. input allow transmit Serializer output selected third input serial stream, this path generally used only local diagnostic loopback purposes. serial line receiver inputs differential, will accommodate wire interconnect with filtering losses transmission line attenuation greater than (VDIF peak-to-peak differential) directly connected fiber-optic interface modules (any logic family, limited 100K). common-mode tolerance these line receivers accommodates wide range signal termination voltages. seen Table these inputs configured allow single-pin control most applications. those systems requiring selection only INA± INB±, signals tied LOW, selection performed using only A/B. those systems requiring only single input local loopback, tied HIGH LOW, used loopback control. Signal Detect selected Line Receiver (that routed clock data recovery PLL) simultaneously monitored for: amplitude pk-pk) density data stream outside normal frequency range (±400 ppm) detected.
state FIFOBYP input presence data Transmit FIFO contents Transmit FIFO state transmitter BIST enable (TXBISTEN) state external halt signal (TXHALT). These signals used Transmit Control State Machine control data formatter, read access Transmit FIFO BIST. They determine content characters passed Encoder Transmit Shifter. When Transmit FIFO bypassed, Transmit Control State Machine operates synchronous REFCLK. this mode, data from TXDATA passed directly from Input Register Pipeline Register. data enabled into Input register (TXEN deasserted TXFULL
Notes When SPDSEL FIFOs bypassed (FIFOBYP LOW), RANGESEL input ignored internally mapped setting. When configured 12-bit preencoded data (BYTE8/10 ENCBYP both LOW) allowable REFCLK ranges 8.33 16.67 16.67 33.33 MHz.
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these conditions must valid Signal Detect block indicate valid signal present. This status presented (Link Fault Indicator) output, which changes synchronous RXCLK. While link status monitored internally times, necessary have transitions RXCLK allow this signal change externally. Clock/Data Recovery extraction bit-rate clock recovery data bits from received serial stream performed within Clock/Data Recovery (CDR) block. clock extraction function performed high-performance embedded that tracks frequency incoming stream aligns phase internal bit-rate clock transitions serial data stream. makes clock present REFCLK input. used ensure that (within CDR) operating correct frequency (rather than some harmonic rate), improve acquisition time, limit unlocked frequency excursions when data present serial inputs. Regardless type signal present, will attempt recover data stream from frequency recovered data stream outside limits range controls, will track REFCLK instead data stream. When frequency selected data stream returns valid frequency, allowed track received data stream. frequency REFCLK required within ±400 frequency clock that drives REFCLK signal remote transmitter ensure lock incoming data stream. systems using multiple redundant connections, output used select alternate data stream. When indication detected, external logic toggle selection INA± INB± inputs through input. When port switch takes place, necessary reacquire serial stream frame incoming characters. Clock Divider This block contains clock division logic, used transfer data from Deserializer/Framer Decoder once every character (once every twelve bits) clock. This counter free running generates outputs bit-rate divided when BYTE8/10 LOW). When Receive FIFO bypassed, these generated clocks driven RXCLK pin. Deserializer/Framer circuit extracts bits from serial data stream clocks these bits into Shifter/Framer bit-clock rate. When enabled, Framer examines data stream looking (when BYTE8/10 LOW) characters possible positions. location this character data stream used determine character boundaries following characters. framer operates different modes, selected RFEN input. When RFEN asserted (HIGH), framer allowed reset internal character boundaries detected (when BYTE8/10 LOW) character.
RFEN LOW, framer disabled changes made character boundaries. framer CY7C9689A operates shifting internal character position align with character clock. This ensures that recovered clock does contain significant phase changes/hops during normal operation framing, allows recovered clock replicated distributed other circuits using PLL-based logic elements. Decoder Block decoder logic block performs primary functions: decoding received transmission characters back into Data Command Character codes, comparing generated BIST patterns with received characters permit at-speed link device testing. 5B/4B, 6B/5B Decoder framed parallel output Deserializer passed 5B/4B, 6B/5B Decoder. Decoder enabled, transformed from 10-bit 12-bit transmission character back original Data Command Character codes. This block uses standard decoder patterns Table Table this data sheet. Data Patterns data indicated RXSC/D, Command Character codes command indicated HIGH. Invalid patterns disparity errors signaled errors HIGH VLTN. Decoder bypassed BYTE8/10 HIGH, (10) data bits each transmission character passed unchanged from framer Pipeline Register. When Decoder bypassed BYTE8/10 LOW, twelve (12) data bits each transmission character passed unchanged from framer Pipeline Register. BIST LFSR output register Decoder block normally used accumulate received characters delivery Receive Formatter block. When configured BIST mode (RXBISTEN LOW), this register becomes signature pattern generator checker logically converting Linear Feedback Shift Register (LFSR). When enabled, this LFSR generates 511-character sequence that includes Data Command Character codes, including explicit violation symbols. This provides predictable pseudo-random sequence that matched identical LFSR Transmitter. When synchronized with received data stream, checks each character Decoder with each character generated LFSR indicates compare errors VLTN output Receive Output Register. LFSR initialized BIST hardware BIST loop start code data sent only once BIST loop). Once start BIST loop been detected receiver, RXRVS asserted pattern mismatches between received characters internally generated character sequence. Code rule violations running disparity errors that occur part BIST loop cause error indication. RXFULL pulses asserted RXCLK cycle BIST loop used check test pattern progress. specific patterns checked receiver described Table
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large number errors detected, receive BIST state machine aborts compare operations resets LFSR D0.0 state look start BIST sequence again. Receive Control State Machine Receive Control State Machine responds multiple input conditions control routing handling received characters. controls staging characters across various registers Receive FIFO. controls various discard policies error control within receiver, operates response received character stream room additional data Receive FIFO state receiver BIST enable (RXBISTEN) state FIFOBYP. These signals conditions used Receive Control State Machine control Receive Formatter, write access Receive FIFO, Receive Output register, BIST. They determine content characters passed each these destinations. Receive Control State Machine always operates synchronous recovered character clock (bit-clock/10 bit-clock/12). When Receive FIFO bypassed, RXCLK becomes output that changes synchronous internal character clock. RXCLK operates same frequency internal character clock. Discard Policies When Receive FIFO enabled, Receive Control State Machine ability selectively discard specific characters from data stream that determined present configuration being unnecessary. When discarding enabled, reduces host system overhead necessary keep Receive FIFO from overflowing losing data. discard policy configured part operating mode using RXMODE[1:0] inputs. four discard policies listed Table Policy simplest also applies conditions where Receive FIFO bypassed. this mode, every character that received placed into Receive FIFO (when enabled) into Receive Output Register. discard policy SYNC character, which automatically transmitted when data present Transmit FIFO, treated differently here. this mode, whenever more adjacent characters received, them discarded except last received before other character type. This allows these fill characters removed from data stream, last SYNC character which used delimiter. Policy identical policy except that C5.0 characters removed from data stream. When FIFOs bypassed (FIFOBYP LOW), characters actually discarded, receiver discard policy used control external filtering data. RXEMPTY FIFO flag used indicate character output valid not. discard policy RXEMPTY flag always deasserted indicate that valid data always Document 38-02020 Rev.
present. discard policy RXEMPTY flag indicates empty condition last character before other character presented. discard policy RXEMPTY flag indicates empty condition SYNC characters. When other character present, this flag indicates that valid "interesting" Data Special Characters present. Receive FIFO Receive FIFO used buffer data captured from selected serial stream later processing host system. This FIFO sized hold 14-bit characters. When FIFO enabled, written Receive Control State Machine. When data present Receive FIFO indicated RXFULL, RXHALF, RXEMPTY Receive FIFO status flags), read from Output Register asserting RXEN. read port Receive FIFO configured same timing models transmit interface: UTOPIA Cascade. Both forms FIFO interface. UTOPIA timing model active RXEMPTY RXFULL status flags, active RXEN enable. When configured Cascade operation, these same signals active HIGH. Either timing model supports connection various host interfaces, state machines, external FIFOs depth expansion (see Figure Figure External FIFO Depth Expansion CY7C9689A Receive Data Path)
CY7C42x5 FIFO REN* REN* WEN*
CY7C9689A RXEN RXEMPTY RXDATA RXSC/D
RXCLK
RCLK
WCLK
RXCLK EXTFIFO
Receive FIFO presents Full, Half-Full, Empty FIFO status flags. These flags provided synchronous RXCLK allow operation with Moore-type external controlling state machine. When configured with Receive FIFO enabled, RXCLK input. When Receive FIFO bypassed (FIFOBYP LOW), RXCLK output operating received character rate. Receive Input Register input register clocked rising edge RXCLK. samples numerous signals that control reading
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Table CY7C9689A TAXI HOTLink BIST Sequence D.00 C.JK C.TR D.89 D.15 D.A8 D.99 D.D1 C.SS D.50 C.JK C.IH C.SR D.42 D.0C C.TT D.46 D.64 C.IH C.QI C.SS C.HI C.JK C.HI C.II C.SR D.EE D.94 C.RS D.96 C.IH C.TS C.SR D.93 C.SS C.QQ D.FB D.55 C.QI C.HI C.QI C.TS C.TR D.77 D.2C D.EB D.91 D.E3 D.3D C.JK D.73 D.44 D.71 D.51 C.QI C.TS C.RS D.9B D.C4 D.52 D.C8 D.08 C.II D.E5 D.DE D.B1 D.1E C.RS D.35 C.II D.34 D.24 D.E0 C.TR D.C6 D.47 C.TS C.HI C.TS C.JK C.RS D.78 D.54 C.HH D.8F D.C5 C.TT D.1C C.IH C.JK C.JK C.TS C.QI D.29 C.TR D.9C C.RS D.C1 C.II C.II D.5C D.68 C.JK C.QI C.IH C.IH C.TR D.E1 D.12 C.QI C.TT D.4B C.II C.RS D.E6 C.QI C.QI C.SR D.70 D.23 C.RS D.6D D.CF D.11 D.C0 D.3A D.6B D.04 C.TS C.HH D.33 C.HQ C.HI C.QH C.SS C.SR C.QH C.TT D.3B C.RR D.66 C.SS C.TT D.09 D.36 D.31 C.TT D.97 D.9E C.TR D.25 C.SS C.TT D.61 D.95 C.RR D.B3 C.TT
C.QQ D.F8
C.QH D.D2
C.RR D.BC
C.QH D.D7
D.CD D.6A C.TS C.QI C.TR C.TR D.E4 C.SR D.65 D.28 C.HQ D.AE
C.RR D.B2 D.ED D.EC C.SS C.II D.7A C.TS C.SS C.IH C.TT
C.QH D.D4
C.HQ D.A3 C.RR C.TR C.QQ D.F4 D.38 D.7E C.JK C.JK C.HI C.RS
C.QQ D.F0 C.TS C.IH C.HI C.II
C.QQ D.FC D.DD D.6E C.TR D.17 D.BD C.HI C.SS C.TR D.02 C.SR D.0D D.5E D.92 C.SS C.QI
C.QH D.D3 D.45
C.RR D.B6
C.HQ D.AA C.HH D.8C D.E2
C.HQ D.A1
C.QQ D.FD
C.RR D.B0 D.6F
C.QQ D.F6 D.0A C.HI D.9F
C.RR D.BA D.48 D.2B D.4F C.TT D.74 C.HI C.TR D.58 D.EF D.40 D.19
C.HQ D.A9 C.II D.13 C.RS D.05 D.6C C.QI C.QH C.RR D.CA D.1D D.9A C.SR
C.QH D.DF C.TS C.II D.C2 D.2F C.QI C.RS D.22 D.9D
C.HH D.85
C.QH D.D8 D.60 C.RS D.5F C.IH C.II D.49 C.HI
C.QH D.DA C.QH D.D9 C.IH C.SR
D.CC C.TS
C.HQ D.AC C.QQ D.F1 D.E9 D.72 C.TT
C.QH D.D5 C.II D.98 C.QI C.II D.7B D.76 C.II D.06 C.IH C.TT D.EA C.RS D.37 C.HI C.IH
C.RR D.B4 D.1B D.E7 D.CB D.07 D.79 D.63
C.RR D.BF
C.HH D.84
C.HH D.8A D.14 C.TR D.4D C.JK C.SR D.2A
C.HQ D.A5 C.IH C.SS D.5B C.SS C.RS D.67 D.E8 C.IH C.QI
C.RR D.B5 D.0E C.SS
C.HH D.87 D.5A C.QQ D.FA
C.HH D.80 D.4E D.56 C.HI C.HI
C.QQ D.F9 D.27
C.HQ D.AD C.HQ D.A6 C.QH D.D6 C.HH D.83 D.69 D.A7 C.SR D.57 D.32 D.59
C.HH D.81
C.RR D.B9
C.HQ D.AF C.SR D.18 C.SS C.SS C.JK
C.HH D.86 C.TT D.2E D.C7 C.HQ C.TR
C.HQ D.A2 C.RR D.BE D.41 D.26 D.20 C.HH D.88
C.HQ D.AO C.TT C.HQ D.AB C.JK C.TT C.IH D.53 C.SR
C.QQ D.F2 D.CE D.75 D.39 C.TS C.SR D.3C D.16
C.RR D.B8 D.5D C.RS C.JK
C.RR D.B7
C.QQ D.F3
C.QH D.DC C.TS C.HQ D.A4 C.RS D.4A D.C3 C.HI
C.QH D.DB C.TR D.30 C.QI C.JK
C.HH D.8E C.TS
C.HH D.82 D.7C C.II
C.QH D.D0 C.QQ D.FE
C.QQ D.F5 D.2D D.1A
C.RR D.BB
C.HH D.8D
Table Receiver Discard Policies Policy (00) (01) (1X) Policy Description Keep received characters Process Commands, discard last SYNC character Process Commands, discard C5.0 characters
Receive FIFO operation Receive Control State Machine. Receive Output Register Receive Output Register changes response rising edge RXCLK. Receive FIFO status flag outputs this register placed High-Z state when CY7C9689A addressed sampled HIGH). Page
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RXDATA output drivers enabled when device selected RXEN being asserted RXCLK cycle immediately following that which device addressed sampled LOW), RXEN being sampled RXCLK. This initiates Receive FIFO read cycle. Just with TXDATA Transmit Input Register, receive outputs also mapped specific decoding bus-width selected ENCBYP, BYTE8/10 FIFOBYP inputs. These assignments shown Table Table Receiver Output Signal
Receive FIFO Decoder bypassed, received characters passed directly Receive Output Register. framing enabled, sync characters have been detected meeting present framing requirements, output characters will appear proper character boundaries. framing disabled (RFEN LOW) sync characters have been detected data stream, received characters output their proper 10-bit boundaries. this mode, some form external framing decoding/descrambling must used recover original source data.
Receiver Decoder Mode[1] RXDATA Output RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXDATA[8]/RXCMD[3] RXDATA[9]/RXCMD[2] RXCMD[1] RXCMD[0] VLTN Encoded 8-bit Character Stream[8] RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXCMD[3] RXCMD[2] RXCMD[1] RXCMD[0] VLTN RXD[0][10, RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9] Pre-encoded 10-bit Character Stream Encoded 10-bit Character Stream[9] RXSC/D RXDATA[0] RXDATA[1] RXDATA[2] RXDATA[3] RXDATA[4] RXDATA[5] RXDATA[6] RXDATA[7] RXDATA[8] RXDATA[9][9] RXCMD[1] RXCMD[0] VLTN RXD[0][10, RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9] RXD[10][12] RXD[11] Pre-encoded 12-bit Character Stream
Notes When BYTE8/10 HIGH, received order decoded form serial stream presented (MSB LSB) RXDATA[7,6,5,4] RXDATA[3,2,1,0] RXCMD[3,2,1,0] indicated RXSC/D. When BYTE8/10 LOW, received order decoded form serial stream presented (MSB LSB) RXDATA[8,7,6,5,4] RXDATA[9,3,2,1,0] RXCMD[1,0] indicated RXSC/D. First shifted into receiver. When ENCBYP BYTE8/10 HIGH, received order (LSB MSB) RXD[0,1,2,3,4,5,6,7,8,9]. When ENCBYP BYTE8/10 LOW, received order (LSB MSB) RXD[0,1,2,3,4,5,6,7,8,9,11,10].
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C +150°C Ambient Temperature with (Power Applied) -55°C +125°C Supply Voltage Ground Potential -0.5V +6.5V Voltage Applied Outputs .-0.5V 0.5V Output Current into Outputs (LOW) Input Voltage.-0.5V 0.5V
Static Discharge Voltage. 2001V (per MIL-STD-883, Method 3015) Latch-up Current. Operating Range Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 5.0V 5.0V
CY7C9689A Electrical Characteristics Over Operating Range
Parameter Outputs VOHT VOLT IOST IOZL Inputs VIHT VILT IIHT IILT IILPDT IILPUT VOHE VOLE VODIF Input HIGH Voltage Input Voltage Input HIGH Current Input Current Input HIGH Current with Internal Pull-down Input Current with Internal Pull-up Output HIGH Voltage (VDD referenced) Output Voltage (VDD referenced) Output Differential Voltage |(OUT+) (OUT-)| 0.0V 0.0V Load 1.33V; RCURSET Load 1.33V; RCURSET Load 1.33V; RCURSET -300 1.03 0.83 1.62 1100 -0.5 +300 Output HIGH Voltage Output Voltage Output Short Circuit Current High-Z Output Leakage Current Min. Min. VOUT 0V[13] Description Test Conditions Min. Max. Unit
Transmitter PECL-Compatible Output Pins: OUTA+, OUTA-, OUTB+, OUTB-
Receiver Single-ended PECL-Compatible Input Pin: CARDET VIHE VILE IIHE IILE VDIFF VIHH VILL IIHH IILL[14] Input HIGH Voltage (VDD referenced) Input Voltage (VDD referenced) Input HIGH Current Input Current Input Differential Voltage |(IN+) (IN-)| Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current VIHH Max. VILL Min. -200 VIHE(min.) VILE(max.) 2500 1.165 1.475
Receiver Differential Line Receiver Input Pins: INA+, INA-, INB+, INB-
Notes Tested output time, output shorted less than second, less than duty cycle. guarantee positive currents PECL voltages, external pull-down resistor must present.
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CY7C9689A Electrical Characteristics Over Operating Range
Parameter Miscellaneous IDD[15] Power Supply Current Freq. Max. Commercial Description Test Conditions Min. Typ. Max. Max. Unit
Capacitance[16]
Parameter CINTTL CINPECL Description Input Capacitance PECL input Capacitance Test Conditions 25°C, MHz, 5.0V 25°C, MHz, 5.0V Max. Unit
Test Loads Waveforms
5.0V OUTPUT R1=500 R2=333 (Includes fixture probe capacitance)
[17]
(Includes fixture probe capacitance)
Test Load
3.0V Vth=1.5V 0.0V 3.0V 2.0V 0.8V 2.0V 0.8V
PECL Test Load
VIHE
[17]
VIHE VILE
Vth=1.5V VILE
Input Test Waveform
PECL Input Test Waveform
Notes Maximum measured with MAX, RFEN LOW, outputs unloaded. Typical measured with 5.0V, 25°C, RFEN LOW, outputs unloaded. Tested initially after design process changes that affect these parameters, 100% tested. Cypress uses constant current (ATE) load configurations forcing functions. This figure reference only.
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CY7C9689A Transmitter Switching Characteristics, FIFO Enabled Over Operating Range
Parameter tTXCLK tTXCPWH tTXCPWL tTXCLKR[16] tTXCLKF[16] tTXA tTXDS tTXDH tTXENS tTXENH tTXRSS tTXRSH tTXCES tTXCEH tTXZA tTXOE tTXAZ TXCLK Period TXCLK HIGH Time TXCLK Time TXCLK Rise Time
[18]
Description TXCLK Clock Cycle Frequency With Transmit FIFO Enabled
Min.
Max.
Unit
TXCLK Fall Time[18] Flag Access Time From TXCLK Output Transmit Data Set-up Time TXCLK Transmit Data Hold Time from TXCLK Transmit Enable Set-up Time TXCLK Transmit Enable Hold Time from TXCLK Transmit FIFO Reset (TXRST) Set-up Time TXCLK Transmit FIFO Reset (TXRST Hold Time from TXCLK Transmit Chip Enable (CE) Set-up Time TXCLK Transmit Chip Enable (CE) Hold Time from TXCLK Sample TXCLK, Output High-Z Active HIGH Sample TXCLK Output Valid Sample HIGH TXCLK Output High-Z
CY7C9689A Receiver Switching Characteristics, FIFO Enabled Over Operating Range
Parameter fRIS tRXCLKIP tRXCPWH tRXCPWL tRXCLKIR[16] tRXCLKIF[16] tRXENS tRXENH tRXRSS tRXRSH tRXCES tRXCEH tRXA tRXZA RXCLK Input Period RXCLK Input HIGH Time RXCLK Input Time RXCLK Input Rise Time[18] RXCLK Input Fall Time[18] Receive Enable Set-up Time RXCLK Receive Enable Hold Time from RXCLK Receive FIFO Reset (RXRXT) Set-up Time RXCLK Receive FIFO Reset (RXRXT) Hold Time from RXCLK Receive Chip Enable (CE) Set-up Time RXCLK Receive Chip Enable (CE) Hold Time from RXCLK Flag Data Access Time From RXCLK Output Sample RXCLK, Output High-Z Active HIGH LOW,[19] Sample RXEN Asserted RXCLK, Output High-Z Active HIGH Description RXCLK Clock Cycle Frequency With Receive FIFO Enabled Min. Max. Unit
Notes Input/output rise fall time measured between 0.8V 2.0V Parallel data output specifications only valid outputs loaded with similar loads.
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CY7C9689A Receiver Switching Characteristics, FIFO Enabled Over Operating Range (continued)
Parameter tRXOE tRXZA Description Sample RXCLK Output Valid,[19] Sample RXEN Asserted RXCLK RXDATA Outputs Valid Sample HIGH RXCLK Output High-Z,[19] Sample RXEN Asserted RXCLK RXDATA Outputs High-Z Min. Max. Unit
CY7C9689A Transmitter Switching Characteristics, FIFO Bypassed Over Operating Range
Parameter tTRA tREFDS tREFDH tREFENS tREFENH tREFCES tREFCEH tREFZA tREFOE tREFAZ Description Flag Access Time From REFCLK Output Write Data Set-up Time REFCLK Write Data Hold Time from REFCLK Transmit Enable Set-up Time REFCLK Transmit Enable Hold Time from REFCLK Transmit Chip Enable (CE) Set-up Time REFCLK Transmit Chip Enable (CE) Hold Time from REFCLK Sample REFCLK, Output High-Z Active HIGH Sample REFCLK Flag Output Valid Sample HIGH REFCLK Flag Output High-Z Min. Max. Unit
CY7C9689A Receiver Switching Characteristics, FIFO Bypassed Over Operating Range
Parameter fROS[20] Description RXCLK Clock Output Frequency-100 MBaud 8-bit Operation (SPDSEL HIGH BYTE8/10 HIGH) RXCLK Clock Output Frequency-50 MBaud 8-bit Operation (SPDSEL BYTE8/10 HIGH) RXCLK Clock Output Frequency-100 MBaud 10-bit Operation (SPDSEL HIGH BYTE8/10 LOW) RXCLK Clock Output Frequency-50 MBaud 10-bit Operation (SPDSEL BYTE8/10 LOW) tRXCLKOP tRXCLKOD tRXCLKOR[16] tRXCLKOF[16] tRXENS tRXENH tRXZA tRXOE tRXAZ RXCLK Output Period RXCLK Output Duty Cycle RXCLK Output Rise Time
[18]
Min. 8.33 4.16 0.25 0.25
Max. 16.67 8.33
Unit
RXCLK Output Fall Time[18] Receive Enable Set-up Time RXCLK Receive Enable Hold Time from RXCLK Sample RXCLK, Outputs High-Z Active Sample RXEN Asserted RXCLK RXDATA Outputs High-Z Active Sample RXCLK Flag Output Valid Sample RXEN Asserted RXCLK RXDATA Output Low-Z Sample HIGH RXCLK Flag Output High-Z Sample RXEN Deasserted RXCLK RXDATA Output High-Z
Note period tROS will match period transmitter reference (REFCLK) when receiving serial data. When data interrupted, RXCLK drift REFCLK +0.2%.
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CY7C9689A REFCLK Input Switching Characteristics Over Operating Range
Parameter fREF Description REFCLK Clock Frequency-50 MBaud, 10-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-50 MBaud, 8-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-50 MBaud, 10-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-50 MBaud, 8-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-100 MBaud, 10-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-100 MBaud, 8-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-100 MBaud, 10-bit Mode, REFCLK Character Rate REFCLK Clock Frequency-100 MBaud, 8-bit Mode, REFCLK Character Rate tREFCLK tREFH tREFL tREFRX REFCLK Period REFCLK HIGH Time REFCLK Time REFCLK Frequency Referenced Received Clock Period[22] Conditions SPDSEL RANGESEL BYTE8/10 1[18] 1[18] Min. 8.33 16.67 8.33 16.67 -0.04 +0.04 Max. 16.67 33.3 16.67 33.3 Unit
CY7C9689A Receiver Switching Characteristics Over Operating Range
Parameter tB[23] tEFW tIN_J Time Static Alignment[16, 0.65
[16,
Description
Min. 20.0
Max.
Unit
Error Free Window[16, Peak-to-Peak Input Jitter Tolerance
Notes When configured synchronous operation with FIFOs bypassed (FIFOBYP LOW), RANGESEL HIGH SPDSEL input ignored operation forced 100-200 MBaud range. REFCLK phase frequency relationship with RXCLK only acts centering reference reduce clock synchronization time. REFCLK must within ±0.04% transmitter reference (REFCLK) frequency, necessitating ±200-PPM crystal. PECL switching threshold midpoint between PECL- VOH, specification (approximately 1.33V). Static alignment measure alignment Receiver sampling point center bit. Static alignment measured absolute difference left right edge shifts (|tSH_L tSH_R|) until character error occurs. Receiver (Unit Interval) calculated 1/(fREF*N) when operated 8-bit mode 10-bit mode data being received, 1/(fREF*N) remote transmitter data being received. operating link this equivalent when REFCLK character rate. alternate multiply ratios selected SPDSEL RANGESEL), numerator multiplied respectively. Error Free Window measure time window between centers where transition occur without causing sampling error. measured over operating range, input jitter specification Duty Cycle Distortion (DCD), Data Dependant Jitter (DDJ), Random Jitter (RJ). Parallel data output specifications only valid outputs loaded with similar loads.
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CY7C9689A Transmitter Switching Characteristics Over Operating Range
Parameter tB[23] tRISE tFALL Time PECL Output Rise Time 20-80% (PECL Test Load) Deterministic Jitter (peak-peak) Random Jitter [16, Transmitter Total Output Jitter (peak-peak)[16]
[16, [16]
Description
Min. 20.0
Max. 1700 1700 0.02 0.008 0.08
Unit
PECL Output Fall Time 80-20% (PECL Test Load)[16]
CY7C9689A HOTLink Transmitter Switching Waveforms
Write Cycle Asynchronous (FIFO) Interface EXTFIFO HIGH tTXCLK FIFOBYP HIGH tTXCPWH
TXCLK
tTXCPWL
tTXDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
tTXDH Note
tTXENH
OPERATION
tTXENS
tTXA tTXA
TXFULL TXHALF TXEMPTY
Notes While sending continuous outputs loaded 1.3V, over operating range. While sending continuous after 100,000 samples measured cross point differential outputs, time referenced REFCLK input, over operating range. When EXTFIFO HIGH, write data captured clock cycle following TXEN HIGH.
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CY7C9689A HOTLink Transmitter Switching Waveforms (continued)
Write Cycle Asynchronous (FIFO) Interface EXTFIFO FIFOBYP HIGH
TXCLK
tTXDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
tTXDH Note
tTXENS
tTXENH
OPERATION
tTXA TXFULL TXHALF TXEMPTY
tTXA
OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO HIGH FIFOBYP HIGH
TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
OPERATION
Note tTXRSS tTXRSH
TXRST
tTXCES
tTXCEH
tTXOE
TXFULL TXHALF TXEMPTY
tTXOAZ
tTXOZA
Notes Illustrates timing only. TXEN TXRST usually active same time period. When transferring data Transmitter input from depth expanded external FIFO, data captured from external FIFO clock cycle following actual enable (TXEN HIGH).
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CY7C9689A HOTLink Transmitter Switching Waveforms (continued)
OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO FIFOBYP HIGH
TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
OPERATION
tTXRSS
TXRST TXRST
tTXRSH
Note tTXCES tTXCEH
tTXOE
TXFULL TXHALF TXEMPTY
tTXOAZ
tTXOZA Write Cycle Synchronous Interface EXTFIFO HIGH FIFOBYP
REFCLK
tREFCLK tREFH tREFL
tREFDS
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
tREFDH Note
tREFENH
OPERATION
tREFENS
TXFULL TXHALF TXEMPTY
tTRA
tTRA
Note \When transferring data Transmitter input from synchronous external controller, data captured same clock cycle actual enable (TXEN LOW).
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CY7C9689A HOTLink Transmitter Switching Waveforms (continued)
Write Cycle Synchronous Interface EXTFIFO FIFOBYP
REFCLK
tREFDS
TXHALT TXSC/D TXDATA[7:0] XDATA[9:8]/TXCMD[2:3] TXCMD[1:0]
tREFDH Note
tREFENS
TXEN
tREFENH
OPERATION
TXFULL TXHALF TXEMPTY
OUTPUT ENABLE Timing Synchronous Interface EXTFIFO HIGH FIFOBYP
REFCLK
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
tREFENH
OPERATION
tREFENS tREFCES tREFCEH
tREFOE
TXFULL TXEMPTY
tREFAZ
tREFZA
Note inhibited reads, Receive FIFO goes empty, data outputs change.
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CY7C9689A HOTLink Transmitter Switching Waveforms (continued)
OUTPUT ENABLE Timing Synchronous Interface EXTFIFO FIFOBYP
REFCLK
TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN
OPERATION
TXFULL TXEMPTY
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CY7C9689A HOTLink Receiver Switching Waveforms
Read Cycle Asynchronous (FIFO) Interface EXTFIFO HIGH FIFOBYP HIGH tRXCLKOD tRXCPWH
RXCLK
tRXCLKOP tRXCLKIP tRXCLKOD tRXCPWL
tRXENS
RXEN
READ
tRXENH
OPERATION READ
tRXA
RXEMPTY
tRXA
FIFO EMPTY
Note
RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0]
VALID DATA
Note
Read Cycle Asynchronous (FIFO) Interface EXTFIFO FIFOBYP HIGH
RXCLK
tRXENS
RXEN
READ
tRXENH
tRXA
RXEMPTY RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0]
tRXA
FIFO EMPTY
VALID DATA
Note
Notes When reading data from synchronous data interface, data captured clock cycle that RXEN LOW. RXEMPTY HIGH indicates data available. RXEMPTY indicates that FIFO empty. Illustrates timing only. RXEN RXRST usually active same time period. Receive FIFO Reads inhibited while outputs High-Z.
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CY7C9689A HOTLink Receiver Switching Waveforms (continued)
Output Enable Timing
RXCLK
tRXENS
RXEN
tRXENH
OPERATION
Note
RXRST
tRXRSS tRXCES
tRXRSH
tRXCEH
tRXOE
RXFULL RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0]
DATA
tRXAZ Note
tRXZA
tREFCLK tREFL tREFH
REFCLK
Static Alignment
tB/2- INA± INB± SAMPLE WINDOW tB/2-
Error-Free Window
tEFW INA± INB± CENTER CENTER
Table HOTLink TAXI-compatible Encoder Patterns 4B/5B Encoder Data 4-bit Binary Data[41] 0000 0001 5-bit Encoded Symbol[42, 11110 01001 Data 5B/6B Encoder 5-bit Binary Data[41] 00000 00001 6-bit Encoded Symbol[42, 110110 010001
Notes Binary Input Data parallel input data which input Transmitter output from Receiver. Binary bits listed from left right following order: 8-Bit mode (BYTE8/10 HIGH TXSC/D RXSC/D LOW)-TXDATA/RXDATA[7], [6], [5], [4], TXDATA/RXDATA[3], [2], [1], [0]; 10-Bit mode (BYTE8/10 TXSC/D RXSC/D LOW)-TXDATA/RXDATA[8], [7], [6], [5], [4], TXDATA/RXDATA[9], [3], [2], [1], [0]. ENCODED Symbols shown here "ones zeros", converted from NRZI stream transmitter output receiver input. NRZI represents "one" state transition (either LOW-to-HIGH HIGH-to-LOW) "zero" transition within interval. Encoded Serial Symbol bits shifted with most significant (Left-most) most significant nibble coming first. Binary parallel input data which input Transmitter output from Receiver. Binary bits listed from left right following order: 8-Bit mode (BYTE8/10 HIGH TXSC/D RXSC/D HIGH)-TXCMD/RXCMD[3], [2], [1], [0]; 10-Bit mode (BYTE8/10 TXSC/D RXSC/D HIGH)-TXCMD/RXCMD[1], [0]. While these Commands legal data will disrupt normal operation used occasionally, they cause data errors grouped into recurrent fields. Normal operation cannot guaranteed more these commands continuously repeated.
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Table HOTLink TAXI-compatible Encoder Patterns (continued) 4B/5B Encoder Data 4-bit Binary Data[41] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5-bit Encoded Symbol[42, 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 Data 5B/6B Encoder 5-bit Binary Data[41] 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 10001 11001 11010 11011 11100 11101 11110 11111 6-bit Encoded Symbol[42, 100100 100101 010010 010011 010110 010111 100010 110001 110111 100111 110010 110011 110100 110101 111110 011001 101001 101101 011010 011011 011110 011111 101010 101011 101110 101111 111010 111011 111100 111101
Table HOTLink TAXI Compatible Command Symbols CY7C9689A (Transmitter) Command Input TXCMD[3:0] Binary CMD[44] 0000 Encoded Symbol[42, 11000 10001 Mnemonic (8-bit SYNC) CY7C9689A (Receiver) Command Output RXCMD[3:0] Binary CMD[44] 0000
8-bit mode (BYTE8/10 HIGH)
Note Signals labeled italics internal CY7C9689A.
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Table HOTLink TAXI Compatible Command Symbols (continued) CY7C9689A (Transmitter) Command Input TXCMD[3:0] 8[45] 9[45] A[45] D[45] E[45] F[45] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11111 11111 01101 01101 01101 11001 11111 00100 01101 00111 11001 00111 11001 11001 00100 00100 00100 11111 00100 00000 00111 00111 00111 11001 00000 00100 00000 11111 00000 00000 011000 100011 111111 111111 011101 011101 011101 111001 (10-bit SYNC) I'I' T'T' T'S' CY7C9689A (Receiver) Command Output RXCMD[3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
10-bit mode (BYTE8/10 LOW)
Functional Description
interconnection more CY7C9689A Transceivers forms general-purpose communications subsystem capable transporting user data MBytes second over several types serial interface media. CY7C9689A highly configurable with multiple modes operation. transmit section CY7C9689A, data moves from input register, through Transmit FIFO, 4B/5B Encoder. encoded data then shifted serially OUTx± differential PECL compatible drivers. bit-rate clock generated internally from 2.5x, clock multiplier. more complete description found section CY7C9689A HOTLink Transmit-Path Operating Mode Description. receive section CY7C9689A, serial data sampled receiver INx± differential line receiver inputs. receiver clock data recovery locks onto selected serial stream generates internal bit-rate sample clock. stream deserialized, decoded, presented Receive FIFO, along with character clock. data FIFO then read either slower faster than incoming character rate. more complete description found section CY7C9689A HOTLink Receive-Path Operating Mode Description.
Transmitter Receiver parallel interface timing functionality configured Cascade directly external FIFOs depth expansion, couple directly registers, couple directly state machines. These interfaces accept output either: 8-bit characters 10-bit characters 10-bit pre-encoded characters (pre-scrambled pre-encoded) 12-bit pre-encoded characters (pre-scrambled pre-encoded). numbering content parallel transmit interface shown Table When operated with 4B/5B, 5B/6B Encoder bypassed, TXSC/D RXSC/D bits ignored. HOTLink Transceiver serial interface provides seamless interface various types media. minimal number external passive components required properly terminate transmission lines provide LVPECL loads. power supply decoupling, single capacitor range 0.02 required power/ground pair. Additional information interfacing these components various media found HOTLink Design Considerations application note.
Note Signals shown dotted lines represent differences timing active state signals when operated Cascade Timing.
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CY7C9689A TAXI HOTLink Transmit-Path Operating Mode Descriptions
TAXI HOTLink Transmitter configured into several operating modes, each providing different capabilities fitting different transmission needs. These modes selected using FIFOBYP, ENCBYP BYTE8/10 inputs CY7C9689A Transceiver. These modes reduced five primary classes: Synchronous Encoded Synchronous Pre-encoded Asynchronous Encoded Asynchronous Pre-encoded. Synchronous Encoded this mode, Transmit FIFO bypassed, while 4B/5B, 5B/6B encoder enabled. character accepted Transmit Input Register rising edge REFCLK, passed Encoder where encoded serial transmission. Serializer operates synchronous REFCLK, which multiplied generate serial data bit-clock. this mode TXRST TXHALT inputs interpreted tied either HIGH LOW. place CY7C9689A into synchronous modes, FIFOBYP must LOW. This mode usually used products that must meet specific predefined protocol requirements, cannot tolerate uncontrolled insertion SYNC fill characters. host system required provide data every rising edge REFCLK (along with TXEN) maintain data stream. TXEN asserted, Encoder loaded with sync characters. Input Register Mapping Encoded modes, bits TXDATA input mapped into characters shown Table including TXSVS bit, eight bits data, TXSC/D select either Special Character codes Data characters. TXSC/D controls encoding TXDATA[7:0] TXDATA[9:0] bits each character. used identify input character represents Data Character Special Character code. TXSC/D LOW, character appeared TXDATA encoded using Data Character codes listed Table TXSC/D HIGH, character TXCMD encoded using Special Character codes listed Table Synchronous Pre-encoded synchronous pre-encoded mode, both Transmit FIFO 4B/5B encoder bypassed, data passes directly from Transmit Input Register Serializer. Serializer operates synchronous REFCLK, which multiplied when BYTE8/10 HIGH selected SPDSEL RANGESEL inputs) generate serial data bit-clock. this mode, part TXCMD inputs used part data input bus. place CY7C9689A into synchronous modes, FIFOBYP must LOW. This mode usually used products containing external encoders scramblers, that must meet specific protocol
requirements. host system required provide data every rising edge REFCLK (along with TXEN) maintain data stream. TXEN asserted, Serializer loaded with sync characters. this mode each input character (TXDATA[0]) shifted first, followed sequentially TXDATA[1] through TXDATA[9] (TXDATA[11] when BYTE8/10 LOW). Asynchronous Encoded Asynchronous Encoded mode, both Transmit FIFO Encoder enabled. This provides characters data buffering. Serializer operates synchronous REFCLK, which multiplied 2.5, generate serial data bit-clock selected SPDSEL RANGESEL). this mode TXRST TXHALT inputs interpreted. This mode supports same Input Register mapping Synchronous Encoded mode. Because both Transmit FIFO Encoder enabled, input FIFO loaded rate supported FIFO MHz), without generating decoder errors receive link.
CY7C9689A TAXI HOTLink Receive-Path Operating Mode Descriptions
HOTLink Receiver configured into several operating modes, each providing different capabilities fitting different reception needs. These modes selected using FIFOBYP, ENCBYP, BYTE8/10 inputs CY7C9689A Transceiver. These modes reduced four primary classes: Synchronous Decoded Synchronous Undecoded Asynchronous Decoded Asynchronous Undecoded. these modes, serial data received differential line receiver inputs routed Deserializer Framer. clock data recovery block used extract bit-rate clock from transitions data stream, uses that clock capture bits from serial stream. These bits passed Deserializer where they formed into 12-bit characters. align incoming stream proper character boundaries, Framer must enabled asserting RFEN HIGH. Framer logic-block checks incoming stream unique pattern that defines character boundaries. This logic filter looks (when BYTE8/10 LOW) sync character. Once sync character found, Framer captures offset data stream from present character boundaries, resets boundary reflect this offset, thus framing data correct character boundaries. Since noise induced errors cause incoming data corrupted, since many combinations corrupt legal data create aliased sync character, framer also disabled deasserting RFEN LOW. Synchronous Decoded these modes, Receive FIFO bypassed, while 5B/4B, 6B/5B Decoder enabled. Framed characters output from Deserializer decoded, passed directly Page
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Receive Output Register. Deserializer operates synchronous recovered bit-clock, which divided generate output RXCLK clock. this mode RXRST input interpreted biased either HIGH LOW. These modes usually used products that must meet specific protocol requirements. decoded characters provided RXDATA outputs once every rising edge RXCLK. RXEMPTY asserted LOW, characters RXCMD output register sync character, discard policy non-0. Because decoder enabled, received characters checked compliance 4B/5B decoding rules. Output Register Mapping RXDATA[11:0] output mapped into character consisting eight bits data four bits command, bits data bits command. accompanying RXSC/D identifies character either command data. Violation (VLTN) output indicates code violation occurred. When VLTN output asserted HIGH, this indicates transmission error detected character current transfer clock cycle. Synchronous Undecoded this mode, both Receive FIFO 5B/4B, 6B/5B Decoder bypassed, data passes directly from Deserializer output register. Deserializer operates synchronous recovered bit-clock, which divided generate output RXCLK clock. this mode RXRST input interpreted biased either HIGH LOW. This mode usually used products containing external decoders descramblers that must meet specific protocol requirements. data provided RXDATA outputs once every rising edge RXCLK. Received characters checked specific coding requirements decoding errors reported. Asynchronous Decoded Asynchronous Decoded mode, both Receive FIFO Decoder CY7C9689A enabled. deserializer operates synchronous recovered bit-clock, which divided generate Receive FIFO write clock. Characters read from Receive FIFO, using external RXCLK input, when addressed selected RXEN. this mode RXRST input interpreted.
Asynchronous Decoded mode supports same Output Register mapping Synchronous Decoded mode. Because both Receive FIFO Decoder enabled, output FIFO read rate supported FIFO, however, Receive FIFO ever indicates full condition (RXFULL asserted), data lost. Asynchronous Undecoded Asynchronous Undecoded modes, Receive FIFO enabled. This means that characters received from serial interface written Receive FIFO before being passed output register. Deserializer operates synchronous recovered bit-clock, which divided generate Receive FIFO write clock. Data read from Receive FIFO, using RXCLK input clock, when addressed selected RXEN. These modes usually used products containing external decoders descramblers, that must meet specific protocol requirements. data read from Receive FIFO time that FIFO status flags indicate non-empty condition (RXEMPTY deasserted). ensure that data lost, Receive FIFO must read faster than data loaded into Receive FIFO. receiver provide framed characters, necessary transmit include sync characters data stream. This done operating transmitter encoded mode writing characters into data stream operating transmitter pre-encoded mode writing 10-bit value encoded (1100010001) (011000100011) character data stream enabling transmitter when operated synchronous mode, allowing transit FIFO empty when operated asynchronous mode.
BIST Operation Reporting
CY7C9689ADX HOTLink Transceiver incorporates same Built-In Self-Test (BIST) capability. This link diagnostic uses Linear Feedback Shift Register (LFSR) generate 511-character repeating sequence that compared, character-for-character, receiver. BIST mode intended check entire high-speed serial link full link-speed, without specialized expensive test equipment. complete sequence characters used BIST documented Table
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CY7C9689A
Figure Built-In Self-Test Illustration
Enable BIST Start BIST BIST LOOP
TXCLK TXBISTEN TXEMPTY TXHALF TXFULL TXCMD[1:0] TXSC/D TXDATA[9:0] TXEN REFCLK
OUTA± OUTB±
Don't Care
enable FIFO Flags
enable VLTN reads Ignore these outputs ERROR Forced indicate EMPTY BIST BIST LOOP
Start BIST Wait Enable BIST
Start BIST match
RXEN RXDATA[9:0] RXSC/D RXCMD[1:0] VLTN RXEMPTY RXHALF RXFULL RXBISTEN RXCLK
CY7C9689A
INA± INB±
HIGH select
BIST Enable Inputs There separate BIST enable inputs transmit receive paths CY7C9689A. These inputs both active LOW; i.e., BIST enabled respective section device when BIST enable input determined logic-0 level. Both BIST enable inputs asynchronous; i.e., they synchronized inside CY7C9689A internal state machines. BIST Transmit Path transmit path operation with BIST controlled TXBISTEN input overrides most other inputs (see Figure When Transmit FIFO enabled (not bypassed) TXBISTEN recognized internally, reads from Transmit FIFO suspended BIST generator enabled sequence character repeating BIST sequence. recognition occurs middle data field, following data transmitted that time, remains Transmit FIFO. Once TXBISTEN signal removed, data Transmit FIFO again available transmission. ensure proper data handling destination, transmit host controller should either TXHALT prevent transmission data specific boundaries, allow Transmit FIFO completely empty before enabling BIST. With transmit BIST enabled, Transmit FIFO remains available loading data. written normal maximum limit while BIST operation takes place. allow Document 38-02020 Rev.
removal stale data from Transmit FIFO, also reset during BIST operation. reset operation proceeds documented, with exception information presented TXEMPTY FIFO status flag. Since this flag used present BIST loop status, continues reflect state transmit BIST loop status until TXBISTEN longer recognized internally. completion reset operation still monitored through TXFULL FIFO status flag. TXEMPTY flag, when used transmit BIST progress indication, continues reflect active HIGH active settings determined UTOPIA Cascade timing model selected EXTFIFO; i.e., when configured Cascade timing model, TXEMPTY TXFULL FIFO flags active HIGH, when configured UTOPIA timing model TXEMPTY TXFULL FIFO flags active LOW. illustration Figure uses UTOPIA conventions. When TXBISTEN first recognized, TXEMPTY flag clocked reset state, regardless addressed state Transmit FIFO not), driven part unless been sampled asserted (LOW). Following this, each completed pass through BIST loop, TXEMPTY flag interface clock period (TXCLK REFCLK). TXEMPTY flag remains until interface addressed state TXEMPTY been observed.
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device addressed sampled LOW), flag remains internally regardless number TXCLK clock cycles that processed. device status polled sufficiently regular basis, possible host system miss more these BIST loop indications. pass through loop defined that condition where Encoder generates 0x00 (where denotes number, e.g. 0x00 denotes HEX00) state. Depending initial state BIST LFSR, first pass through loop occur substantially less than character periods. Following first pass, long TXBISTEN remains LOW, remaining passes exactly characters length. When Transmit FIFO bypassed, interface clocked REFCLK signal instead TXCLK. While active asserted state TXEMPTY signal still controlled EXTFIFO, state completed BIST loops longer preserved. Instead, TXEMPTY flag reflects dynamic state BIST loop progress, asserted only once every character periods. interface addressed time that this occurs, then FIFO status flags remain high-Z state loop event lost. BIST Receive Path receive path operation BIST similar that transmit path. While Receive FIFO enabled (not bypassed) RXBISTEN recognized internally, writes Receive FIFO suspended. data present Receive FIFO when RXBISTEN recognized remains FIFO cannot read until BIST operation complete. data Receive FIFO remains valid, available reading through host parallel interface. This because error output indicator receive BIST operations VLTN signal, which normally part RXDATA bus. prevent read operations while BIST operation, RXEMPTY RXHALF flags forced indicate Empty condition. Once RXBISTEN been removed recognized internally, Receive FIFO status flags updated reflect current content status Receive FIFO. allow removal stale data from Receive FIFO, reset during BIST operation. reset operation proceeds documented, with exception that RXEMPTY RXHALF status flags already indicate empty condition. RXFULL flag used present BIST progress. active (asserted) state RXFULL (and RXEMPTY) remain controlled present operating mode interface timing model (UTOPIA Cascade). When RXBISTEN been recognized, RXFULL becomes receive BIST loop indicator (regardless logic state FIFOBYP). When RXBISTEN first recognized, RXFULL flag clocked state, regardless addressed state Receive FIFO sampled not). Following this, RXFULL remains until receiver detects start BIST pattern. Then RXFULL deasserted duration BIST pattern, pulsing asserted RXCLK period last symbol each BIST loop. consecutive characters received error, RXFULL returns state until start BIST sequence again detected. Just like BIST status flag transmit data path, RXFULL flag captures asserted states, keeps them Document 38-02020 Rev.
until they read. This means that status flag read regular basis, events lost. detection errors presented VLTN output. Unlike RXFULL FIFO status flag, active state this output controlled EXTFIFO input. With Receive FIFO enabled, these outputs should operate same RXFULL flag, with respect preserving detection state error until read. Unlike RXFULL flag, which only needs CY7C9689A addressed sampled RXCLK) enable RXFULL three-state driver, RXCLK "read" flag, VLTN output requires selection (assertion RXEN while addressed) enable RXDATA three-state drivers. selection process necessary ensure that multi-PHY implementation does enable multiple VLTN drivers same time. When Receive FIFO bypassed, interface clocked RXCLK output signal. While active asserted state RXFULL signal still controlled EXTFIFO input, state completed BIST loops detected errors longer preserved. Instead, RXFULL flag reflects dynamic state BIST loop progress, asserted only once every character periods. interface addressed time that this occurs, then FIFO status flags remain high-Z state loop event lost. This also true VLTN output, such that CY7C9689A receive path selected enable RXDATA three-state drivers, detection BIST miscompare lost. BIST Three-state Control When BIST enabled either transmitter receiver, three-state enable signals BIST status flags error indicators work same normal data processing. output drivers BIST status that presented FIFO status flags only enabled when been sampled asserted (LOW) respective clock (TXCLK, RXCLK, REFCLK). access BIST error information, necessary perform read cycle addressed receiver. This means that must enable receiver (Rx_Match), RXEN must asserted from HIGH select device. Because part BIST, data read from FIFO, data driven. This allows VLTN indicator driven onto RXDATA bus. long RXEN remains asserted, receiver stays selected, data remains driven, VLTN meaning.
Interfacing
parallel transmit receive host interfaces CY7C9689A configurable either synchronous asynchronous operation. Each these configurations supports selectable timing control models Shared Cascade. asynchronous configurations have internal Transmit Receive FIFOs enabled. This allows data written read from these FIFOs rate maximum 50-MHz clock rate FIFOs. internal operations CY7C9689A external TXCLK RXCLK, instead make synthesized derivatives
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CY7C9689A
REFCLK transmit path operations recovered character clock receive path operations. synchronous configurations require interface operations synchronous REFCLK transmit path recovered clock (output RXCLK) receive path. internal FIFOs bypassed synchronous modes. supported timing control models Shared Cascade. Shared based timing model FIFO with active FIFO status flags read/write enables. Cascade timing model modification Shared model that changes flags FIFO read/write enables active HIGH. This model present primarily allow depth expansion internal FIFO direct coupling external CY7C42x5 synchronous FIFOs. allow this direct coupling, cycle-to-cycle timing between transmit receive enables (TXEN RXEN) also modified ensure correct data transfer. These four configurations operation timing/control used with without external FIFOs. Depending specific mode selected, amount external hardware necessary properly couple CY7C9689A state machines external FIFOs minimal cases, zero proper configuration selected. With only minor exceptions, configurations CY7C9689A Shared mode borrowed concepts from AForum's UTOPIA operation. concepts addressing selection control enabled/disabled state output drivers, when data written read from part. Shared Interface Concept CY7C9689A Parallel Interface designed interfacing Shared Bus. maximum TXCLK RXCLK frequency MHz, which provides total bandwidth 50Million characters second each direction. More than CY7C9689A serviced same full serial line speed. CY7C9689A designed Slave Master-Slave type shared architecture. Generally, Master Medium Access Device, MAC) higher layer device that sources going data/command sinks incoming data/command to/from Slaves (CY7C9689A) shared (see Figure Figure Shared Architecture Master
TXDATA/TXCMD RXDATA/RXCMD Status, Control
data (TXDATA, RXDATA), command (TXCMD, RXCMD) FIFO status flags (TXFULL, RXEMPTY, etc.) each CY7C9689A shared connected together respectively. Each Slave assigned address. address each Slave decoded decoder which drives input each Slave. Master will poll each Slave selecting "Addressing") device, sample FIFO flags. Depending FIFOs status each Slave device, Master schedule read accesses Slaves which have data RXFIFOs, write accesses Slaves which have room TXFIFOs. While data being transferred data/command bus, Master continue poll each Slave device independently. Device Selection actions Shared interface controlled Chip Enable selection states interface. These states control read write access Receive Transmit FIFOs, access FIFO status flags, reset Transmit Receive FIFOs, read write access Serial Address Register. CY7C9689A supports concept "address match" through single Chip Enable (CE) input. Address Match FIFO Flag Access CY7C9689A makes single active-LOW Chip Enable (CE) generate address-match conditions. This allows multiple CY7C9689A devices share common bus, with device output three-state controls being managed either address match condition sampled LOW), selection state. Transmit Receive FIFO flag output drivers enabled TXCLK, REFCLK, RXCLK cycle following being sampled asserted (LOW) rising edge respective clock. input sampled separately clocks transmit receive interfaces, which allows these clocks both asynchronous each other, operate different clock rates. example both Transmit Receive FIFO flag access shown Figure Figure FIFO Flag Driver Enables.
TXCLK TXFULL Valid
Transmit Port Addressing
RXCLK RXEMPTY Valid
CY7C9689A
CY7C9689A
CY7C9689A
Receive Port Addressing
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When Transmit FIFO enabled (FIFOBYP HIGH) sampled rising edge TXCLK, output drivers TXFULL TXEMPTY FIFO flags enabled. When sampled HIGH rising edge TXCLK, these same output drivers disabled. When Transmit FIFO bypassed (FIFOBYP byte-packed mode) sampled rising edge REFCLK, output drivers TXFULL TXEMPTY FIFO flags enabled. When sampled HIGH rising edge REFCLK, FIFO flag output drivers disabled. When sampled rising edge RXCLK (input output), output drivers RXFULL RXEMPTY FIFO flags enabled. When sampled HIGH rising edge RXCLK, FIFO flag output drivers disabled. Device Selection concept selection used control access transmit receive parallel-data ports device. There three primary types selection: Transmit data selection (with without internal Transmit FIFO) Receive data selection (with without internal Receive FIFO) Continuous selection (for either both transmit receive interfaces). addition these normal selection types, there additional sequences that used control internal Transmit Receive FIFOs reset operations, control read/write access Serial Address Register: Transmit reset sequence Receive reset sequence. these operations, transmit data selection transmit reset sequence mutually exclusive cannot exist same time. receive data selection receive reset sequence also mutually exclusive cannot exist same time. Either transmit operation exist same time either receive operation.
normal forms selection require that Chip Enable must asserted sampled LOW) either same time selection control signal being sampled asserted, more clock cycles prior selection control signal being sampled asserted. Transmit Data Selection Asynchronous With Shared Timing Control (Transmit FIFO Enabled) When sampled TXRST sampled HIGH rising edge TXCLK, Tx_Match condition generated. This Tx_Match condition continues until sampled HIGH TXRST sampled rising edge TXCLK. When Tx_Match Tx_RstMatch) condition present, TXEMPTY TXFULL output drivers enabled. When Tx_Match Tx_RstMatch) condition present, these same drivers disabled (High-Z). selection state Transmit FIFO entered when Tx_Match condition present, TXEN transitions from HIGH LOW. Once selected, Transmit FIFO remains selected until TXEN sampled HIGH rising edge TXCLK. selected state, data present TXDATA inputs captured stored Transmit FIFO. This transmit interface selection process shown Figure Synchronous With Shared Timing Control (Transmit FIFO Bypassed) When Transmit FIFO bypassed (FIFOBYP byte-packed mode), CY7C9689A must still selected write data into Transmit Input Register. When sampled TXRST sampled HIGH rising edge REFCLK, Tx_Match condition generated. This Tx_Match condition continues until sampled HIGH TXRST sampled rising edge REFCLK. When Tx_Match Tx_RstMatch) condition present, TXEMPTY TXFULL output drivers enabled (with Transmit FIFO bypassed, status flags normally indicate Empty condition). When Tx_Match Tx_RstMatch) condition present, these same drivers disabled (High-Z).
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Figure Transmit Selection with Transmit FIFO Enabled
TXCLK TXRST Tx_Match
[46]
TXEN Tx_Selected TXDATA/TXCMD
(Shared Timing)
Note [46]
TXDATA/TXCMD
(Cascade Timing)
TXFULL
Full
Note
Full
selection state Transmit Input Register entered when Tx_Match condition present, TXEN transitions from HIGH LOW. Once selected, transmit input register remains selected until TXEN sampled HIGH rising edge REFCLK. selected state, data present TXDATA inputs captured Transmit Input Register passed Serializer Encoder selected ENCBYP input). This transmit interface selection process shown Figure When 4B/5B Encoder enabled data written Transmit Input Register, data stream automatically padded with SYNC characters. When 4B/5B, 5B/6B Encoder disabled data written Transmit Input Register, SYNC characters also automatically padded with SYNC characters.
Receive Data Selection Asynchronous With Shared Timing Control (Receive FIFO Enabled) When sampled RXRST sampled HIGH rising edge RXCLK input, Rx_Match condition generated. This Rx_Match condition continues until sampled HIGH RXRST sampled rising edge RXCLK input. When Rx_Match Rx_RstMatch) condition present, RXEMPTY RXFULL output drivers enabled. When Rx_Match Rx_RstMatch) condition present, these same drivers disabled (High-Z).
Notes Signals shown dotted lines indicate timing levels when configured external FIFOs (EXTFIFO HIGH). Signal names listed italics internal signals, shown reference only.
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selection state Receive FIFO entered when Rx_Match condition present, RXEN transitions from HIGH LOW. Once selected, Receive FIFO remains selected until RXEN sampled HIGH rising edge
RXCLK input. selected state initiates read cycle from Receive FIFO enables Receive FIFO data onto RXDATA bus. This receive interface selection process shown Figure
Figure Transmit Selection with Transmit FIFO Bypassed
REFCLK TXRST
[46]
Tx_Match
TXEN
[46]
Note
Tx_Selected TXDATA/TXCMD
(Shared Timing)
TXDATA/TXCMD
(Cascade Timing)
TXFULL
Full
Note
Full
Synchronous With UTOPIA Timing Control (Receive FIFO Bypassed) When Receive FIFO bypassed (FIFOBYP LOW), CY7C9689A must still selected enable output drivers RXDATA bus. With Receive FIFO bypassed, RXCLK becomes synchronous output clock operating character rate. When sampled RXRST sampled HIGH rising edge RXCLK output, Rx_Match condition generated. This Rx_Match condition continues until sampled HIGH RXRST sampled rising edge RXCLK. When Rx_Match Rx_RstMatch) condition present, RXEMPTY RXFULL output drivers enabled. With
Receive FIFO bypassed, these flags normally indicate non-empty condition indicate empty SYNC character present output register receiver discard policy non-0. When Rx_Match Rx_RstMatch) condition present, these same drivers disabled (High-Z). selection state Receive Output Register entered when Rx_Match condition prese
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