IW4017B -stageJohnson counter having decode outputs. shaping that allo

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IW4017B -stageJohnson counter having decode outputs. shaping that allo

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IW4017B
IW4017B -stageJohnson counter having decode outputs. shaping that allows unlimited clock input pulse rise fall times. counter advanced count positive clock signal transition CLOCK INHIBITsignal low. Counter advancement clock line isinhibited when CLOCK INHIBIT signal high. high RESET signal clears counter zero count. Johnson counter configuration permits highspeed operation, input decode-gating spike-free decoded outputs. Anti-lock gating provided, thus assuring proper counting sequence. decoded Outputs normally high only their YOUT Inputs include CLOCK, RESET, CLOCK INHIBIT signal. Schmitt trigger action CLOCK input circuit provides pulse
respective decoded time slot. Each decoded output remains high full clock cycle. Signal completes cycle every clock input cycles.
Features
Operating Voltage Range: over full packageMaximum input current temperature range ;100 Noise margin (over full package temperature range): supply 10.0 supply 15.0 supply
Assignment
Logic Diagram Function Table
Clock Clock Enable Reset Output State
Package
PIN16
change change reset counter Q0=H, Q1-Q9=L, C0=H Advance next state change change Advance next state
Carry Out=H ,Q1,Q2,Q3 Q4=H Carry otherwise, care
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4017B
Absolute Maximum Ratings
Symbol VOUT Tstg Parameter Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Power Dissipation Still Air, Plastic Value -0.5 -0.5 -0.5 Unit
SOIC Package Power Dissipation Output Transistor Storage Temperature Lead Temperature, from Case Seconds (Plastic SOIC Package)
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: from 65°to SOIC Package from
Recommended Operating Conditions
Symbol VOUT Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Unit
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, should constrained range (VIN VOUT) Unused inputs must always tied appropriate logic voltage level (e.g., either Unused outputs must left open.
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4017B
Electrical Characteristics
Symbol Parameter Test Conditions (Voltages Referenced GND) Guaranteed Limit -55° 4.95 9.95 14.95 13.5 0.05 0.05 0.05 0.64 -0.64 4.95 9.95 14.95 13.5 0.05 0.05 0.05 0.51 -0.51 4.95 9.95 14.95 13.5 0.05 0.05 0.05 0.36 -0.36 1.15 Unit
Minimum High-Level VOUT=0.5 Input Voltage VOUT=1.0 VOUT=1.5 Maximum Level Input Voltage VOUT=0.5 VOUT=1.0 VOUT=1.5
Minimum High-Level VIN=GND Output Voltage =1.5V, VIH=3.5V, IO=-1µA =3.0V, VIH=7.0V, IO=-1µA =4.0V, VIH=11V, IO=-1µ
Maximum Low-Level Output Voltage
VIN=GND
=1.5V, VIH=3.5V, IO=1µ =3.0V, VIH=7.0V, IO=1µ =4.0V, VIH=11V, IO=1µ Maximum Input Leakage Current VIN= VIN=
Maximum Quiescent Supply Current (per Package) Minimum Output (Sink) Current
VIN= VOL=0.4 VOL=0.5 VOL=1.5 VIN= VOH=4.6 VOH=2.5 VOH=9.5 VOH=13.5
Minimum Output High (Source) Current
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4017B
Electrical Characteristics
Symbol fmax Parameter Maximum Clock Frequency =50pF, =200 Input Guaranteed Limit -55° 125° Unit
tPLH, tPHL MaximumPropagation Delay, Clock Decode Output (Figure tPLH, tPHL Maximum Propagation Delay, Clock Carry Output (Figure Maximum Output Transition Time, Carry Output Decode Output (Figure Maximum Propagation Delay, Reset Output Decode Output (Figure Maximum Input Capacitance
tTLH, tTHL
tPLH, tPHL Carry
Timing Requirements
Symbol Parameter
(VCC=5.0V 10%, =50pF, =200 -55°
Input 125°
Unit
Minimum Pulse Width, Clock (Figure
Maximum Input Rise Fall Times, Clock (Figure Minimum Pulse Width, Reset (Figure
UNLIMITED
trem
Minimum Removal Time, Reset (Figure
Minimum Setup Time, Clock Inhibit Clock (Figure
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4017B
CLOCK INHIBI RESET DECODE
CLOCK
DECODE OUTPU
CARRY OUTPU
Figure Switching Waveforms
Timing diagram
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4017B
Expanded Logic Diagram
Address
Postalcode:100039 Tel: 86-010-58895780 Http://www.estek.com.cn Email:sales@estek.com.cn
6A06-6A07 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
010-58895793
No:01-060833
BEIJING ESTEK ELECTRONICS CO.,LTD

IW4017B -stageJohnson counter having decode outputs. shaping that allo

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