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IW4520B

Package

IW4520B
Description
The IW4520B Dual Binary Up-Counter consists two identical, internally synchronous 4- stage counters. The counter stages are D- type flip-flops having interchang eable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition.For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK.The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable i nput of the subsequent counter while the CLOCK of the latter is held low. input
Features
Operating Voltage Range: 3.0 to 18 V Maximum input current of 1u A at 18 V over full packagetemperature range 100 nA at 18 V and 25 C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply 16 DIP - 16
Package
Pin Assignment
Logic Diagram
CLOCK A ENABLE A
ENABLE CLOCK B
RESET A
Function Table
11 CLOCK B 9 ENABLE B 10
Inputs CLOCK L X X L H X ENABLE H RESET L L L L L L
RESET
BEIJING ESTEK ELECTRONICS CO., LTD
IW4520B
Absolute Maximum Ratings
SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW / ° from 65 ° 125 ° C to C SOIC Package: : - 7 mW / ° from 65° to 125° C C
Recommended Operating Conditions
Symbol VCC VIN , VOUT TA
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types
Min 3.0 0 -55
Max 18 VCC 125
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND (VIN or VOUT) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC Unused outputs must be left open.
BEIJING ESTEK ELECTRONICS CO., LTD
IW4520B
DC Electrical Characteristics
Maximum Low-Level Output Voltage
Maximum Input Leakage Current
ICC Maximum Quiescent Supply Current (per Package) IOL Minimum Output Low (Sink) Current
Minimum Output High (Source) Current
BEIJING ESTEK ELECTRONICS CO., LTD
IW4520B
AC Electrical Characteristics
tPHL, tPLH
Maximum Propagation Delay, Clock or Enable to Output (Figures 1, 3) Maximum Propagation Delay, Reset to Output (Figure 2) Maximum Output Transition Time, Any
tTHL, tTLH Output CIN
Maximum Input Capacitance
Timing Requirements
Guaranteed Limit -55° C 25° C125° C 200 100 70 250 110 80 400 200 140 15 5 5 200 100 70 250 110 80 400 200 140 15 5 5 400 200 140 500 220 160 800 400 280 15 5 5
Unit ns
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Enable (Figure 3)
Maximum Input Rise and Fall Times (Figure 1)
BEIJING ESTEK ELECTRONICS CO., LTD
IW4520B
tf Vcc RESET
Vcc GND Vcc
CLOCK
GND tPLH
tPHL OUTPUT tPHL Vcc GND t
OUTPUT
GND Figure 2. Switching Waveforms
t Figure 1. Switching Waveforms
tw Vcc
ENABLE tPLH tPHL OUTPUT
GND Vcc GND
Timing Diagram
1 CLOCK ENABLE
BEIJING ESTEK ELECTRONICS CO., LTD
IW4520B
Expanded Logic Diagram (1 / 2 of the Device)
ENABLE
Address :
Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Http: / / www.estek.com.cn Email:sales@estek.com.cn
6A06-6A07 Rm 6A07, Changyin Office Building , No.88, Yong Ding Road, Hai Dian District , Beijing
Fax : 010-58895793
REV No:01-060837
BEIJING ESTEK ELECTRONICS CO., LTD