IW4520B Dual Binary Up-Counter consists identical, internally synchron

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IW4520B Dual Binary Up-Counter consists identical, internally synchron

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IW4520B
IW4520B Dual Binary Up-Counter consists identical, internally synchronous stage counters. counter stages type flip-flops having interchang eable CLOCK ENABLE lines incrementing either positive-going negative-going transition.For single-unit operation ENABLE input maintained high counter advances each positive-going transition CLOCK.The counters cleared high levels their RESET lines. counter cascaded ripple mode connecting enable nput subsequent counter while CLOCK latter held low. input
Operating Voltage Range: Maximum input current over full packagetemperature range ;100 Noise margin (over full package temperature range): supply 10.0 supply 15.0 supply
Package
Assignment
CLOCK ENABLE RESET
Logic Diagram
CLOCK ENABLE
ENABLE CLOCK
RESET
Function Table
CLOCK ENABLE
Inputs CLOCK ENABLE RESET
Outputs Mode IncrementCounter IncrementCounter Change Change Change Change thru
RESET
PIN16
care
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4520B
Absolute Maximum Ratings
Symbol VOUT Tstg Parameter Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Power Dissipation Still Air, Plastic DIP+ Value -0.5 -0.5 CC0.5 +150 +0.5 +0.5 Unit
SOIC Package+ Power Dissipation Output Transistor Storage Temperature Lead Temperature, from Case Seconds (Plastic SOIC Package)
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. +Derating Plastic DIP: from SOIC Package: from 125°
Recommended Operating Conditions
Symbol VOUT
Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types
Unit
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, should constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either Unused outputs must left open.
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4520B
Electrical Characteristics
(Voltages Referenced GND) Symbol Parameter Minimum High-Level Input Voltage Maximum Level Input Voltage Test Conditions VOUT=0.5 VOUT=1.0 VOUT=1.5 VOUT=0.5 VOUT=1.0 VOUT=1.5 Guaranteed Limit -55° 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 Unit
Minimum High-Level VIN=GND Output Voltage
Maximum Low-Level Output Voltage
VIN=GND
0.05 0.05 0.05
0.05 0.05 0.05
0.05 0.05 0.05
Maximum Input Leakage Current
VIN= VIN=
3000
Maximum Quiescent Supply Current (per Package) Minimum Output (Sink) Current
VIN= VOL=0.4 VOL=0.5 VOL=1.5 VIN= VOH=4.6 VOH=2.5 VOH=9.5 VOH=13.5
0.64 -0.64
0.51 -0.51
0.36 -0.36 1.15
Minimum Output High (Source) Current
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4520B
Electrical Characteristics
=50pF, =200 Symbol fmax Parameter Maximum ClockFrequency, (Figure Input Unit Guaranteed Limit -55° C125° 0.75 1120 1300
tPHL, tPLH
Maximum Propagation Delay, Clock Enable Output (Figures 1,3) Maximum Propagation Delay, Reset Output (Figure Maximum Output Transition Time,
tPHL
tTHL, tTLH Output
Maximum Input Capacitance
Timing Requirements
=50pF, =200 Symbol Parameter Minimum Pulse Width, Clock (Figure Input
Guaranteed Limit -55° C125°
Unit
Minimum Pulse Width, Reset (Figure
Minimum Pulse Width, Enable (Figure
Maximum Input Rise Fall Times (Figure
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4520B
RESET
CLOCK
1/fmax
tPLH
tPHL OUTPUT tPHL
OUTPUT
Figure Switching Waveforms
Figure Switching Waveforms
ENABLE tPLH tPHL OUTPUT
Timing Diagram
CLOCK ENABLE
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4520B
Expanded Logic Diagram (1/2 Device)
RESET
ENABLE
Address
Postalcode:100039 Tel: 86-010-58895780 Http://www.estek.com.cn Email:sales@estek.com.cn
6A06-6A07 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
010-58895793
No:01-060837
BEIJING ESTEK ELECTRONICS CO.,LTD

IW4520B Dual Binary Up-Counter consists identical, internally synchron

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