IW4049B buffers feature logic-level conversion using only supply (volt
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IW4049B
IW4049B buffers feature logic-level conversion using only supply (voltage Vcc).The input- signal high (Vih) exceed supply voltage when these devices used logic -level conversions. These devices intended CMOS DTL/TTL converters
Operating Voltage Range: over full packageMaximum input current temperature range ;100 Noise margin (over full package temperature range): supply 10.0 supply 15.0 supply
Package
Logic Diagram Assignment
CONNECTION
Function Table
Inputs Output
PINS CONNECTION
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4049B
Absolute Maximum Ratings
Symbol VOUT Tstg Parameter Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Power Dissipation Still Air, Plastic Value -0.5 -0.5 VCC+0.5 Unit
SOIC Package Power Dissipation Output Transistor Storage Temperature Lead Temperature, from Case Seconds (Plastic SOIC Package)
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: from 65°to from SOIC Package IW4049B high-to-low level voltage conversion capability low-to-high level,thefore recommended that
Recommended Operating Conditions
Symbol VOUT Parameter Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Operating Temperature, Package Types Unit
IW4049B high-to-low level voltage conversion capability low-to-high level,thefore recommended that This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, should constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either Unused outputs must left open.
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4049B
Electrical Characteristics
(Voltages Referenced GND) Symbol Parameter Minimum High-Level Input Voltage Maximum Level Input Voltage Test Conditions VOUT=0.5 VOUT=1.0 VOUT=1.5 VOUT=0.5 VOUT=1.0 VOUT=1.5 Guaranteed Limit -55° 12.5 4.95 9.95 14.95 12.5 4.95 9.95 14.95 12.5 4.95 9.95 14.95 Unit
Minimum High-Level VIN=GND Output Voltage
Maximum Low-Level Output Voltage
VIN=V
0.05 0.05 0.05
0.05 0.05 0.05
0.05 0.05 0.05
Maximum Input Leakage Current
VIN= VIN=
-2.6 1.55 0.81 0.48
-2.1 -0.65 -1.65 -4.3
Maximum Quiescent Supply Current (per Package) Minimum Output (Sink) Current
VIN= VOL=0.4 VOL=0.4 VOL=0.5 VOL=1.5
Minimum Output High (Source) Current
VIN= VOH=2.5 VOH=4.6 VOH=9.5 VOH=13.5
-1.18 -3.1
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4049B
Electrical Characteristics
Symbol tPLH Parameter Maximum Propagation Delay, Input Output (Figure =50pF, =200 Input Guaranteed Limit -55° 125° 22.5
Unit
tPHL
Maximum Propagation Delay, Input Output (Figure
tTLH
Maximum Output Transition Time, Output (Figure Maximum Output Transition Time, Output (Figure Maximum Input Capacitance
tTHL
INPUT tPHL OUTPUT
tPLH
Figure Switching Waveforms
BEIJING ESTEK ELECTRONICS CO.,LTD
IW4049B
Expanded Logic Diagram (1/6 Device)
Address
Postalcode:100039 Tel: 86-010-58895780 Http://www.estek.com.cn Email:sales@estek.com.cn
6A06-6A07 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
010-58895793
No:01-060836
BEIJING ESTEK ELECTRONICS CO.,LTD
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