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ICS9FG1201 follows Intel DB1200G Differential Buffer Specification. Th


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Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201 follows Intel DB1200G Differential Buffer Specification. This buffer provides output clocks Host Bus, Express, Fully Buffered DIMM applications. outputs configured with groups. Both groups (DIF 9:0) (DIF 11:10) equal have gear ratio input clock. differential clock from CK410 CK410B main clock generator, such ICS954101 ICS932S401, drives ICS9FG1201. ICS9FG1201 provide outputs 400MHz.
ICS9FG1201H
Features/Benefits
Power default outputs mode DIF_(9:0) "gear-shifted" from input Host Clock DIF_(11:10) "gear-shifted" from input Host Clock Spread spectrum compatible Supports output clock frequencies Selectable SMBus addresses SMBus address determines Bypass mode
Specifications
output cycle-to-cycle jitter 50ps output-to-output skew 50ps within group output-to-output skew 100ns across outputs
56-pin SSOP/TSSOP package Available RoHS compliant packaging
Funtional Block Diagram
SPREAD COMPATIBLE
GEAR SHIFT LOGIC
STOP LOGIC
DIF(11:10)
OE(9:0)#
CLK_IN CLK_IN#
SPREAD COMPATIBLE
GEAR SHIFT LOGIC
STOP LOGIC
DIF(9:0)
HIGH_BW# FS_A_410 VTT_PWRGD#/PD SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK
CONTROL LOGIC
IREF
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H
10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Configuration
HIGH_BW# CLK_IN CLK_IN# SMB_A0 OE0# DIF_0 DIF_0# OE1# DIF_1 DIF_1# DIF_2 DIF_2# OE2# DIF_3 DIF_3# OE3# DIF_4 DIF_4# OE4# DIF_5 DIF_5# OE5# SMB_A1 SMBDAT VDDA GNDA IREF OE10_11# DIF_11 DIF_11# DIF_10 DIF_10# FS_A_410 VTT_PWRGD#/PD OE9# DIF_9 DIF_9# OE8# DIF_8 DIF_8# DIF_7 DIF_7# OE7# DIF_6 DIF_6# OE6# SMB_A2_PLLBYP# SMBCLK
56-pin SSOP TSSOP
Functionality Table
DIF_(9:0) Output DIF_(11:10) Output 100.00 100.00 133.33 133.33 166.66 166.66 RESERVED 200.00 200.00 200.00 266.66 266.66 266.66 333.33 333.33 333.33 400.00 400.00 400.00 FS_A_410 low-threshold input. Please VIL_FS VIH_FS specifications Input/Supply/Common Output Parameters Table correct values. FS_A_410
CLK_IN (CPU FSB) 100.00 133.33 166.66
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Power Groups
Number 11,22,38,50 12,23,37,49 Description Main PLL, Analog clocks
Name HIGH_BW# CLK_IN CLK_IN# SMB_A0 OE0# DIF_0 DIF_0# OE1# DIF_1 DIF_1# DIF_2 DIF_2# OE2# DIF_3 DIF_3# OE3# DIF_4 DIF_4# OE4# DIF_5 DIF_5# OE5# SMB_A1 SMBDAT Type Description 3.3V input selecting Band Width High, Input reference clock. "Complementary" reference clock input. SMBus address (LSB) Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs SMBus address Data SMBUS circuitry, tolerant
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Description (continued)
Name SMBCLK SMB_A2_PLLBYP# Type Description Clock SMBUS circuitry, tolerant SMBus address When Low, part operates fanout buffer with bypassed. When High, part operates zero-delay buffer (ZDB) with operating. fanout mode (PLL bypassed), mode (PLL used) Active input enabling pair tri-state outputs, enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active input enabling pair tri-state outputs, enable outputs Vtt_PwrGd# active input used determine when latched inputs ready sampled. asynchronous active high input used device into power state. internal clocks, PLLs crystal oscillator stopped. 3.3V tolerant threshold input frequency selection. This requires CK410 FSA. Refer input electrical characteristics Vil_FS Vih_FS threshold values. 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active input enabling output pairs tri-state outputs, enable outputs This establishes reference current differential currentmode output pairs. This requires fixed precision resistor tied ground order establish appropriate current. ohms standard value. Ground core. 3.3V power core.
OE6# DIF_6# DIF_6 OE7# DIF_7# DIF_7 DIF_8# DIF_8 OE8# DIF_9# DIF_9 OE9#
VTT_PWRGD#/PD
FS_A_410 DIF_10# DIF_10 DIF_11# DIF_11 OE10_11#
IREF GNDA VDDA
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201 Programmable Gear Ratios
FS_A_410 SMBus Byte Input Output Gear Ratio (n/m) Input (CPU FSB) Output Frequencies (MHz) 200.0 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.750 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 266.7 320.0 333.3 400.0
66.7 88.9 106.7 111.1 133.3 80.0 106.7 128.0 133.3 160.0 83.3 111.1 133.3 138.9 166.7 100.0 133.3 160.0 166.7 200.0 120.0 160.0 192.0 200.0 240.0 125.0 166.7 200.0 208.3 250.0 133.3 177.8 213.3 222.2 266.7 150.0 200.0 240.0 250.0 300.0 166.7 222.2 266.7 277.8 333.3 200.0 266.7 320.0 333.3 400.0 240.0 320.0 384.0 400.0 250.0 333.3 400.0 266.7 355.6 300.0 400.0 333.3 400.0 (CPU FSB) Frequency (MHz) 133.33 166.67
0.333 0.400 53.3 64.0 66.7 0.417 55.6 66.7 69.4 0.500 50.0 66.7 80.0 83.3 0.600 60.0 80.0 96.0 100.0 0.625 62.5 83.3 100.0 104.2 0.667 66.7 88.9 106.7 111.1 0.800 80.0 106.7 128.0 133.3 0.833 111.1 133.3 138.9 1.000 100.0 133.3 160.0 166.7 1.200 120.0 160.0 192.0 200.0 1.250 125.0 166.7 200.0 208.3 1.333 133.3 177.8 213.3 222.2 1.500 150.0 200.0 1.667 166.7 222.2 266.7 277.8 2.000 200.0 266.7 320.0 333.3 Note: Lines BOLD Power-up defaults FS_A_410 respectively. Shaded areas shown reference only necessarily valid operating points
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
9FG1201 SMBus ddress apping when using CK410/CK 410B DB400/800
SMB_A(2:0) Adr: 9FG1201 (DB1200G) Adr: 954101 932S401 (CK410/410B)
BYPASS SMB_A2_PLLBYP#
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
MODE SMB_A2_PLLBYP#
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
Adr: 9DB104/108 (DB400/800)
SMB_A(2:0) Adr: 9FG1201 (DB1200G)
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
General SMBus serial interface information ICS9FG1201H Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) sends data byte count clock will acknowledge Controller (host) starts sending Byte through Byte (see Note clock will acknowledge each byte time Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) will send separate start bit. Controller (host) sends read address clock will acknowledge clock will send data byte count clock sends Byte clock sends Byte through byte X(H) written byte Controller (host) will need acknowledge each byte Controllor (host) will send acknowledge Controller (host) will send stop
Index Block Write Operation
Controller (Host) starT Slave Address D0(H)* WRite Beginning Byte Data Byte Count Beginning Byte Byte (Slave/Receiver)
Index Block Read Operation
Controller (Host) starT Slave Address D0(H)* WRite Beginning Byte Repeat starT Slave Address D1(H)* ReaD Data Byte Count Beginning Byte Byte (Slave/Receiver)
Byte stoP
Byte acknowledge stoP
Note: SMBus Address Mapping (page programming SMBus Read/Write Address
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBusTable: Gear Ratio Select Register Name Control Function Byte Group gear ratio enable DIF(9:0) DIF(11:10) Group gear ratio enable Reserved Gear Ratio (FS_A_410) Gear Ratio Gear Ratio Gear Ratio Gear Ratio SMBusTable: Output Control Register Byte Name DIF_7 DIF_6 DIF_5 19,20 DIF_4 16,17 DIF_3 13,14 DIF_2 9,10 DIF_1 DIF_0
Type Gear Ratio Gear Ratio 9FG1201 Programmable Gear Ratios Table
Latch
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable Enable Enable Enable
SMBusTable: Output Control Register Byte Name Control Function Type Reserved High note PLL_BW# adjust Bypass note BYPASS# test mode Reserved DIF_11 Output Control Hi-Z 51,52 Hi-Z 47,48 DIF_10 Output Control DIF_9 Output Control Hi-Z 42,43 39,40 DIF_8 Output Control Hi-Z Note: wired input, selects High Note: wired input, selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte Name Control Function Readback OE7# Input Readback OE6# Input Readback OE5# Input Readback OE4# Input Readback OE3# Input Readback OE2# Input Readback OE1# Input Readback OE0# Input
Enable Enable Enable Enable
Type
Readback Readback Readback Readback Readback Readback Readback Readback
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBusTable: Output Enable Readback Register Name Control Function Byte Readback FS_A_410 Readback HIGH_BW# Readback SMB_A2_PLLBYP# Reserved Reserved Readback OE10_11# Input Readback OE9# Input Readback OE8# Input SMBusTable: Vendor Revision Register Name Control Function Byte RID3 RID2 REVISION RID1 RID0 VID3 VID2 VENDOR VID1 VID0 SMBusTable: DEVICE Byte
Type
Readback Readback Readback Readback Readback Readback Readback Readback
Type
Name Control Function Device (MSB) Device Device Device Device Device Device Device
Type
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBusTable: Byte Count Register Byte Name
Type Writing this register configures many bytes will read back.
Control Function
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBusTable: Frequency Selection Byte Name Control Function RESERVED RESERVED RESERVED RESERVED RESERVED Frequency Select Frequency Select FS_A_410 SMBusTable: Reserved Register Name Byte SMBus Table: Programming Enable Byte Name M/N_EN
Type
9FG1201H Programming Table
Latch
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function Type Gear Programming Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Disable
Enable
SMBus Table: Gear Frequency Control Register Byte Name Control Function RESERVED RESERVED Gear Div5 Gear Div4 Divider Programming Gear Div3 bits Gear Div2 Gear Div1 Gear Div0
Type
9FG1201H programming Table
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBus Table: Gear Frequency Control Register Name Control Function Byte Gear Div7 Gear Div6 Gear Div5 Divider Programming Gear Div4 bits Gear Div3 Gear Div2 Gear Div1 Gear Div0 SMBusTable: Gear Output Divider Register Name Control Function Byte RESERVED RESERVED RESERVED RESERVED GoutDiv GoutDiv Gear Output Divider GoutDiv GoutDiv SMBusTable: Reserved Register Byte Name SMBusTable: Reserved Register Name Byte
Type
9FG1201H programming Table
Type
Gear Output Divider Table
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBusTable: Reserved Register Name Byte
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
SMBus Table: Frequency Control Register Name Control Function Byte RESERVED RESERVED Div5 Div4 Divider Programming Div3 bits Div2 Div1 Div0 SMBus Table: Frequency Control Register Name Control Function Byte Div7 Div6 Div5 Divider Programming Div4 bits Div3 Div2 Div1 Div0
Type
9FG1201H programming Table
Type
9FG1201H programming Table
SMBusTable: Output Divider Register Byte Name Control Function Type RESERVED RESERVED RESERVED RESERVED 1outDiv 1outDiv Output Divider 1outDiv 1outDiv
Output Divider Table
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
SMBusTable: Reserved Register Name Byte
Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
SMBusTable: Test Byte Register Test Type Test Function Byte ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST Note: write Erratic device operation will result!
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Absolute
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input protection SYMBOL VDD_A VDD_In Tambient Tcase prot CONDITIONS Human Body Model 2000 0.5V 0.5V UNITS Notes
Electrical Characteristics Input/Supply/Common Output Parameters
70°C; Supply Voltage +/-5% PARAMETER Input High Voltage Input Voltage Input High Current Input Current Threshold InputHigh Voltage Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Inductance Input Capacitance Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time SYMBOL VIH_FS VIL_FS DD3.3OP DD3.3PD Lpin COUT TSTAB CONDITIONS +/-5% +/-5% Inputs with pullup resistors +/-5%, Applies FS_A_410 +/-5%, Applies FS_A_410 outputs driven diff pairs driven differential pairs tri-stated Logic Inputs Output capacitance From Power-Up deassertion clock Triangular Modulation output enable after de-assertion fall time rise time Maximum input voltage PULLUP 0.35 (Max 0.15) (Min 0.15) (Min 0.15) (Max 0.15) 1000 UNITS Notes
VMAX PULLUP TRI2C TFI2C
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Electrical Characteristics 0.7V Current Mode Differential Pair
70°C; +/-5%; =2pF, RS=33.2, RP=49.9, PARAMETER Current Source Output Impedance Voltage High Voltage Voltage Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL
CONDITIONS Statistical measurement single ended signal using oscilloscope math function. Measurement single ended signal using absolute value.
3000 -150 -300
UNITS NOTES 1,4,5
VHigh VLow Vovs Vuds Vcross(abs d-Vcross
1150
Average period
Tperiod
Absolute period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
d-tr d-tf tJCYC-CYC
Variation crossing over edges Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread 0.175V, 0.525V 0.525V 0.175V
-300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720
2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
Jitter, Cycle cycle tJBYP Notes:
Measurement from differential wavefrom mode, from differential wavefrom Bypass mode additive jitter
1.Guaranteed design characterization, 100% tested production. Long Term Accuracy Clock Period specifications guaranteed assuming that input frequency meets CK410B accuracy requirements 3.IREF VDD/(3xRR). (1%), IREF 2.32mA. IREF 0.7V ZO=50. Measured into fixed load cap. Input output skew measured first output edge following corresponding input. Measured from differential cross-point differential cross-point Bypass Mode Input-to-Output specs refer timing between input edge specific output edge created
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Electrical Characteristics Skew Differential Jitter Parameters
70°C; Supply Voltage +/-5% Group CLK_IN, DIF[x:0] CLK_IN, DIF[x:0] DIF[11:10] DIF[9:0] DIF[11:0] Jitter Peaking Jitter Peaking Bandwidth Bandwidth Jitter, Phase NOTES:
Measured into fixed load cap. Input output skew measured first output edge following corresponding input. Measured from differential cross-point differential cross-point Bypass Mode Input-to-Output specs refer timing between input edge specific output edge created This parameter deterministic given device Measured with scope averaging find mean value. period input clock http://www.pcisig.com complete specs Device driven 932S401EGLF equivalent Measured maximum pass band gain. frequencies ithin loop highest point magnification called jitter peaking. Guaranteed design characterization, 100% tested production. Measured half point.
Parameter SPO_PLL PD_BYP SKEW_G2 SKEW_G10 SKEW_A12 jpeak-hibw jpeak-lobw pllHIBW pllLOBW jphasePLL
Description Input-to-Output Skew mode (1:1 only), nominal value 25°C, 3.3V Input-to-Output Skew Bypass mode (1:1 only), nominal value 25°C, 3.3V Output-to-Output Skew Group (Common Bypass mode) Output-to-Output Skew Group (Common Bypass mode) Output-to-Output Skew across outputs (Common Bypass mode outputs same gear) (HIGH_BW# (HIGH_BW# (HIGH_BW# (HIGH_BW# PCIe phase jitter (1.5 MHz) phase jitter (11-33 MHz)
-500
Units
Notes 1,2,4,5,6, 1,2,3,5, 1,2,10 1,2,10 1,2,3,10 9,10 9,10 10,11 10,11 1,7,8,10
1,7,8,10
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Reference Clock Common Recommendations Differential Routing Dimension Value length, Route non-coupled trace. length, Route non-coupled trace. length, Route non-coupled trace. 49.9 Down Device Differential Routing length, Route coupled microstrip differential trace. length, Route coupled stripline differential trace. Differential Routing Express Connector length, Route coupled microstrip differential trace. length, Route coupled stripline differential trace. Dimension Value 14.4 Dimension Value 0.25 0.225 12.6
Unit inch inch inch Unit inch inch Unit inch inch
Figure Figure Figure
Figure Down device routing.
HSCL Output Buffer
Board Down Device REF_CLK Input
Figure
Figure Express Connector Routing.
Board REF_CLK Input
HSCL Output Buffer
Figure
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Alternative termination LVDS other common differential signals. Figure
Vdiff Vp-p 0.45 0.22v 0.58 0.28 0.80 0.40 0.60 Figure_3. 1.08 78.7 78.7 none Note
ICS874003i-02 input compatible Standard LVDS
HSCL Output Buffer
Down Device REF_CLK Input
Cable connected coupled application, figure
Component R5a,R5b R6a,R6b Value 8.2K 0.350 volts Note
Volts
PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
56-Lead, Body, mil, SSOP
SYMBOL
INDEX AREA
VARIATIONS
Millimeters COMMON DIMENSIONS 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 VARIATIONS
Inches COMMON DIMENSIONS .095 .110 .008 .016 .008 .0135 .005 .010 VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 VARIATIONS
SEATING PLANE (.004)
18.31 18.55 .720
(inch) .730
Reference Doc.: JEDEC Publication MO-118
10-0034
Ordering Information
9FG1201HFLF-T
Example:
XXXX
Designation tape reel packaging RoHS Compliant Package Type SSOP Revision Designator Device Type (consists digit numbers)
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
INDEX AREA
56-Lead 6.10 Body, 0.50 Pitch TSSOP (240 mil) mil) Millimeters Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 VARIATIONS VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 VARIATIONS VARIATIONS -0.10 -.004 VARIATIONS
10-0039
SEATING PLANE
13.90 14.10
(inch) .547 .555
erence Doc.: JEDEC Publicat O-153
Ordering Information
9FG1201HGLF-T
Example:
XXXX
Designation tape reel packaging RoHS Compliant Package Type TSSOP Revision Designator (will correlate with datasheet revision) Device Type
IDTTM/ICSFrequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
ICS9FG1201H 10/22/07
ICS9FG1201H Frequency Generator CPU, PCIe Gen1* Fully Buffered DIMM Clocks
Revision History
Rev. Issue Date 10/22/07 Description Release Final. Page
Innovate with accelerate your future networks. Contact:
www.IDT.com
Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
Tech Support
408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road Jose, 95138 United States 7015 +408 8200 (outside U.S.)
Asia Pacific Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. 199707558G Orchard Road #20-03 Wisma Atria Singapore 238877 5505
Europe
Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 1372
2006 Integrated Device Technology, Inc. rights reserved. Product specifications subject change without notice. logo trademarks Integrated Device Technology, Inc. Accelerated Thinking service mark Integrated Device Technology, Inc. other brands, product names marks trademarks registered trademarks used identify products services their respective owners. Printed

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