Power management multimedia processors Step-down converters 1.5V

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Power management multimedia processors Step-down converters 1.5V

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STw4810
Power management multimedia processors
Step-down converters 1.5V with steps 600mA 1.8V 600mA general purpose usage Low-drop output regulators different uses analog supplies: 1.05V, 1.2V, 1.3V 1.8V 10mA Processor analogue functions: 2.5V 10mA Auxiliary device: 1.5V, 1.8V, 2.5V, 2.8V module Full speed transceiver Charge-pump (5V, 100mA) cable Mass memory cards (SD/MMC/SDIO) linear regulator: 1.8V, 2.85V, 150mA Level shifter Miscellaneous control multimedia processor Processor supply monitoring Processor reset control Serial interfaces
STw4810CHD TFBGA 6x6x1.2mm 0.5mm pitch STw4810CRA VFBGA 4.6x4.6x1.0mm 0.4mm pitch
Description
STw4810 power management companion chip multimedia processors used portable applications. supplies multimedia processor including memories peripherals. STw4810 supports main mass memory standard cards. SDIOis also supported allows connect multimedia peripherals like cameras.
Application
NOMADIKSTn88xx Multimedia processor Mobile phones, PDA, videophone
September 2007
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Contents
STw4810
Contents
Overview Functional block diagram Ball information
Ball connections Ball functions
Functional description
Introduction Digital control module
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 State machine POWER VDDOK Sleep mode Interface Control registers generation Clock switching control
Power management module
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 Bandgap, biasing references VCORE regulator: DC/DC step-down regulator VIO_VMEM regulator: DC/DC step- down regulator VPLL VANA VAUX Power supply monitoring Power supply domains Thermal shut-down
module
4.4.1 4.4.2 4.4.3 Block diagram Modes operations enable control
SD/MMC/SDIO module
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STw4810
Contents
Electrical timing characteristics
Absolute maximum rating Package dissipation Power supply
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Operating conditions VREF18 VCORE DC/DC step-down converter VIO_VMEM DC/DC step-down converter regulators Power supply monitoring
Digital specifications
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 CMOS input/output static characteristics: interface CMOS input/output dynamic characteristics: interface CMOS input/output static characteristics: level CMOS input/output static characteristics: VBAT level CMOS input/output static characteristics: VMMC level
transceiver SD/MMC card interface
Application information
Components list Application schematics
Package mechanical data
TFBGA balls VFBGA balls
Ordering information Revision history
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List tables
STw4810
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table STw4810 ball connections STw4810 balls function. Device Register address. Register data Register general information. Register summary. Power control register register address Vendor Product Read only control register (address clearh) control register (Address clearh) Interrupt source register (address 08h) interrupt latch registers (address clearh) interrupt mask false register (address 0Dh) interrupt mask true register (address 0Fh) register (address 10h) control register (11h) Power control register General information (Address 1Eh) Power control register General information (Address 1Fh) Power control register mapping Power control register address Power control register address Power control register address Power control register address Power control register address Power control register address Twarning register (Address 20h) Power supply domains Thermal threshold values Data transmission control register (DAT_SE0 mode) Suspend Data transmission control register (DAT_SE0 mode) Suspend Data receiver control register STw4810 absolute maximum ratings Package dissipation Operating conditions (Temp range: °C). VREF18 VCORE DC/DC step-down converter VIO_VMEM DC/DC step-down converter regulators VPLL regulators VANA regulators VAUX Power supply monitoring CMOS input/output static characteristics: interface CMOS input/output dynamic characteristics: interface level: control I/Os level: interface CMOS input/output static characteristics: VBAT level
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STw4810 Table Table Table Table Table Table Table Table Table
List tables CMOS input/output static characteristics VMMC level transceiver SD/MMC card interface Components list Recommended coils TFBGA balls 6x6x1.2mm body size ball pitch dimensions VFBGA balls 4.6x4.6x1.0 body size ball pitch Order codes Document revision history
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List figures
STw4810
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical mobile multimedia system STw4810 block diagram Start-up timing Switching POWER sleep timing VDDOK block diagram interface block diagram Control interface: format. Control interface: timing Clock switching between master internal clock Block diagram biasing references device Thermal threshold temperatures `it_warn' VDDOK ball transceiver block diagram block diagram Propagation clock/data skew times STw4810 application schematics TFBGA balls 6x6x1.2mm body size ball pitch drawing VFBGA balls 4.6x4.6x1.0 ball pitch drawing
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STw4810
Overview
Overview
STw4810 power management device following features:
Power management module Step-down converter processor core with steps Step-down converter (1.8 general purpose usage such processor input/output supply, external memory, SDRAM peripherals Low-drop output regulator analog supplies, such (1.05 Low-drop output regulator processor analogue functions (2.5 Low-drop output regulator auxiliary devices (1.5 Full speed transceiver Linear regulators (3.1 supplying transceiver Charge-pump supplying VBUS line cable Linear regulator (1.8 2.85 Level shifter control multimedia processor Processor supply monitoring Processor reset control Serial interfaces Typical mobile multimedia system
module
Mass memory cards (SD/MMC/SDIO)
Miscellaneous
Figure
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Functional block diagram
STw4810
Figure
Functional block diagram
STw4810 block diagram
VMINUS_VIO_VMEM VBAT_VIO_VMEM VMINUS_VCORE 1V=>1.5V- 600mA VLX_VIO_VMEM
VBAT_VCORE
VLX_VCORE
VIO_VMEM
VBAT_DIG VMINUS_DIG Internal oscillator 1.8V- 600mA
MASTER_CLK CLK32K_IN CLK32K GPO1 GPO2 USBINTn
clock switching control SOFT_START VREF_VIO_VMEM
VREF_VCORE VREF_VPLL VREF_VAUX
VCORE
VBAT_ANA VMINUS_ANA
BIAS
Buffer
VREF_18
Control registers Thermal shutdown Monitoring VPLL_LDO 1.05V,1.2V,1.3V,1.8V, 10mA VANA_LDO 2.5V, 10mA PORn_VBAT
VBAT_VPLL_ANA
TCXO_EN REQUEST_MC VDDOK PORn PWREN SW_RESETn
VPLL
General control
VANA VBAT_VAUX VAUX_LDO 1.5V,1.8V2.5V,2.8V, 150mA
interface
VAUX VBAT_USB
transceiver interface USBSDA USBSCL IT_WAKE_UP SD/MMC/ SDIO control USBOEn USBVP USBVM USBRCV VMINUS_USB MCCMDDIR MCDAT0DIR MCDAT2DIR MCDAT31DIR MCCLK MCFBCLK MCCMD MCDATA0 MCDATA[3:1] Driver Level shifter Pull down VUSB VBAT_MMC MMC/SDIO interface control Charge pump 100mA VBUS
Control
3.1V 40mA
Level shifter
1.8/2.85/3V-150mA
VMMC LATCHCLK CLKOUT CMDOUT DATAOUT0 DATAOUT[3:1]
Driver
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STw4810
Ball information
Table
Ball information
Ball connections
STw4810 ball connections
VMINUS_ VIO_VMEM
VLX_VIO_ VMEM
VAUX
VANA
VPLL
VREF_18
VCORE
CLK32K_IN
VBAT_VIO_ VIO_VMEM VMEM VMINUS_ "Reserved"
"Reserved" TCXO_EN VBAT_DIG DATAOUT0 DATAOUT CLKOUT MCCMD MCDATA MCDATA0
REQUEST_ VMINUS_ VBAT_VIO_ VIO_VMEM VMEM IT_WAKE_ MASTER_ DATAOUT CMDOUT MCCLK MCDATA VDDOK MCDAT0 VMINUS_ "reserved" DATAOUT LATCHCLK MCCMD MCDATA PORN CLK32K MCDATA31 VBAT_ RESET VLX_VIO_ VMEM
VBAT_ VAUX VBAT_ANA
"Reserved" VBAT_ VPLL_ANA
"Reserved" VLX_ VCORE "Reserved" "Reserved"
"Reserved" VMINUS_ VCORE VBAT_ VCORE VBAT_USB USBSCL USBSDA VMINUS_ MCDAT2
VMINUS_ VCORE VLX_ VCORE VBAT_ VCORE VUSB VBUS "Reserved"
MCFBCLK GPO1 VMMC
PWREN GPO2
USBVP USBRCV
USBINTn USBVM USBOEn
Ball functions
STw4810 includes following ball types
VDDD/VDDA: digital/analog power supply VSSD/VSSA: digital/analog ground supply DO/DI/DIO: Digital Output Digital Input Digital Input Output DOz: Digital Output with high impedance capability AO/AI/AIO: Analog Output Analog Input Analog Input-Output connected ground left open Int-Ref: Associated internal reference
Table details ballout.
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Ball information Table
Ball General supplies VBAT_DIG VMINUS_DIG VBAT_ANA VMINUS_ANA VBAT_USB VMINUS_USB VREF_18 VDDD-VBAT VSSD VDDA-VBAT VSSA VDDA-VBAT VSSA Int-Ref Battery supply digital/oscillator Ground digital oscillator Battery supply analog Ground analog Battery supply block Ground block Internal reference
STw4810
STw4810 balls function
Ball name Ball type Description
Control balls SW_RESETn VDDOK PORn PWREN TCXO_EN REQUEST_MC MASTER_CLK CLK32K_IN CLK32K DI(VBAT) Pull Down 1.5M DI(VIO_VMEM) Pull 1.5M DO(VIO_VMEM) DO(VIO_VMEM) DI(VIO_VMEM) Pull 1.5M DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DI(VIO_VMEM) DIO(VIO_VMEM) Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) Power-on reset Software reset, reset applications when SW_RESETn Supply monitoring multimedia processors. Interruption high temperature warning Multimedia processor Resetn Sleep mode from multimedia processor Request master clock from modem part Request master clock oscillator Clock Main interface Main interface MHz, 19.2 from modem input multimedia processor
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STw4810 Table
Ball Regulator balls balls IT_WAKE_UP USBOEn DO(VBAT-DIG) DIO(VIO_VMEM) Pull Down 1.5M DIO(VIO_VMEM) Pull Down 1.5M DIO(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) AIO(VUSB) AIO(VUSB) AI(VBAT-USB) AIO(VBUS) VBAT_VIO_VMEM VMINUS_VIO_VMEM VLX_VIO_VMEM VIO_VMEM VBAT_VCORE VMINUS_VCORE VLX_VCORE VCORE VBAT_VPLL_ANA VANA VPLL VAUX VBAT_VAUX VDDA-VBAT VSSA VDDA-VBAT VSSA VDDA-VBAT VDDA-VBAT
Ball information STw4810 balls function (continued)
Ball name Ball type Description
Battery power supply step down VIO_VMEM Ground step down VIO_VMEM BUCK step down VIO_VMEM VIO_VMEM Feed back input Battery power supply step down VCORE Ground step down VCORE BUCK step-down VCORE VCORE sense Battery supply VPLL, VANA VANA output VPLL output VAUX output Battery supply VAUX
Interrupt modem wake-up plug Output enable differential driver mode Data input transmit mode, positive data input single-ended transmit mode, UART mode Single-ended zero input transmit mode, negative data input single-ended transmit mode, UART mode Differential receiver output Positive data line mode, serial data input UART mode Negative data line mode, serial data output UART mode. ball detector used protocol identification. plus flying capacitor (VBUS level 5.25)
USBVP
USBVM USBRCV
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Ball information Table
Ball VBUS VUSB USBSCL USBSDA USBINTn
STw4810
STw4810 balls function (continued)
Ball name Ball type AIO(VBUS) AIO(VBUS) DI(VIO_VMEM) DIO(VIO_VMEM) DO(VIO_VMEM) Description minus flying capacitor (VBUS Level) cable supply (VBUS Level) Decoupling capacitor internal regulator Clock dedicated dedicated Interrupt multimedia processor accessory plug
balls MCCMDDIR DI(VIO_VMEM) Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M DI(VIO_VMEM) Pull Down 1.5M direction. "high": signal from processor card "Low": signal from card processor DATA0 direction "high": DATA0 signal from processor card "Low": DATA0 signal from card processor DATA2 direction "high": DATA2 signal from processor card "Low": DATA2 signal from card processor DATA(3,1) direction "high": DATA(3,1) signal from processor card "Low": DATA(3,1) signal from card processor Host clock, between processor STw4810, card (processor clock). Host feedback clock between STw4810 processor, re-synchronize data processor. Bidirectional command/response signal between processor STw4810. Bidirectional data0 between processor STw4810 Bidirectional data [3:1] between processor STw4810. Host feedback clock STw4810, resynchronize data processor. Host clock, between STw4810 card (processor clock). Bidirectional command/response signal between STw4810 processor. Bidirectional data0 between STw4810 card
MCDAT0DIR
MCDAT2DIR
MCDAT31DIR
DI(VIO_VMEM) Pull Down 1.5M
MCCLK MCFBCLK MCCMD MCDATA0
DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DIO(VIO_VMEM) Pull 1.5M DIO(VIO_VMEM) Pull Up1.5M DIO(VIO_VMEM) Pull 1.5M DI(VMMC) Pull Down 1.5M DO(VMMC) DIO(VMMC) Pull 1.5M DIO(VMMC) Pull 1.5M
MCDATA[3:1]
LATCHCLK CLKOUT CMDOUT DATAOUT0
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STw4810 Table
Ball Other balls GPO1 GPO2 "Reserved" General purpose output General purpose output connected ground
Ball information STw4810 balls function (continued)
Ball name DATAOUT[3:1] VBAT_MMC VMMC Ball type DIO(VMMC) Pull 1.5M VDDA-VBAT Description Bidirectional data[3:1] between STw4810 card. Battery supply VMMC VMMC supply output
"Reserved"
left open
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Functional description
STw4810
Functional description
Introduction
STw4810 integrates power supplies multimedia processor well memories peripherals:
switched mode power supply regulators: multimedia processor core, multimedia processor I/Os memories Three low-drop output regulators multimedia processor analog supplies (PLL others) auxiliary components FS/LS physical interface card power supplies level shifters Multimedia processor supply monitoring power-on reset power supply alarms interrupt management serial communication interfaces; control devices (SDA, SCL) control (USBSDA, USBSCL).
Digital control module
This module describes interfaces used program device related registers.
4.2.1
State machine
Description each states: (Figure Off: this mode STw4810 switched off. when PON=0, when battery level under when thermal shutdown activated. There multimedia processor power supply. only active cell cable detection VBAT level detection. OSC_START: Oscillator enabled power module waiting rising edge internal signal OSC_OK start power sequence. This state duration START_BIAS: Bias, reference thermal shut-down enabled, counter activated wait rising edge internal signals PDN_regulators. This state duration typical value 7.77 worst case value 9.46 START_PM: after wait, multimedia processor power supplies available (VIO_VMEM, VCORE, VPLL, VANA). device allow communication, output power supply monitoring application (USB,SD/MMC). OFF2: STw4810 waiting multimedia processor signal. This state indeterminate duration. 32kHz present during states describes above, effect. signal taken into account STw4810 only when `VDDOK' ball high, that START_PM state. Reset: STw4810 forces reset during 10*32 period before setting PORn high. INT_OSC: STw4810 work without MASTER_CLK internal oscillator. device waits external clock detection before switching external clock. When receiving rising edge PWREN ball (coming from multimedia processor) TCXO_EN ball (coming from modem), STw4810 answers asserting
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STw4810
Functional description REQUEST_MC ball. STw4810 remains internal oscillator mode until receives external clock signal MASTER_CLK ball. EXT_CLK: When MASTER_CLK detected, STw4810 uses this clock reference switches internal oscillator save quiescent. MASTERCLK should remain connected sleep mode. Sleep: Sleep mode required multimedia processor setting PWREN level. Then VDDOK forced regulators (VCORE, VIO_VMEM) switch sleep mode wait PWREN high level (Figure Wake-up: From sleep mode, multimedia processor requests switch back Normal mode. Thus device restarts internal oscillator then switches regulators from sleep normal mode informs multimedia processor with VDDOK high level (Figure
Note:
default VAUX stand mode, pdn_vaux (Table 18). programmed normal mode only asserted pdn_vaux "1".
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Functional description Figure Start-up timing
VBAT ball
300µs
9.38ms (11ms
STw4810
PDN_OSC
START_BIAS
START_PM
PDN_regulators VDDOK ball
7.77ms (9.46ms
11*(1/32kHz)
CLK32K_IN ball PORn ball PWREN ball
Reset PWREN unmasked
Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball
OFF2 VPLL VIO_VMEM VCORE
"or"
Reset
INT_OSC
Voutput(s) ball
CLK32K ball Delays worst case maximum delays available before VDDOK signal rising edge, OFF2 state duration null
regulators started with PDN_regulators switched from beginning during application software (Table
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STw4810 Figure Switching POWER sleep timing
PWREN Sleep regulators VDDOK PDN_regulators CLK32K PDN_intOSC int_OSC_detect REQUEST_MC Internal_OSC MASTER_CLK SLEEP ~100µs
Functional description
Registers reset
event hardware reset coming from modem, ball "0", registers reset initial value when ball goes back level. software reset from multimedia processor STw4810, through SW_RESETn ball "0", reset registers except power control register address 1F).
Main clock oscillator control
REQUEST_MC output gate between PWREN (coming from multimedia processor) TCXO_EN (coming from modem supply), synchronized kHz, except during power-up where PWREN masked considered high. REQUEST_MC enabled disabled master clock oscillator device.
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Functional description
STw4810
4.2.2
POWER VDDOK
case VDDOK falling edge under voltage VCORE VIO_VMEM detected, `it_twarn' (Table 18), then multimedia processor reset (PORn during minimum time 312.5 restarted with time-out. (see Figure case VDDOK falling edge because PWREN balls equals "0", there reset (PORn still high). case falling edge (STw4810 switched from modem) multimedia processor also reset with time-out. consider that clean switch between modem multimedia processor done software directly. VDDOK block diagram
Digital block VDDOK
Figure
PWREN
vcore_monitor vio_monitor
it_twarn mask_twarn register reset after read operation falling edge PORN_VBAT.
status
Under voltage detection VDDOK Operating voltage threshold value reached
PORn 312.5 (10* Khz)
4.2.3
Sleep mode
STw4810 goes into sleep mode different ways. Whether VCORE, VIO_VMEM VAUX programmed sleep mode indicated Table
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STw4810
Functional description
4.2.4
Interface
device supports interfaces. main interface (SDA,SCL) controls power management programmable functions, second interface (USBSDA, USBSCL) dedicated control. STw4810 allows work with only main interface control functions, including USB, USB_I2C_CTRL power control register (Table 27). Interface used read status information from inside device. Flags, interrupt write registers used configure device functions (threshold, clock division, output voltage, etc.). default, main interface (SCL,SDA) controls main registers interface (USBSCL, USBSDA) controls registers. Figure interface block diagram
usb_i2c_ctrl USBSCL USBSDA
Main registers
USBSCL USBSDA registers
Both configured slave serial interface compatible with registered trademark Phillips Inc. (version 2.1).
interface description
STw4810 slave serial interface with serial data line (SDA USBSDA) serial clock line (SCL USBSCL): USBSCL: input clock used shift data USBSDA: input/output bidirectional data transfers filter reject spikes data line preserve data integrity Bidirectional data transfers 400kbit/s (Fast-mode) USBSDA signal
composed
USBSDA signal contains input/output control data signals that shifted device, first. first must high (START) followed Device bits) Read/Write control indicates read access, logical indicates write access). Device write mode: (01011010) Device read mode: (01011011)
Then STw4810 sends acknowledge bits transfer. next bits correspond register address followed another acknowledge. bits data field sent last, followed last acknowledge.
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Functional description Table
AdrID6
STw4810
Device
AdrID5 AdrID4 AdrID3 AdrID2 AdrID1 AdrID0
Table
RegADR7
Register address
RegADR6 RegADR5 RegADR4 RegADR3 RegADR2 RegADR1 RegADR0
Table
DATA7
Register data
DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
interface modes
Figure Control interface: format
DEVICE ADDRESS REGn ADDRESS REGn Data
WRITE SINGLE BYTE
01011010
START STOP
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS
REGn ADDRESS
DEVICE ADDRESS
REGn Data
01011010
START
01011011
START
RANDOM ADDR READ MULTI BYTE DEVICE ADDRESS REGn ADDRESS DEVICE ADDRESS Data
01011010
START
01011011
START
Data STOP
data bytes
Figure
Control interface: timing
USBSDA USBSCL
Stop
tbuf thd_sta tlow thigh thd_dat tsu_dat
tsu_sta tsu_sto thd_sta
Start
Start repeated
Stop
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STw4810
Functional description
4.2.5
Control registers
Control registers have following functions: Select level regulation multimedia processor supply Control interface Control SD/MMC/SDIO interface Control state machine
Table
Register general information
Comment Registers (Table Table Control register (Table Test registers Power control registers (Table Table twarning register (Table control USBSDA USBSCL
Address
Controlled USB_I2C_CTRL Power control register (Table
Table
Register summary
Addr. used vbus_ chrg cr_int cr_int cr_int cr_int used monitori ng_vio_ vmem_ vcore uart_en vbus_ dischrg bdis_ acon bdis_ acon bdis_ acon bdis_ acon oe_int_ vbus_ id_float id_float id_float id_float
Register Vendor
Product control register control register interrupt source interrupt latch interrupt mask false interrupt mask true
bdis_ used dat_se0 acon_en id_gnd dn_hi dn_hi dn_hi dn_hi
suspend speed pullup
pulldown pulldown pullup id_gnd_ forced id_gnd_ forced id_gnd_ forced id_gnd_ forced dp_hi dp_hi dp_hi dp_hi
sess_vld vbus_vld sess_vld vbus_vld sess_vld vbus_vld sess_vld vbus_vld usb_en used pdn_ vmmc mask_ twarn
control
pdn_ vaux
it_warn
gpo2
gpo1
sel_vmmc<1:0>
Twarning
used
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Functional description Table Power control register
Addr. Addr. address bits
STw4810
Register Power control Register Power control
used
address bits write
data din/dout bits
Registers controlled
registers described this chapter controlled through serial interface, USBSCL USBSDA balls. These registers could also controlled through main interface, balls setting USB-I2C_CTRL Power control register (Table 23). Table register address
Register Vendor Product Control Register Control Register Control Register Control Register Interrupt Source used Interrupt Latch Interrupt Latch Interrupt Mask False Interrupt Mask False Interrupt Mask True Interrupt Mask True USB_EN Type
Address clearh clearh clearh clearh clearh
Note:
register writing address 04h, reset writing address 05h. This also applicable Control Register (06h, 07h), Interrupt register (0Ah,0Bh), Interrupt Mask False register (0Ch, 0Dh) Interrupt Mask True register (0Eh, 0Fh). Writing address effect content register.
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STw4810 Table Vendor Product Read only
Name Vendor Vendor Product Address
Functional description
Register Value
control register
Table
Register name Type
control register (address clearh)
used uart_en speed
oe_int_ bdis_ used dat_se0 suspend acon_en
Bits
Name uart_en oe_int_en
Value
Settings Inactive UART logic buffers enabled Inactive Allow send interruption through USBOEn Inactive (default) Enable A-device connect B-device disconnect detected: VP_VM mode DAT_SE0 mode Inactive (default) transceiver power mode rise fall times transmit speed Full speed
Default
bdis_acon_en
dat_se0
suspend
speed
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Functional description
STw4810
control register
Table
Register name Type
control register (Address clearh)
vbus_ chrg vbus_ dischrg vbus_ id_gnd pulldown pulldow pullup pullup
Bits
Name vbus_chrg
Value
Settings Inactive Charge VBUS through resistor Inactive Discharge VBUS through resistor ground. Inactive Provide power VBUS Inactive Connect ball ground Inactive Connect pull-down Inactive Connect pull-down Inactive Connect pull-up Inactive Connect pull-up
Default
vbus_dischrg
vbus_drv
id_gnd
dn_pulldown
dp_pulldown
dn_pullup
dp_pullup
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STw4810
Functional description
interrupt source register
Table
Register name Type
Interrupt source register (address 08h)
cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vbus_
Bits cr_int
Name
Value
Settings Inactive ball above carkit interrupt threshold Inactive when bdis_acon_en set, transceiver asserts dp_pullup after detecting B-device disconnect. Inactive ball floating Inactive ball high Inactive ball grounded Inactive asserted during SRP, Session valid comparator threshold <0.8V >4.4V 0.8V Session valid comparator threshold 4.4V A-device VBUS valid comparator threshold <4.4V A-device VBUS valid comparator threshold >4.4V
Default
bdis_acon
id_float
dn_hi
id_gnd_forced
dp_hi
sess_vld
vbus_vld
latch register
Table
Register name Default Type
interrupt latch registers (address clearh)
cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vbus_
interrupt latch register bits indicate which sources have generate interrupt.
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Functional description
STw4810
interrupt mask false register
Table
Register name Default Type
interrupt mask false register (address 0Dh)
cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl vbus_vl
interrupt mask false register bits enable transition from true false.
interrupt mask true register
Table
Register name Type
interrupt mask true register (address 0Fh)
cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl vbus_vl
interrupt mask true register bits enable interrupts transition from false true.
register
Table
Register name Type
register (address 10h)
used
usb_en used
Bits
Name usb_en
Value Inactive Enable
Settings
Default
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STw4810
Functional description
Registers controlled main
controlled registers controlled through main serial interface, balls.
control register
Table
Register
control register (11h)
pdn_ vaux pdn_ vmmc
name
monitori ng_vio_ it_warn vmem_ vcore R(1) R(1)
gpo2
gpo1
sel_vmmc<1:0>
Type
These bits reset after reading
Bits
Name pdn_vaux
Value Inactive Enable vaux
Settings
Default
it_warn monitoring_vio_ vmem_vcore gpo2
Below temperature threshold Above temperature threshold Outputs good range Outputs lower than expected vio_vmem vcore Output GPO2 Output GPO2 Output GPO1 Output GPO1 1.8V selection 1.8V selection 2.85V selection selection Inactive Enable SD/MMC SDIO function.
gpo1
[2:1] sel_vmmc<1:0>
pdn_vmmc
Flash registers allow program STw4810 energy management part. These registers address must programmed with register first followed register.
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Functional description
STw4810
Power control register address
Table
Register name Type
Power control register General information (Address 1Eh)
address bits LSB's
data din/dout bits
Bits [7:5] [4:1]
Name address bits data din/ dout bits
Value
Settings Table "Address" column (LSB's). Table control register
Default
Read enabled Write enabled
Power control register address
Table
Register name Type
Power control register General information (Address 1Fh)
used
address bits MSB's
Bits [9:8]
Name address bits MSB's
Value
Settings Table "Address" column (MSB's).
Default
Power control register mapping
Table Power control register mapping
Address address used bits MSB's bits LSB's data din/dout bits Comments Test purpose Setting Table Table Test purpose Address
Caution:
Only latest value written register address 1E/1F read.
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STw4810
Functional description
Power control register address
Table Power control register address
Address Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1.00V 1.05V 1.10V 1.15V 1.20V (default) 1.22V 1.24V 1.26V 1.28V 1.30V 1.32V 1.34V 1.36V 1.38V 1.40V 1.50V Address Default
used Bits Name
vcore_sel [3:0] Settings
[4:1]
vcore_sel [3:0]
0100
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Functional description
STw4810
Power control register address
Table Power control register address
Address vpll_sel Settings 1.05V 1.2V 1.3V 1.8V 1.5V 1.8V 2.5V 2.8V interface controls registers Main interface controls registers Address usb_ i2c_ctrl
used
vaux_sel <1:0>
Bits
Name vpll_sel[1:0] address
Value
Default
[3:2] vaux_sel[1:0]
usb_i2c_ctrl
Power control register address
Table Power control register address
Address en_vpll Address used vcore vpll_sel
used
Bits
Name en_vpll
Value
Settings Disabled VPLL Enabled VPLL ON(1) Disabled VCORE Enabled VCORE ON(1) Table
Default
en_vcore vpll_sel[1]
soft start feature supply enabled after disabled/enabled sequence
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STw4810
Functional description
Power control register address
Table Power control register address
Address Address vana used
used
en_clk en_mo square nitorin Settings
Bits
Name en_clock_squarer
Value
Default
Disabled Enabled (sine wave signal input) Disabled MONITORING Enabled VCORE VIO_VMEM monitoring Disabled VANA Enabled VANA
en_monitoring
en_vana
Power control register address
Table Power control register address
Address vaux_ sleep Address used used used
used
Bits
Name
Value
Settings When PWREN low: VAUX stays normal mode VAUX goes sleep mode (default) Reserved Reserved
Default
vaux_sleep
used used
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Functional description
STw4810
Power control register address
Table Power control register address
Address vaux_ force_ sleep Address used
used
vio_ vcore_ vmem_ force_ force_ sleep sleep
Bits
Name vaux_force_sleep
Value
Settings VAUX normal mode VAUX goes sleep mode (for PWREN level) VIO_VMEM normal mode VIO_VMEM goes sleep mode (for PWREN level) VCORE stays normal mode VCORE goes sleep mode (for PWREN level)
Default
vio_vmem_force_ sleep
vcore_force_sleep
Twarning register
Table
Register name Type
Twarning register (Address 20h)
used mask_ twarn
Bits
Name
Value
Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK
Default
mask_twarn
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STw4810
Functional description
4.2.6
generation
STw4810 three interrupt balls: IT_WAKE_UP: with only VBAT supply, other supply available, when cable plugged this interrupt activated wake host modem, depends application (active low). USBINTn: This interrupt ball dedicated protocol sent multimedia processor VDDOK: This ball functions: When high, indicates that VIO_VMEM VCORE output voltages within right range that device internal temperature below maximum allowed temperature. When low, indicates that output regulators (VCORE VIO_VMEM) regulated properly PWREN "0", that temperature above allowed threshold (see Thermal shut-down section). interruption source application register (address 11h) needs checked.
4.2.7
Clock switching control
This block generates clock used DC/DC converter (USB charge pump, step-down VIO_VMEM step-down VCORE). STw4810 able sustain master clock frequencies MHz, 19.2MHz MHz. also sustain dedicated MASTER_CLK signal frequency range 750KHz 1MHz. clock detected internal oscillator automatically selected.
Note:
Figure
When present Master clock should remain connected sleep mode.
Clock switching between master internal clock
internal clock transition external clock
Phase delay less than between clock
INT_OSC INT_OSC_OK MASTER_CLK_OK Third rising edge after switching PDN_INT_OSC CONTROL_SWITCH
MASTER_DIV_CLK STEP_DOWN_CLK
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Functional description
STw4810
Power management module
STw4810 includes several regulators that supply multimedia processor peripherals. regulators work different modes depending processor needs. When STw4810 `low current mode'", output current reduced save energy lower quiescent current. nominal mode called high power mode (HPM). mode selected PWREN signal according both multimedia processor STw4810 state. When PWREN "0", sleep mode selected. selected default when PWREN "1". Each regulator dedicated battery power supply. powered down signal called PDN_regulator_name shown Figure STw4810 block diagram. this mode, regulator switched only leakage current present (max. 1µA). VCORE, VAUX VPLL output voltages programmable, through main interface, using "Regulator"_SEL[x:0] bits power control registers (Table Table 27). addition, output current limitation prevents high current delivery case output short circuit. multimedia processor power supplies have same soft start prevent leakage multimedia processor device during start-up phase. There exception with VAUX which started independently.
4.3.1
Bandgap, biasing references
Figure Block diagram biasing references device
Voltage reference control internal references internal biasing Bias generator VREF_18
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STw4810
Functional description
4.3.2
VCORE regulator: DC/DC step-down regulator
This regulator drives core multimedia processor. VCORE DC/DC step-down regulator that generates regulated power supply with very high efficiency. voltage levels enable dynamic voltage frequency scaling suitable supply voltage CMOS process, they also follow processor process roadmap. regulated output voltage levels adjustable power control registers (Table 22), main interface (SDA, SCL). master clock (13, 19.2 MHz) automatically detected, squared divided generate switching clock SMPS. When this clock available, regulators internal oscillator. DC/DC step-down regulator following main features;
Programmable output voltage, levels from (VCORE_SEL [3:0] bits power control register Table power domains: `Normal mode' when multimedia processor mode, full load `Low current mode' when multimedia processor sleep mode, current capability. Fast switching from current normal mode. regulator `low current mode' when multimedia processor sleep mode. PWREN signal indicates that multimedia processor about switch mode. VDDOK signal indicates multimedia processor that supplies specified range.
Note:
definition sleep mode given section 4.2.3: Sleep mode. `Power down mode' `standby mode' when regulator switched off, consumption (EN_VCORE power control register Table Soft start circuitry start from power normal mode, when ball changes from "1". Default setting defined start-up configuration.
4.3.3
VIO_VMEM regulator: DC/DC step- down regulator
VIO_VMEM step-down regulator same structure than VCORE. VIO_VMEM regulator supplies multimedia processor peripherals. This regulator used supply memories working with multimedia processor, such DDR-SDRAM. switched mode power supply voltage down converter used generate regulated power supply with very high efficiency. master clock (13, 19.2 MHz) automatically detected, squared divided generate SMPS switching clock. When this clock available, regulators internal oscillator. Main features
Fixed output voltage power domains: `Normal mode' when multimedia processor mode full load `Low current mode' when multimedia processor sleep mode, current capability.
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Functional description
STw4810
Fast switching from current normal mode. regulator `low current mode' when multimedia processor sleep mode. PWREN signal indicates that multimedia processor about switch mode. VDDOK signal indicates multimedia processor that supplies specified range.
Note:
definition sleep mode given 4.2.3: Sleep mode section. Soft start circuitry start from power normal mode, when ball changes from "1". Default setting defined start-up configuration.
4.3.4
VPLL
This dedicated multimedia processor (1.05 power supply with full load (Power Control Registers Table Table 28). Main features
Programmable output voltage, (VPLL_SEL[1:0] bits power control register Table Table power domains: `Normal mode' full load `Power down mode' `standby mode' when regulators switched there power consumption (EN_VPLL power control register Table
Soft start circuitry start from power normal mode, when ball changes from "1". Default setting defined start-up configuration.
4.3.5
VANA
This dedicated multimedia processor analogue function (2.5 power supply with full load. Main features:
output voltage, power domains `Normal mode' full load `Power down mode' `standby mode' when regulators switched there power consumption (EN_VANA power control register Table 29),
Default setting defined start-up configuration.
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STw4810
Functional description
4.3.6
VAUX
This dedicated either multimedia processor input/output signals auxiliary devices. Power supply values V,1.8 with full load sleep mode. case output, this supplied using VIO_VMEM DC/DC converter (1.8 feed-back used. Main features:
Programmable output voltage, levels (VAUX_SEL[1:0] bits Power control register Table Three power domains: `Normal mode' when multimedia processor mode, full load `Low current mode' when multimedia processor sleep mode, current capability. Fast switching from current normal mode.
Note:
Definition sleep mode given 4.2.3: Sleep mode section. `Power down mode' `standby mode' when regulator switched off, power consumption (PDN_VAUX control register Table Default setting defined start-up configuration
4.3.7
Power supply monitoring
This block monitors VCORE VIO_VMEM output voltage. VCORE VIO_VMEM drop below threshold, multimedia processor reset. This feature desactivated setting EN_MONITORING Power control register (Table "0".
4.3.8
Power supply domains
Table lists register bits that control STw4810 supply domains each supply.
Table
Supply name VCORE
Power supply domains
Supply domains Description Normal STEP-DOWN values VCORE_SEL[3:0] values VPLL_SEL[1:0] values VAUX_SEL[1:0] values SEL_VMMC[1:0] VAUX_SLEEP VAUX_FORCE_SLEEP Sleep VCORE_SLEEP VCORE_FORCE_SLEEP VIO_MEM_SLEEP VIO_VMEM_FORCE_SLEEP EN_VPLL EN_VANA PDN_VAUX PDN_VMMC Power down EN_VCORE
VIO_VMEM STEP-DOWN VPLL VANA VAUX VMMC
Note:
More details VMMC supply given Section
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Functional description
STw4810
4.3.9
Thermal shut-down
thermal sensor used monitor temperature.
soon temperature exceeds thermal warning rising threshold, VDDOK ball goes `it_warn' control register Table 18). turns back VDDOK ball `it_warn' when device temperature drops below thermal warning falling threshold thermal sensor. second thermal detection level, thermal shutdown threshold, puts STw4810 supplies OFF, supplies goes back goes back state when temperature under thermal shutdown threshold after startup phase. Thermal threshold values
Description Unit
Table
Thermal warning threshold Rising threshold Falling threshold Thermal shutdown threshold Threshold
Figure Thermal threshold temperatures `it_warn' VDDOK ball
`it_warn' supplies turn "OFF"
VDDOK ball
Rising warning threshold Shutdown threshold Temperature
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STw4810
Functional description
module
This transceiver complies with specification:
Universal Serial specification revision supplement specification revision 1.0-a interface specification (see: transceiver specification revision 0.92) Full speed transceiver Mbit/s Mbit/s data rate) Support data line VBUS pulsing session request Host Negotiation Protocol (HNP) command status register Charge pump regulator supply VBUS line cable VBUS pull-up pull-down resistors defined Session Request Protocol (SRP) VBUS threshold comparators VUSB internal regulator which provides power supply driver receiver. line detector interrupt generator Dedicated serial control interface
transceiver modes: mode UART mode. includes:
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Functional description
STw4810
4.4.1
Block diagram
Figure transceiver block diagram
VBAT_USB VBAT_DIG VMINUS_DIG
USB_INTn
vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uart_en dat_se0 oe_int_en suspend
R_VBUS_SRP
R_VBUS_PD
CHARGE PUMP 100mA
vbus_drv
VBUS RA_BUS_IN
VBUS_MONITOR VBUS vbus_vld sess_vld
VBUS
vbus_chrg
VBUS 0.8V
VBAT_USB
VUSB_LDO
vbus_dischrg vbus_session_end
VUSB
DP_MONITOR cr_int
USBSCL
USBSDA
[0.4 0.6]
TRANCEIVER
dn_pullup dp_pullup
RPU_DP
SW_RESETn
DAT_VP
Diff
USBVM USBOEn SEO_VM OE_TP_INT
RPU_DN
USBVP
out_diff_Rx Diff suspend
RPD_DN USBRCV RPD_DP
SINGLE ENDED DECODER
SE_DP dn_pulldown SE_DN
VBAT_DIG
dp_pulldown
VBAT_USB
RID_PU 0.85*ID
Plug detect Management
IT_WAKE_UP
id_float sess_vld id_gnd
Detector
0.15*ID
id_gnd
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STw4810
Functional description
VBUS monitoring
These comparators monitor VBUS voltage. They detect current status VBUS line:
VBUS means VBUS_VALID V<VBUS<4.4 means SESSION_VALID VBUS<0.8 means SESSION_END
These three bits generate interrupt when active (see interrupt registers). VUSB LDO: Internal regulator which provides power supply driver receiver. detector: This block detects status line. capable detecting three different states line: ball floating ID_FLOAT high, ball tied ground ID_GND high ball grounded resistor. This detection generates interrupts (see interrupt registers). Transceiver: driver operate several different modes. classical lowspeed full-speed differential driver, independent single-ended drivers single-ended driver UART mode. This block contains differential receiver mode operation single-ended receivers signaling UART mode. monitor: This block used detect peripheral (0.6 DP). Pull pull down resistor: Configurable integrated pull-up pull-down resistor data line VBUS.
4.4.2
Modes operations
Power modes
transceiver power modes are:
Active power mode Suspended power mode Power down mode
suspended power mode differential transmitter receiver turned save power interface still active (pull-up pull-down VBUS on). power down mode, only serial interface active transceiver able detect SRP. power down mode, ball sensing turned on/off control control registers.
modes
transceiver modes are:
DAT_SEO mode (dat_se0 control register Table VP_VM mode (dat_se0 control register Table
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Functional description
STw4810
Data transmission transceiver transmits data following conditions control register (Table Table 32): uart_en=0; oe_int_en=0 Table Data transmission control register (DAT_SE0 mode) Suspend
Inputs USBVP USBVM Outputs Comments USBRCV used used used DIFF_RX DIFF_RX DIFF_RX DIFF_RX DAT_VP drives level SE0_VM drives level Single ended data (zero sent) Single ended data sent) Force single ended zero
mode (DAT_SE0) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode)
Table
Data transmission control register (DAT_SE0 mode) Suspend
Inputs Outputs Comments USBVP USBVM USBRCV used used used (off) (off) Driver suspended (off) (off) Single ended data (zero sent) Single ended data sent) Force single ended zero
mode (dat_se0) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode)
oe_int_en suspend=1 (USB control register Table 11), USBOEn ball becomes output used generate multimedia processor.
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STw4810 transceiver receives data following conditions: uart_en (USB control register oe_int_en Table Data receiver control register
Inputs mode (dat_se0) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (DAT_SE0 mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) (VP_VM mode) Suspend USBVP Diff Diff
Functional description
Outputs USBVM USBRCV used used used used used used used used diff diff used used used used
UART mode
UART mode entered setting `uart_en' (USB control register Table 11). transceiver contains digital logic level translators between following balls:
signal: from USBVM signal: from USBVP
When UART mode level translators disabled.
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Functional description
STw4810
VBUS monitoring control
monitoring made three comparators that determine VBUS voltage valid level operation:
VBUS valid: corresponds minimum level VBUS. voltage VBUS below threshold considered fault. During power-up, expected that this comparator output ignored. VBUS session valid: This threshold necessary session request protocol detect VBUS pulsing. VBUS session end: Session ended. this block, B-device session threshold defined within range [0.2; 0.8] reason limit that leakage current could charge VBUS (maximum).
When A-device (default master) power supplied does supply VBUS, presents input impedance RA_BUS_IN VBUS more than A-device responds VBUS pulsing method SRP, then input impedance RA_BUS_IN lower than When A-device supplies power, rise time TA_VBUS_RISE VBUS from less than when driving with external load capacitance addition VBUS decoupling capacitance). VBUS does reach this voltage within TA_VBUS_RISE maximum time, indicates that B-device drawing more current that A-device capable providing over-current condition exists. this case, A-device turns VBUS terminates session.
VBUS capacitance
dual-role device must have VBUS capacitance CDRD_VBUS value comprised between (see charge pump specification). limit decoupling capacitance allows B-device differentiate between powered-down dual-role device powereddown standard host. capacitance host higher than
Data line pull-down resistance
When A-device idle acting host, activates pull-down resistors both lines. When A-device acting peripheral, disables A-device disable both pull-down resistors during interval packet transmission when acting either host peripheral. bits control register, dn_pulldown dp_pulldown (Table used connect/disconnect pull-down resistors. When line used, pull-down activated maximum level this ball should exceed 0.342
Data line pull-up resistance
Full-speed low-speed devices differentiated position pull-up resistor from peripheral device. pull-up resistor connected line full-speed device pull-up resistor connected line low-speed device. pull-up resistor value range 1600 when idle 1425 3100 when upstream device transmitting.
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STw4810
Functional description bits control register dp_pullup dn_pullup (Table used connect/disconnect pull-up resistors.
Session Request Protocol (SRP)
save power, supplement allows A-device leave VBUS turned when being used. B-device wants when VBUS turned off, then requires A-device supply power VBUS using Session Request Protocol (SRP).
Initial conditions
B-device does attempt start session until determined A-device detected previous session. B-device must ensure that VBUS below VBUS_SESSION_END before requesting session. Additionally, B-device switches pull-down resistor (R_VBUS_PD) from VBUS ground order quicken discharge process long B-device does draw more than from VBUS. R_VBUS_PD activated `vbus_dischrg' control register (Table 12). When B-device detects that VBUS below VBUS_SESSION_END that both have been (SEO) least then previous session Adevice over session start.
Data-line pulsing
indicate request session using data line pulsing, B-device turns pull-up resistor (only full speed, pulsing). pull-up resistor connected VUSB (regulator output voltage). Timing controlled digital control.
VBUS pulsing
indicate request session using VBUS pulsing method, B-device waits initial conditions then drives VBUS. VBUS driven long enough period capacitance VBUS that smaller than 2x6.5 charged while capacitance VBUS higher than charged above this block, VBUS_SESSION_VALID threshold used determine A-device (dual role device) standard host. B-device VBUS pulsing block designed that maximum drawn current does exceed this block, pull-up 30%. B-device attached standard device, pull-up must disconnected after defined timing prevent damage standard hosts designed withstand voltage externally applied VBUS.
Session Request Protocol (SRP)
B-device correct condition start session, first performs data line pulsing, followed VBUS pulsing. When VBUS next crosses SESSION VALID threshold, device considers session progress asserts data line within After initialization, device wait least seconds A-device respond before informing user that consumption attempt failed.
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Functional description
STw4810
Host Negotiation Protocol (HNP)
start session, A-device role host default. During session, host role transferred back forth between A-device B-device number times using Host Negotiation Protocol (HNP). process this exchange host role described Supplement Specification" (rev 1.0).
detector
either active suspended power mode, detector detects condition line differentiates between following three conditions: ball floating: (e.g. with B-device connected) ball shorted ground: (e.g. with A-device connected) ball connected ground through resistor RACC_ID: (e.g.with accessory).
transceiver pulls ball VID_HI (VBAT) through resistance RID_PU when accessory plugged this case, ball externally connected ground Racc_ID resistor. comparators used detect voltage: VID_GND VID_FLOAT. detector also switch that used ground ball. This switch controlled id_gnd control register (Table 12); This pull-down used CEA_KARKIT purposes.
interrupt detector
transceiver able detect when line below Carkit Interrupt threshold `cr_int', (see interrupt register) (refer specifications, 0.92, p13).
Charge pump
From VBAT_USB, charge pump supplies VBUS, `vbus_drv' control register (Table used enable/disable charge pump.
From VBAT_USB, provides VUSB supply, `usb_en' USB_EN register (Table used enable/disable VUSB LDO.
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STw4810
Functional description
4.4.3
enable control
STw4810
this state, overall system able detect connection through IT_WAKE_UP ball with VBUS session valid comparator detection IT_WAKE_UP activated (low level) either following cases: When Mini connector cable connected goes When activity VBUS, i.e. mini connected able communicate. This mode used wake-up modem platform. this configuration, USBINTn ball enabled.
STw4810 driver enabled
USBINTn enabled. cable already connected while STw4810 starting, driver will enabled when power management ready.
Wake-up driver conditions plug-in mini A-device active detector device connected ready start data transfer, VBUS driven high (session valid high) Activity registers (00h Table Table 16). Multimedia processor ready wake-up set-up PHY. Possibility force high (enable) when writing usb_en register (Table External it_wake_up usb_en writing interface Access other register (00h 0Fh) it_wake_up only then usb_en register (Table
condition: among following possibilities
Power down driver conditions order driver power down mode:
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Functional description
STw4810
SD/MMC/SDIO module
This block provides power supply (1.8 2.85 signal shifting functions required connect following peripherals multimedia processor: card cards, high speed SDIO cards (except SDIO card version Vsupply range: [3.1; 3.6]
Cards detection automatically done multimedia processor system. Following card detection, multimedia processor starts SD/MMC application writing control register (Table start VMMC then starts protocol initialization. module includes: 2.85 voltage regulators (150 Five bidirectional level shifter channels compatible with 2.85 unidirectional lines clock: multimedia processor card feedback clock multimedia processor synchronization. Four control signals channel direction
Figure block diagram
MMC/SDIO INTERFACE
MCCMDDIR MCDATA0DIR MCDATA2DIR MCDATA31DIR VMMC
1.8V,2.85V,3V 150mA
VBAT_VMMC
MCCLK DRIVER
Vsdc2
CLKOUT
EMIF
Level
SDIO CARDS
Shifter MCCMD MCDATA0 MCDATA[3:1] MCFBCLK CMDOUT DATAOUT0 DATAOUT[3:1] LATCHCLK
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STw4810
Electrical timing characteristics
Electrical timing characteristics
Otherwise specified parameters defined 25°C. VBAT
Absolute maximum rating
Table
Symbol
STw4810 absolute maximum ratings
Description Maximum power supply Values -0.5 model(1) -450 +750 Units
Maximum operating ambient temperature Human body
VESD
Electrostatic discharge model
Charge device model(2)
tests have been performed compliance with JESD22-A114-B S5.1-2001.HBM tests have been performed compliance with ANSI-ESD S5.3.1-1999
Package dissipation
Table
Symbol
Package dissipation
Description Min. Typ. Max. Units
TFBGA 6x6x1.2mm 0.5mm ball pitch RTHJ-A Thermal resistance Junction Ambient °C/W
VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch RTHJ-A Thermal resistance Junction Ambient °C/W
Note:
Power supply
STw4810 different ways sleep mode.
different possibilities VCORE, VIO_VMEM VAUX programmed sleep mode given Table Table following tables: "Normal mode" defined "SLEEP `0'" "Sleep mode" defined "SLEEP `1'"
Table refer each Vxxx supply (VCORE VIO_VMEM VAUX).
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Electrical timing characteristics
STw4810
5.3.1
Operating conditions
Table
Symbol VBAT IQSLEEP IQSTDBY
Operating conditions (Temp range:
Description Power supply Sleep mode Quiescent Current mode Test conditions Min. Typ. Max. Units
5.3.2
VREF18
Table
Symbol VBAT VREF_18 PSRR
VREF18
Description Supply voltage Output voltage Power supply rejection ratio Noise Test conditions Min. 1.78 7.77 9.46 Typ. Max. 1.84 Units
Settling time
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STw4810
Electrical timing characteristics
5.3.3
VCORE DC/DC step-down converter
Table
Symbol
VCORE DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VCORE regulator normal mode (SLEEP `0') Otherwise specified; VCORE VBAT VRIPPLE Input power supply Battery voltage Output voltage ripple VCORE_SEL[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 (default) 0011 0010 0001 0000 -3.7% mVpp
VOUT
Programmable output voltage
-4.25%
1.50 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00
+3.7%
+4.25%
IOUT PEFF LDR(1) ISHORT ILKG PSRR(1) LIRT LDRT
Output current Power efficiency Line regulation Load regulation Short circuit current limitation(2) Quiescent current Power-down current Power supply rejection Transient line regulation Transient load regulation IOUT `en_vcore' VBAT IOUT 600] VBAT IOUT VBAT: [2.7; 4.8]V IOUT: [0.1; 600]
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Electrical timing characteristics Table
Symbol
STw4810
VCORE DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
VCORE regulator sleep mode (SLEEP= `1') VBAT VRIPPLE IOUT PEFF LIRT Input power supply Battery voltage VCORE output voltage ripple Line regulation Load regulation VCORE output current Power efficiency Quiescent current Transient line regulation VBAT= IOUT: [0.1; IOUT VBAT= VBAT: [2.7; 4.8]V IOUT: [0.1; mVpp
Guaranteed design Guaranteed design
5.3.4
VIO_VMEM DC/DC step-down converter
Table
Symbol
VIO_VMEM DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VIO_VMEM regulator normal mode (SLEEP `0') VBAT VOUT VRIPPLE LDR(2) IOUT PEFF Input power supply Battery voltage Output voltage Output ripple Line regulation Load regulation Output current Power efficiency Short circuit current limitation(2) Quiescent current Power supply rejection Transient line regulation Transient load regulation IOUT VBAT IOUT= 600] VBAT IOUT= VBAT: [2.7; 4.8]V IOUT: [0.1; 600] mVpp
ISHORT PSRR(2) LIRT LDRT
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STw4810 Table
Symbol
Electrical timing characteristics VIO_VMEM DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
VIO_VMEM regulator sleep mode (SLEEP='1') VBAT VRIPPLE IOUT PEFF LIRT Input power supply Battery voltage Output ripple Line regulation Load regulation Output current Power efficiency Quiescent current Transient line regulation VBAT IOUT [0.1; IOUT VBAT VBAT: [2.7; 4.8]V IOUT: [0.1; mVpp
Including output voltage temperature coefficient, line load regulations, voltage reference accuracy, industrial manufacturing tolerances ripple voltage switching Guaranteed design
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Electrical timing characteristics
STw4810
5.3.5
regulators
VPLL
Table
Symbol
regulators VPLL
Description Test conditions Min. Typ. Max. Units
VPLL regulator normal mode otherwise specified, VPLL VBAT Input power supply Battery voltage VPLL_SEL[1:0] (default) 1.05 IOUT EN_VPLL <100 VBAT: [2.7; 4.8]V IOUT: [0.1; VBAT IOUT [0.1;
VOUT
Output voltage
IOUT ISHORT ILKG
Output current Short-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Noise density
PSRR(1)
nVrms
LIRT LDRT En(1)
Guaranteed design
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STw4810
Electrical timing characteristics
VANA
Table
Symbol
regulators VANA
Description Test conditions Min. Typ. Max. Units
VANA regulator normal mode VBAT VOUT IOUT ISHORT ILKG PSRR(1) LIRT LDRT Input power supply Battery voltage Output voltage Output current Short-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT EN_VANA VBAT: [2.7; 4.8] IOUT: [0.1; VBAT IOUT [0.1;
Guaranteed design
VAUX
Table
Symbol
regulators VAUX
Description Test conditions Min. Typ. Max. Units
VAUX regulator normal mode (PDN_VAUX= SLEEP= `0') VOUT 1.5V VBAT Input power supply VOUT 1.8/2.5 VOUT VAUX_SEL[1:0] (default)
VOUT
Output voltage
IOUT ISHORT ILKG
Output current Short-circuit limitation Quiescent current Power-down current IOUT PDN_VAUX
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Electrical timing characteristics Table
Symbol PSRR(1)
STw4810
regulators VAUX (continued)
Description Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Settling time Test conditions VOUT=1.5 VOUT=1.5 VBAT: [2.7; 4.8]V VOUT=1.5 IOUT= [0.1; 150] VBAT IOUT [10; 90%] Min. Typ. Max. Units
LDR(1) LIRT
LDRT
VAUX regulator sleep mode (PDN_VAUX= SLEEP='1') VOUT 1.5V VIO_VMEM supply VBAT Input power supply VOUT 1.8/2.5 VOUT VAUX_SEL[1:0] (default)
VOUT
Output voltage
IOUT PSRR(1)
Output current Quiescent current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT VOUT=1.5 VOUT=1.5 VBAT: [2.7; 4.8]V VOUT=1.5 IOUT= [10; 90%] VBAT IOUT [10; 90%]
LIRT LDRT
Guaranteed design
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Electrical timing characteristics
5.3.6
Power supply monitoring
This block monitors VCORE VIO_VMEM output voltage. VCORE VIO_VMEM drops below threshold, multimedia processor reset. Table
Symbol Threshold THCORE(1) Threshold VCORE THVIO(1) Threshold VIO_VMEM VCORE150 1.65
Power supply monitoring
Description Test conditions Min. Typ. Max. Units
Comparators VBAT tRES HYFALL HYRIS Supply voltage Response time Hysteresis (input voltage falling) Hysteresis (input voltage rising)
Guaranteed design
5.4.1
Digital specifications
CMOS input/output static characteristics: interface
Table
Symbol interface(1) level input voltage High level input voltage level input current High level input current level output voltage High level output voltage (with open drain open collector) (with open drain open collector) 0.8*VIO 0.7*VIO -1.0 -1.0 0.3*VIO
CMOS input/output static characteristics: interface
Description Test conditions Min. Typ. Max. Units
0.2*VIO
VIO_VMEM
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Electrical timing characteristics
STw4810
5.4.2
CMOS input/output dynamic characteristics: interface
Table
Symbol interface (Figure Fscl thigh tlow thd_sta tsu_sta thd_dat tsu_dat tsu_sto tbuf Clock frequency Clock pulse width high Clock pulse width 1300
CMOS input/output dynamic characteristics: interface
Description Min. Typ. Max. Units
SDA, SCL, USBSDA, USBSCL rise time 20+0.1*Cb SDA, SCL, USBSDA, USBSCL fall time Start condition hold time Start condition time Data input hold time Data input time Stop condition time free time Capacitive load each line
20+0.1*Cb 1300
total capacitance line
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STw4810
Electrical timing characteristics
5.4.3
CMOS input/output static characteristics: level
control I/Os
Table
Symbol
level: control I/Os
Description Test conditions Min. Typ. Max. Units
SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN, USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK VIL(1) CI/O level input voltage High level input voltage level input current High level input current Input capacitance level output voltage High level output voltage Output fall time Output rise time Driving capability Capacitance 10pF Capacitance 10pF 0.8*Vio 0.7*Vio -1.0 -1.0 0.2*Vio 0.3*Vio
VIO_VMEM
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Electrical timing characteristics
STw4810
Interface
Table
Symbol
level: interface
Description Test conditions Min. Typ. Max. Units
interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 VIL(1) CI/O level input voltage High level input voltage level input current High level input current Input capacitance level output voltage High level output voltage Driving capability 0.8*Vio 0.7*Vio -1.0 -1.0 0.2*Vio 0.3*Vio
VIO_VMEM
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Electrical timing characteristics
5.4.4
CMOS input/output static characteristics: VBAT level
Table
Symbol
CMOS input/output static characteristics: VBAT level
Description Test conditions Min. Typ. Max. Units
IT_WAKE_UP, PON, GPO1, GPO2 level input voltage High level input voltage level input current High level input current Input capacitance level output voltage High level output voltage Output fall time Output rise time Driving capability IT_WAKE_UP, GPO1, GPO2 IT_WAKE_UP, GPO1, GPO2 Capacitance 10pF Capacitance 10pF 0.8*Vbat 0.7*Vbat -1.0 -1.0 0.2*Vbat 0.3*Vbat
CI/O
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Electrical timing characteristics
STw4810
5.4.5
CMOS input/output static characteristics: VMMC level
Table
Symbol
CMOS input/output static characteristics VMMC level
Description Test conditions Min. Typ. Max. Units
DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT CI/O level input voltage High level input voltage level input current High level input current Input capacitance level output voltage High level output voltage Driving capability 0.8*VMMC 0.7*VMMC -1.0 -1.0 0.2*VMMC 0.3*VMMC
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Electrical timing characteristics
Table
Symbol UART mode
transceiver
transceiver
Description Test conditions Min. Typ. Max. Units
Rise time
CLOAD= [50;100] [10; VOH-VOL CLOAD= [50;100] 10.90% VOH-VOL CLOAD= [50;100] |VOH-VOL| CLOAD= [50;100] |VOH-VOL|
Fall time Drive propagation delay high Drive propagation delay high
tPLH tPHL
full speed mode signals) DRFM OSCV PDEL Rise time Fall time Differential rise fall time matching Output signal crossover voltage Propagation delay USBVP USBVM Trise Tfall Skew 0.66
speed mode signals) DRFM OSCV Rise time Fall time Differential rise fall time matching Output signal crossover voltage
VBUS comparators VBAT Input power supply Rising reacting time Fall reacting time Battery voltage
Threshold VBUS monitoring VBval VBses VBUS valid VBUS session valid
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Electrical timing characteristics Table
Symbol VBUS RA_BUS_IN TA_VBUS_
RISE
STw4810
transceiver (continued)
Description Test conditions Min. Typ. Max. Units
VBUS 4.4] ILOAD
100mA
External 10µF
Data line pull-down resistance RPD_DPDN Data line pull-up resistance RPU_DP RPU_DN Pull-down VBUS RVBUS_PD Pull-up VBUS RVBUS_SRP VID_GND VID_HI (VBAT) VID_FLOAT RPU_ID RPD_ID Carkit threshold detection cR_INT Transceiver VOH_TXD_DAT VOL_TXD_DAT VIH_RXD_DAT VIL_RXD_DAT output high ISOURCE output input high input ISINK Carkit interrupt threshold ID_GND comparator threshold Battery level ID_FLOAT comparator threshold VBAT 0.15*VBAT 0.85*VBAT 1200 idle driven idle driven 1425 1425 1200 2300 1200 2300 1600 3100 1600 3100
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STw4810 Table
Symbol Charge pump VBAT VBUS Input power supply Output voltage Battery voltage Current load [0;4.8] Ext. load: External 10µF Load
Electrical timing characteristics transceiver (continued)
Description Test conditions Min. Typ. Max. Units
VUSB+0.1 4.75
5.25
VRipple IOUT
Settling time Quiescent current
Amplitude output ripple Current load VBUS Current load 100mA Output current VBAT 3.0V IOUT =100mA VBAT= 3.6V. IOUT
Efficiency
VUSB regulator VBAT(1) Input voltage Battery voltage: VBAT VOUT 0.1V VBAT min= VOUT 0.1V VUSB+0.1
VOUT ISHORT PSRR(2) NVOUT LIRT
Output voltage Short circuit current limitation Quiescent current Power supply rejection Output noise voltage Transient line regulation Settling time OFF->ON Discharge time ON>OFF
load VBAT= VOUT+0.2V VBAT= VOUT+0.2V 10Hz 100kHz VBAT 10µs. IOUT IOUT
µVrms
From charge pump "Off" feature provided Guaranteed design
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Electrical timing characteristics
STw4810
SD/MMC card interface
Table
Symbol
SD/MMC card interface
Description Test conditions Min. Typ. Max. Units
VMMC regulator specifications (PDN_VMMC VBAT Input voltage VOUT VOUT 2.85 VOUT 3.25 2.85
VOUT IOUT ISHORT ILKG PSRR(1)
Output voltage Output current Short circuit current limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Settling time OFF->ON Discharge time ON>OFF IOUT PDN_VMMC IOUT VOUT=2.85 VBAT: [3.1; 4.8]V VOUT=2.85 IOUT= 150] VOUT=2.85 VBAT: 3.4V IOUT 150] IOUT IOUT
LIR(1) LDR(1)
LIRT
LDRT
line specifications RA(2) Pull-up resistor Pull-down resistor Clock frequency data transfert mode prevent floating prevent floating With 30pF
Clock frequency With 30pF identification mode
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STw4810 Table
Symbol TPHC TPCH
Electrical timing characteristics SD/MMC card interface (continued)
Description Propagation time from Host card Propagation time from card host Clock /data skew time from host card Clock /data skew time from card host Rise time Fall time Between multimedia processor STw4810 line capacitance Test conditions Min. Typ. Max. Units
Figure Figure Figure Reference CLKOUT Figure Reference MMCLK
TSHC
TSCH
C1LINE
20(3)
C2LINE
line Between STw4810 capacitance card
20(4)
Guaranteed design interface pull resistors EMIF06-HCM01F2 device CMD; Data wires) equivalent board parasitic capacitance. EMIF06 protection board parasitic capacitance.
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Electrical timing characteristics Figure Propagation clock/data skew times
MCCLK MCCMD MCDATA[3:0] MCFBCLK CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK
STw4810
TSHC
TPHC
MCCLK
CLKOUT
MCDATA[3:0] DATAOUT[3:0]
TPHC
CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK MCCLK MCCMD MCDATA[3:0] MCFBCLK
TSCH
TPCH
CLKOUT
MCCLK
DATAOUT[3:0] MCDATA[3:0]
TPCH
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Application information
Table
Name
Application information
Components list
Components list
Typical value 22µF Comments Function VIO_VMEM output filter VCORE output filter VBAT_VIOVMEM decoupling 10µF complete system application, capacitors connected each STw4810 ball must never less than value indicated typical value column this table. This includes capacitor parameters: production dispersion bias voltage applied temperature range complete system application aging VBAT_ANA decoupling VBAT_VCORE decoupling VPLL output filter VANA output filter VREF output filter VUSB output filter VAUX output filter Flying capacitor charge pump VBUS output filter (tank charge pump capacitor) VSD_MMC output filter Vbattery input voltage decoupling capacitors Coil VIOVMEM DC/DC 4.7µH Table recommended coils Coil VCORE DC/DC
C13, C14, C15, C16, 470nF 4.7µF 2.2µF
Table
Supplier
Recommended coils
Part Number VLF3010AT-4R7MR70 0.28 0.16 0.14 0.15 0.32 0.19 Irms(1) 0.74
VLF3012AT-4R7MR74 VLF4012AT-4R7M1R1 DO1605T-472MX
Coilcraft
DO3314-472ML ME3320-472MX
Irms: decrease initial value
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Application information Table Other components
Name EMIF02 EMIF06 Order code EMIF02USB05 EMIF06-HMC01F2 Function ESD/EMI Protection
STw4810
Interface ESD/EMI Protection
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Application information
Application schematics
Figure STw4810 application schematics
Modem system clock VBAT_DIG VMINUS_DIG CLK32Kin MASTER_CLK IT_WAKE_UP REQUEST_MC TCXO_EN VLX_VIOVMEM VMINUS_VIOVMEM VBAT_VIOVMEM VIOVMEM_FB C13(*) VMINUS_ANA VBAT_ANA
VBAT_VCORE VLX_VCORE
VMINUS_VCORE
VCORE
C14(*) VBAT_VPLL_VANA VPLL VANA VREF C15(*) VBAT_VAUX VAUX C16(*)
PWREN VDDOK PORn CLK32K SW_RESETn Multimedia processor USBVP USBOEn USBVM USBRCV USBINTn USBSCL USBSDA MCCLK MCFBCLK MCCMDDIR MCCMD MCDAT0DIR MCDAT0 MCDAT31DIR MCDAT[3,1] MCDAT2DIR MCDAT2
VBAT_USB VMINUS_USB
STw4810
VUSB VBUS Filter SDIO CARD filter
EMIF02
VBAT_MMC VMMC
DATOUT[3:1] DATAOUT0 CMDOUT CLKOUT LATCHCLK
GPO1 GPO2 usefulness these capacitors depend layout
EMIF06-HMC01F2
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Package mechanical data
STw4810
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second Level Interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com.
TFBGA balls
Figure TFBGA balls 6x6x1.2mm body size ball pitch drawing. Table TFBGA balls 6x6x1.2mm body size ball pitch dimensions(1) Min. Typ. Max.
1.16 0.20 0.25 0.82 0.25 5.90 0.30 6.00 4.50 5.90 6.00 4.50 0.45 0.65 0.50 0.75 0.55 0.85 0.08 6.10 0.35 6.10 0.30
Drawing dimensions (mm)
These measurements conform JEDEC standards
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Package mechanical data Figure TFBGA balls 6x6x1.2mm body size ball pitch drawing
Note:
terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
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Package mechanical data
STw4810
VFBGA balls
Figure VFBGA balls 4.6x4.6x1.0 ball pitch drawing. Table VFBGA balls 4.6x4.6x1.0 body size ball pitch(1) Min. Typ. Max.
0.864 0.15 0.19 0.615 0.18 0.435 0.21 4.55 0.25 4.60 3.60 4.55 4.60 3.60 0.40 0.50 0.08 0.13 0.04 4.65 0.29 4.65 0.23
Drawing dimensions (mm)
These measurements conform JEDEC standards
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STw4810
Package mechanical data Figure VFBGA balls 4.6x4.6x1.0 ball pitch drawing
Note:
terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
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Ordering information
STw4810
Ordering information
Table Order codes
Package TFBGA84- pitch TFBGA84- pitch VFBGA 4.6x pitch VFBGA 4.6x pitch Tray Tape reel Tray Tape reel Packing
Part number STw4810CHDR/LF STw4810CHDT/LF STw4810CRAE/LF STw4810CRAT/LF
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Revision history
Revision history
Table
Date 24-Jan-2006
Document revision history
Revision Initial release. Modified document title. Reviewed list applications cover page. Replaced with multimedia processor. Replaced fuse with analogue function. Renamed VFUSE VANA. Modified figure Control interface format Correction Figure block diagram. Correction Figure STw4810 application schematics. Correction Section 4.2.3: Sleep mode page Removed formula some text about sleep mode. Table Power control register address page Replaced with "not used" "reserved". Update short circuit current limit Table VCORE DC/DC stepdown converter, Table VIO_VMEM DC/DC step-down converter. Updated short circuit minimum value Table regulators VAUX Table SD/MMC card interface Updated ordering information. Corrected VBAT maximum value Table Operating conditions (Temp range: °C). Updated Figure Start-up timing replaced references with values Table Table Table Table Replaced performance with VESD Table Updated minimum value removed maximum junction temperature maximum power dissipation temperature Table STw4810 absolute maximum ratings. Updated Section 4.3.9: Thermal shut-down. Changes
07-Feb-2006
09-Feb-2006
10-Mar-2006
25-Jul-2006 30-Nov-2006 15-Mar-2007
23-Apr-2007
08-Jun-2007 03-Sep-2007
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STw4810
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Power management multimedia processors Step-down converters 1.5V

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