70.8 (71.8 dBFS) 32.7 MSPS SFDR MSPS analog supply operation CMOS outp
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Diversity Receiver AD6653
70.8 (71.8 dBFS) 32.7 MSPS SFDR MSPS analog supply operation CMOS output supply LVDS output supply Integer 1-to-8 input clock divider Integrated dual-channel Sample rates MSPS sampling frequencies Internal voltage reference Integrated sample-and-hold inputs Flexible analog input range: clock duty cycle stabilizer channel isolation/crosstalk Integrated wideband digital downconverter (DDC) 32-bit, complex, numerically controlled oscillator (NCO) Decimating half-band filter filter Supports real complex output modes Fast attack/threshold detect bits Composite signal monitor Energy-saving power-down modes
Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, demodulation systems Smart antenna systems General-purpose software radios Broadband data applications
PRODUCT HIGHLIGHTS
Integrated dual, 12-bit, MSPS/150 MSPS ADC. Integrated wideband decimation filter 32-bit complex NCO. Fast overrange detect signal monitor with serial output. Proprietary differential input maintains excellent performance input frequencies MHz. Flexible output modes, including independent CMOS, interleaved CMOS, mode CMOS, interleaved LVDS. SYNC input allows synchronization multiple devices. 3-bit port register programming register readback.
FUNCTIONAL BLOCK DIAGRAM
AVDD FD[0:3]A BITS/THRESHOLD DETECT VIN+A VIN-A LP/HP DECIMATING FILTER DVDD DRVDD
AD6653
CMOS/LVDS OUTPUT BUFFER
D11A
VREF SENSE RBIAS VIN-B VIN+B MULTI-CHIP SYNC BITS/THRESHOLD DETECT SELECT LP/HP DECIMATING FILTER SIGNAL MONITOR 32-BIT TUNING
fADC
DIVIDE DUTY CYCLE STABILIZER GENERATION
CMOS OUTPUT BUFFER
CLK+ CLK- DCOA DCOB
D11B
PROGRAMMING DATA
SIGNAL MONITOR DATA
SIGNAL MONITOR INTERFACE
AGND
SYNC
FD[0:3]B
NOTES NAMES CMOS CONFIGURATION ONLY; FIGURE LVDS NAMES.
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. rights reserved.
06708-001
SDFS SCLK/ SDO/ PDWN
SDIO/ SCLK/
DRGND
AD6653 TABLE CONTENTS
Features Applications. Product Highlights Functional Block Diagram Revision History General Description Specifications. Specifications Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings. Thermal Characteristics Caution. Configurations Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory Operation Architecture Analog Input Considerations. Voltage Reference Clock Input Considerations Power Dissipation Standby Mode. Digital Outputs Digital Downconverter Downconverter Modes Numerically Controlled Oscillator (NCO) Half-Band Decimating Filter Filter. fADC/8 Fixed-Frequency Numerically Controlled Oscillator (NCO) Frequency Translation Synchronization Phase Offset. Amplitude Phase Dither Decimating Half-Band Filter Filter Half-Band Filter Coefficients. Half-Band Filter Features Fixed-Coefficient Filter Synchronization. Combined Filter Performance. Final Overrange Gain Control. Fast Detect Overview. Fast Magnitude Overrange (OR). Gain Switching. Signal Monitor Peak Detector Mode. RMS/MS Magnitude Mode. Threshold Crossing Mode. Additional Control Bits Correction Signal Monitor SPORT Output Channel/Chip Synchronization. Serial Port Interface (SPI). Configuration Using SPI. Hardware Interface. Configuration Without Accessible Features. Memory Reading Memory Register Table. Memory Register Table. Memory Register Description Applications Information Design Guidelines Evaluation Board Power Supplies Input Signals. Output Signals Default Operation Jumper Selection Settings. Alternative Clock Configurations. Alternative Analog Input Drive Configuration. Schematics. Evaluation Board Layouts Bill Materials. Outline Dimensions Ordering Guide
Rev. Page
AD6653
REVISION HISTORY
11/07-Revision Initial Version
Rev. Page
AD6653 GENERAL DESCRIPTION
AD6653 mixed-signal intermediate frequency (IF) receiver consisting dual, 12-bit, MSPS/150 MSPS ADCs wideband digital downconverter (DDC). AD6653 designed support communications applications where cost, small size, versatility desired. dual core features multistage, differential pipelined architecture with integrated output error correction logic. Each features wide bandwidth differential sample-and-hold analog input amplifiers supporting variety user-selectable input ranges. integrated voltage reference eases design considerations. duty cycle stabilizer provided compensate variations clock duty cycle, allowing converters maintain excellent performance. data outputs internally connected directly digital downconverter (DDC) receiver, simplifying layout reducing interconnection parasitics. digital receiver channels provides processing flexibility. Each receive channel four cascaded signal processing stages: 32-bit frequency translator (numerically controlled oscillator (NCO)), decimating half-band filter, fixed filter, fADC/8 fixed-frequency NCO. addition receiver, DDC, AD6653 several functions that simplify automatic gain control (AGC) function system receiver. fast detect feature allows fast overrange detection outputting four bits input level information with short latency. addition, programmable threshold detector allows monitoring incoming signal power using four fast detect bits with latency. input signal level exceeds programmable threshold, coarse upper threshold indicator goes high. Because this threshold indicator latency, user quickly turn down system gain avoid overrange condition. second AGC-related function signal monitor. This block allows user monitor composite magnitude incoming signal, which aids setting gain optimize dynamic range overall system. After digital processing, data routed directly external 12-bit output ports. These outputs from CMOS LVDS. CMOS data also output interleaved configuration double data rate, using only Port AD6653 receiver digitizes wide spectrum frequencies. Each receiver designed simultaneous reception main channel diversity channel. This sampling architecture greatly reduces component cost complexity compared with traditional analog techniques less integrated digital methods. Flexible power-down options allow significant power savings, when desired. Programming setup control accomplished using 3-bit SPI-compatible serial interface. AD6653 available 64-lead LFCSP specified over industrial temperature range -40°C +85°C.
Rev. Page
AD6653 SPECIFICATIONS
SPECIFICATIONS
AVDD DVDD DRVDD maximum sample rate, -1.0 dBFS differential input, internal reference, enabled, unless otherwise noted. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error Mode) Load Regulation INPUT-REFERRED NOISE VREF ANALOG INPUT Input Span, VREF Input Capacitance VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD IDVDD2, IDRVDD2 (3.3 CMOS) IDRVDD2 (1.8 CMOS) IDRVDD2 (1.8 LVDS) POWER CONSUMPTION Input Sine Wave Input2 (DRVDD Sine Wave Input2 (DRVDD Standby Power Power-Down Power
Temperature Full Full Full Full 25°C 25°C Full Full Full Full 25°C Full Full Full
AD6653BCPZ-125
AD6653BCPZ-150
Unit Bits
-3.9
Guaranteed ±0.3 -2.7 ±0.3 ±0.1 0.21
±0.6 -0.7 ±0.6 ±0.7
-5.2
Guaranteed ±0.2 ±0.6 -3.2 -0.9 ±0.2 ±0.2 ±0.7 ±0.7
ppm/°C ppm/°C
0.21
Full Full Full Full Full Full Full Full Full Full Full Full Full
1215 1275
1395 1450
Input capacitance refers effective capacitance between differential input AGND. Figure equivalent analog input structure. Measured with MHz, full-scale sine wave input, enabled with frequency MHz, filter enabled fS/8 output enabled with approximately loading each output bit. maximum limit applies combination IAVDD IDVDD currents. Standby power measured with input with inactive (set AVDD AGND).
Rev. Page
AD6653
SPECIFICATIONS
AVDD DVDD DRVDD maximum sample rate, -1.0 dBFS differential input, internal reference, enabled, enabled, half-band filter enabled, filter enabled, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE-RATIO (SNR) WORST SECOND THIRD HARMONIC SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST OTHER HARMONIC SPUR TWO-TONE SFDR 29.12 MHz, 32.12 dBFS) 169.12 MHz, 172.12 dBFS) CROSSTALK ANALOG INPUT BANDWIDTH
Temperature 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C
AD6653BCPZ-125 71.0 70.8
AD6653BCPZ-150 70.9 70.8
Unit
69.8 70.6 70.2
69.4 70.6 70.0
Application Note AN-835, Understanding High Speed Testing Evaluation, complete definitions. Applications Information section more information about worst other specifications AD6653. Crosstalk measured with dBFS channel with input alternate channel.
Rev. Page
AD6653
DIGITAL SPECIFICATIONS
AVDD DVDD DRVDD maximum sample rate, -1.0 dBFS differential input, internal reference, enabled, unless otherwise noted. Table
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS, SDFS)1 High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Resistance Input Capacitance Temp AD6653BCPZ-125 AD6653BCPZ-150 Unit
Full Full Full Full Full Full Full Full Full Full
CMOS/LVDS/LVPECL AVDD AVDD AVDD CMOS AVDD 1.22 1.22 1.22 -135 AVDD
CMOS/LVDS/LVPECL AVDD AVDD AVDD CMOS AVDD 1.22 1.22 1.22 -135 AVDD
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Rev. Page
AD6653
Parameter LOGIC INPUTS (SMI SDO/OEB, SCLK/PDWN)2 High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode-DRVDD High Level Output Voltage Level Output Voltage CMOS Mode-DRVDD High Level Output Voltage Level Output Voltage LVDS Mode-DRVDD Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
Temp Full Full Full Full Full Full
1.22
AD6653BCPZ-125 -134
1.22
AD6653BCPZ-150 -134
Unit
Full Full Full Full
3.29 3.25 0.05
3.29 3.25 0.05
Full Full Full Full Full Full Full Full
1.79 1.75 0.05 1.15 1.15 1.25 1.25 1.35 1.35
1.79 1.75 0.05 1.15 1.15 1.25 1.25 1.35 1.35
Pull Pull down.
Rev. Page
AD6653
SWITCHING SPECIFICATIONS
Table
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 Enabled Disabled Period-Divide-by-1 Mode (tCLK) Pulse Width High (tCLKH) Divide-by-1 Mode, Enabled Divide-by-1 Mode, Disabled Divide-by-2 Mode, Enabled Divide-by-3 Through Divide-by-8 Modes, Enabled DATA OUTPUT PARAMETERS (DATA, CMOS Noninterleaved Mode-DRVDD Data Propagation Delay (tPD)2 Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Noninterleaved Mode-DRVDD Data Propagation Delay (tPD)2 Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved Mode-DRVDD Data Propagation Delay (tPD)2 Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved Mode-DRVDD Data Propagation Delay (tPD) Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) LVDS Mode-DRVDD Data Propagation Delay (tPD)2 Propagation Delay (tDCO) Pipeline Delay (Latency) NCO, FIR, fS/8 Disabled Pipeline Delay (Latency) Enabled; fS/8 Disabled (Complex Output Mode) Pipeline Delay (Latency) NCO, Filter, fS/8 Enabled Aperture Delay (tA) Aperture Uncertainty (Jitter, Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME
Temperature Full Full Full Full Full Full Full Full
AD6653BCPZ-125
AD6653BCPZ-150 6.66 3.33 3.33
Unit MSPS MSPS
4.66 3.66
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
8.16 5.16 8.36 4.96 4.23 2.43 4.43 2.23
Cycles Cycles Cycles Cycles
Conversion rate clock rate after divider. Output propagation delay measured from transition DATA transition, with load. Wake-up time dependent value decoupling capacitors.
Rev. Page
AD6653
TIMING SPECIFICATIONS
Table
Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC TIMING REQUIREMENTS tCLK tHIGH tLOW tEN_SDIO tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSLKSDO tSSCLKSDFS Conditions SYNC rising edge setup time SYNC rising edge hold time Setup time between data rising edge SCLK Hold time between data rising edge SCLK Period SCLK Setup time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state Time required SDIO switch from input output relative SCLK falling edge Time required SDIO switch from output input relative SCLK rising edge Delay from rising edge CLK+ rising edge SCLK Delay from rising edge SCLK Delay from rising edge SCLK SDFS 0.24 Unit
-0.4 -0.4
+0.4 +0.4
Timing Diagrams
CLK+
DECIMATED CMOS DATA CHANNEL DATA BITS
tDCO
CHANNEL DATA BITS CHANNEL DATA BITS
DECIMATED DATA
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
06708-109
DECIMATED DCOA/DCOB
Figure Decimated Noninterleaved CMOS Mode Data Fast Detect Output Timing (Fast Detect Mode Select Bits 000)
CLK+
tDCO
DECIMATED CMOS DATA
CHANNEL DATA BITS
CHANNEL DATA BITS
CHANNEL DATA BITS
DECIMATED DATA
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
DECIMATED DCOA/DCOB
Figure Decimated Noninterleaved CMOS Mode Data Fast Detect Output Timing (Fast Detect Mode Select Bits Through Fast Detect Mode Select Bits 100)
Rev. Page
06708-002
AD6653
CLK+
DECIMATED INTERLEAVED CMOS DATA DECIMATED INTERLEAVED DATA DECIMATED CHANNEL DATA CHANNEL DATA CHANNEL DATA CHANNEL DATA
tDCO
CHANNEL DATA CHANNEL DATA
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
CHANNEL BITS
06708-003
Figure Decimated Interleaved CMOS Mode Data Fast Detect Output Timing
CLK+
DECIMATED CMOS OUTPUT DATA CHANNEL A/B: DATA CHANNEL A/B: DATA CHANNEL A/B: DATA
tDCO
CHANNEL A/B: DATA CHANNEL A/B: DATA CHANNEL A/B: DATA
CMOS DATA
CHANNEL A/B: BITS
CHANNEL A/B: BITS
CHANNEL A/B: BITS
CHANNEL A/B: BITS
CHANNEL A/B: BITS
CHANNEL A/B: BITS
DECIMATED DCOA/DCOB
Figure Decimated Mode CMOS Data Fast Detect Output Timing
CLK- CLK+
LVDS DATA CHANNEL DATA CHANNEL DATA CHANNEL DATA CHANNEL DATA CHANNEL DATA
LVDS FAST DCO- DCO+
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
tDCO
06708-005
Figure Decimated Interleaved LVDS Mode Data Fast Detect Output Timing
CLK+
tSSYNC
SYNC
tHSYNC
06708-006
Figure SYNC Timing Inputs
Rev. Page
06708-004
AD6653
CLK+ CLK-
tCSSCLK
SCLK
tSSCLKSDFS
SDFS
tSSCLKSDFS
DATA
DATA
Figure Signal Monitor SPORT Output Timing
Rev. Page
06708-007
AD6653 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD, DVDD AGND DRVDD DRGND AGND DRGND VIN+A/VIN+B, VIN-A/VIN-B AGND CLK+, CLK- AGND SYNC AGND VREF AGND SENSE AGND AGND RBIAS AGND AGND SCLK/DFS DRGND SDIO/DCS DRGND SDO/OEB DRGND SCLK/PDWN DRGND SDFS DRGND D0A/D0B through D11A/D11B DRGND FD0A/FD0B through FD3A/FD3B DRGND DCOA/DCOB DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating -0.3 +2.0 -0.3 +3.9 -0.3 +0.3 -0.3 AVDD -0.3 +3.9 -0.3 +3.9 -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 +3.9 -0.3 +3.9 -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -40°C +85°C 150°C -65°C +125°C
THERMAL CHARACTERISTICS
exposed paddle must soldered ground plane LFCSP package. Soldering exposed paddle customer board increases reliability solder joints maximizes thermal capability package. Table Thermal Resistance
Package Type 64-Lead LFCSP (CP-64-3)
Airflow Velocity (m/s)
JA1, 18.8 16.5 15.8
JC1,
JB1,
Unit °C/W °C/W °C/W
JEDEC 51-7, plus JEDEC 25-5 2S2P test board. JEDEC JESD51-2 (still air) JEDEC JESD51-6 (moving air). MIL-Std 883, Method 1012.1. JEDEC JESD51-8 (still air).
Typical specified 4-layer with solid ground plane. shown, airflow increases heat dissipation, which reduces addition, metal direct contact with package leads from metal traces, through holes, ground, power planes, reduces
CAUTION
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Rev. Page
AD6653 CONFIGURATIONS FUNCTION DESCRIPTIONS
INDICATOR
DRGND (LSB) DVDD FD3B FD2B FD1B FD0B SYNC CLK- CLK+
DRVDD D10B D11B (MSB) DCOB DCOA (LSB)
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD6653
PARALLEL CMOS VIEW (Not Scale)
SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN-B RBIAS SENSE VREF VIN-A VIN+A AVDD SDFS SCLK/PDWN SDO/OEB
CONNECT
DRGND DRVDD DVDD D10A D11A (MSB) FD0A FD1A FD2A FD3A
Figure LFCSP Parallel CMOS Configuration (Top View)
Table Function Descriptions (Parallel CMOS Mode)
Mnemonic Power Supplies DRGND DRVDD DVDD AVDD AGND Analog VIN+A VIN-A VIN+B VIN-B VREF SENSE RBIAS CLK+ CLK- Fast Detect Outputs FD0A FD1A FD2A FD3A FD0B FD1B FD2B FD3B Type Ground Supply Supply Supply Ground Description Digital Output Ground. Digital Output Driver Supply (1.8 Digital Power Supply (1.8 Nominal). Analog Power Supply (1.8 Nominal). Analog Ground. exposed thermal bottom package. Connect. Differential Analog Input Channel Differential Analog Input Channel Differential Analog Input Channel Differential Analog Input Channel Voltage Reference Input/Output. Voltage Reference Mode Select. Table details. External Reference Bias Resistor. Common-Mode Level Bias Output Analog Inputs. Clock Input-True. Clock Input-Complement. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details. Channel Fast Detect Indicator. Table details.
Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output
Rev. Page
06708-008
AD6653
Mnemonic Digital Inputs SYNC Digital Outputs (LSB) D10A D11A (MSB) (LSB) D10B D11B (MSB) DCOA DCOB Control SCLK/DFS SDIO/DCS Signal Monitor Port SDO/OEB SDFS SCLK/PDWN Type Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Digital Synchronization Pin. Slave mode only. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel CMOS Output Data. Channel Data Clock Output. Channel Data Clock Output. Serial Clock/Data Format Select External Mode. Serial Data I/O/Duty Cycle Stabilizer External Mode. Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) External Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input External Mode.
Rev. Page
AD6653
INDICATOR
DRGND FD3+ FD3- FD2+ FD2- DVDD FD1+ FD1- FD0+ FD0- SYNC CLK- CLK+
DRVDD (LSB) (LSB) DCO- DCO+
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD6653
PARALLEL LVDS VIEW (Not Scale)
SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN-B RBIAS SENSE VREF VIN-A VIN+A AVDD SDFS SCLK/PDWN SDO/OEB
CONNECT
DRGND DRVDD DVDD D10- D10+ D11- (MSB) D11+ (MSB)
Figure LFCSP Interleaved Parallel LVDS Configuration (Top View)
Table Function Descriptions (Interleaved Parallel LVDS Mode)
Mnemonic Power Supplies DRGND DRVDD DVDD AVDD AGND Analog VIN+A VIN-A VIN+B VIN-B VREF SENSE RBIAS CLK+ CLK- Fast Detect Outputs FD0+ FD0- FD1+ FD1- FD2+ FD2- FD3+ FD3- Type Ground Supply Supply Supply Ground Description Digital Output Ground. Digital Output Driver Supply (1.8 Digital Power Supply (1.8 Nominal). Analog Power Supply (1.8 Nominal). Analog Ground. exposed thermal bottom package. Connect. Differential Analog Input Channel Differential Analog Input Channel Differential Analog Input Channel Differential Analog Input Channel Voltage Reference Input/Output. Voltage Reference Mode Select. Table details. External Reference Bias Resistor. Common-Mode Level Bias Output Analog Inputs. Clock Input-True. Clock Input-Complement. Channel A/Channel LVDS Fast Detect Indicator 0-True. Table details. Channel A/Channel LVDS Fast Detect Indicator 0-Complement. Table details. Channel A/Channel LVDS Fast Detect Indicator 1-True. Table details. Channel A/Channel LVDS Fast Detect Indicator 1-Complement. Table details. Channel A/Channel LVDS Fast Detect Indicator 2-True. Table details. Channel A/Channel LVDS Fast Detect Indicator 2-Complement. Table details. Channel A/Channel LVDS Fast Detect Indicator 3-True. Table details. Channel A/Channel LVDS Fast Detect Indicator 3-Complement. Table details.
Rev. Page
Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output
06708-009
AD6653
Mnemonic Digital Inputs SYNC Digital Outputs (LSB) (LSB) D10+ D10- D11+ (MSB) D11- (MSB) DCO+ DCO- Control SCLK/DFS SDIO/DCS Signal Monitor Port SDO/OEB SDFS SCLK/PDWN Type Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Digital Synchronization Pin. Slave mode only. Channel A/Channel LVDS Output Data 0-True. Channel A/Channel LVDS Output Data 0-Complement. Channel A/Channel LVDS Output Data 1-True. Channel A/Channel LVDS Output Data 1-Complement. Channel A/Channel LVDS Output Data 2-True. Channel A/Channel LVDS Output Data 2-Complement. Channel A/Channel LVDS Output Data 3-True. Channel A/Channel LVDS Output Data 3-Complement. Channel A/Channel LVDS Output Data -True. Channel A/Channel LVDS Output Data 4-Complement. Channel A/Channel LVDS Output Data 5-True. Channel A/Channel LVDS Output Data 5-Complement. Channel A/Channel LVDS Output Data 6-True. Channel A/Channel LVDS Output Data 6-Complement. Channel A/Channel LVDS Output Data 7-True. Channel A/Channel LVDS Output Data 7-Complement. Channel A/Channel LVDS Output Data 8-True. Channel A/Channel LVDS Output Data 8-Complement. Channel A/Channel LVDS Output Data 9-True. Channel A/Channel LVDS Output Data 9-Complement. Channel A/Channel LVDS Output Data 10-True. Channel A/Channel LVDS Output Data 10-Complement. Channel A/Channel LVDS Output Data 11-True. Channel A/Channel LVDS Output Data 11-Complement. Channel A/Channel LVDS Data Clock Output-True. Channel A/Channel LVDS Data Clock Output-Complement. Serial Clock/Data Format Select External Mode. Serial Data Input/Output/Duty Cycle Stabilizer External Mode. Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) External Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input (Active High) External Mode.
Rev. Page
AD6653 EQUIVALENT CIRCUITS
SCLK/DFS
06708-010
Figure Equivalent Analog Input Circuit
Figure Equivalent SCLK/DFS Input Circuit
AVDD
1.2V CLK+ CLK-
SENSE
Figure Equivalent Clock lnput Circuit
06708-011
Figure Equivalent SENSE Circuit
DRVDD
AVDD
DRGND
06708-012
Figure Equivalent Digital Output Circuit
Figure Equivalent Input Circuit
AVDD
DRVDD DRVDD SDIO/DCS
06708-013
VREF
Figure Equivalent SDIO/DCS Circuit SDFS Circuit
Figure Equivalent VREF Circuit
Rev. Page
06708-017
06708-016
06708-015
06708-014
AD6653 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD DVDD DRVDD sample rate MSPS, enabled, internal reference, differential input, -1.0 dBFS, sample, 25°C, enabled, filter enabled, unless otherwise noted. plots that follow, location second third harmonics noted when they fall pass band filter.
-100 -120 -140 FREQUENCY (MHz) SECOND HARMONIC 150MSPS 2.4MHz -1dBFS 70.9dBc (71.9dBFS) SFDR 83.2dBc fNCO 18.75MHz
AMPLITUDE (dBFS)
150MSPS 140.1MHz -1dBFS 70.6dBc (71.6dBFS) SFDR 82.9dBc fNCO 126MHz
AMPLITUDE (dBFS)
THIRD HARMONIC
THIRD HARMONIC -100 -120 -140
SECOND HARMONIC
06708-018
FREQUENCY (MHz)
Figure AD6653-150 Single-Tone with MHz, fNCO 18.75
-100 -120 -140 FREQUENCY (MHz)
Figure AD6653-150 Single-Tone with 140.1 MHz, fNCO
THIRD HARMONIC -100 -120 -140 FREQUENCY (MHz)
150MSPS 30.3MHz -1dBFS 71.0dBc (72.0dBFS) SFDR 92.3dBc fNCO 24MHz
AMPLITUDE (dBFS)
150MSPS 220.1MHz -1dBFS 70.0dBc (71.0dBFS) SFDR 80.9dBc fNCO 205MHz
AMPLITUDE (dBFS)
06708-019
Figure AD6653-150 Single-Tone with 30.3 MHz, fNCO
THIRD HARMONIC -100 -120 -140 FREQUENCY (MHz) 150MSPS 70.1MHz -1dBFS 70.8dBc (71.8dBFS) SFDR 82.9dBc fNCO 56MHz
Figure AD6653-150 Single-Tone with 220.1 MHz, fNCO
-100 -120 -140 FREQUENCY (MHz) 150MSPS 332.1MHz -1dBFS 69.4dBc (70.4dBFS) SFDR 91.2dBc fNCO 321.5MHz
AMPLITUDE (dBFS)
06708-020
AMPLITUDE (dBFS)
Figure AD6653-150 Single-Tone with 70.1 MHz, fNCO
Figure AD6653-150 Single-Tone with 332.1 MHz, fNCO 321.5
Rev. Page
06708-023
06708-022
06708-021
AD6653
THIRD HARMONIC -100 -120 -140 FREQUENCY (MHz) 150MSPS 445.1MHz -1dBFS 69.1dBc (70.1dBFS) SFDR 73.7dBc fNCO 429MHz SECOND HARMONIC
AMPLITUDE (dBFS)
125MSPS 70.3MHz -1dBFS 70.9dBc (71.9dBFS) SFDR 85.9dBc fNCO 78MHz
AMPLITUDE (dBFS)
THIRD HARMONIC -100 -120 -140 FREQUENCY (MHz)
06708-024
Figure AD6653-150 Single-Tone with 445.1 MHz, fNCO
-100 -120 -140 FREQUENCY (MHz) 125MSPS 2.4MHz -1dBFS 71.0dBc (72.0dBFS) SFDR 84.6dBc fNCO 15.75MHz
Figure AD6653-125 Single-Tone with 70.3 MHz, fNCO
-100 -120 -140 FREQUENCY (MHz) THIRD HARMONIC 125MSPS 140.1MHz -1dBFS 70.6dBc (71.6dBFS) SFDR 86.1dBc fNCO 142MHz
AMPLITUDE (dBFS)
SECOND HARMONIC THIRD HARMONIC
06708-025
AMPLITUDE (dBFS)
Figure AD6653-125 Single-Tone with MHz, fNCO 15.75
THIRD HARMONIC -100 -120 -140 FREQUENCY (MHz)
Figure AD6653-125 Single-Tone with 140.1 MHz, fNCO
-100 -120 -140 FREQUENCY (MHz)
125MSPS 30.3MHz -1dBFS 70.9dBc (71.9dBFS) SFDR 90.7dBc fNCO 21MHz
AMPLITUDE (dBFS)
125MSPS 220.1MHz -1dBFS 70.2dBc (71.2dBFS) SFDR 87.9dBc fNCO 231MHz
AMPLITUDE (dBFS)
06708-026
Figure AD6653-125 Single-Tone with 30.3 MHz, fNCO
Figure AD6653-125 Single-Tone with 220.1 MHz, fNCO
Rev. Page
06708-029
06708-028
06708-027
AD6653
SFDR +85°C
SNR/SFDR (dBc)
SNR/SFDR (dBc dBFS)
SFDR (dBFS)
(dBFS)
SFDR +25°C
SFDR -40°C +25°C +85°C -40°C
SFDR (dBc) (dBc)
06708-030
85dB REFERENCE LINE
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure AD6653-150 Single-Tone SNR/SFDR Input Amplitude (AIN) with MHz, fNCO 18.75
Figure AD6653-125 Single-Tone SNR/SFDR Input Frequency (fIN) Temperature with DRVDD
-1.5
SNR/SFDR (dBc dBFS)
SFDR (dBFS) -2.0
GAIN ERROR (%FSR)
OFFSET
OFFSET ERROR (%FSR)
06708-035 06708-034
(dBFS)
-2.5
-3.0 GAIN -3.5
SFDR (dBc) (dBc)
06708-031
85dB REFERENCE LINE
-4.0
TEMPERATURE (°C)
INPUT AMPLITUDE (dBFS)
Figure AD6653-150 Single-Tone SNR/SFDR Input Amplitude (AIN) with 98.12 MHz, fNCO 100.49
SFDR/IMD3 (dBc dBFS)
Figure AD6653-150 Gain Offset Temperature
SFDR +85°C
SNR/SFDR (dBc)
SFDR (dBc) IMD3 (dBc) SFDR +25°C
SFDR -40°C INPUT FREQUENCY (MHz) +25°C +85°C -40°C
SFDR (dBFS) -100 IMD3 (dBFS)
06708-032
-120
INPUT AMPLITUDE (dBFS)
Figure AD6653-125 Single-Tone SNR/SFDR Input Frequency (fIN) Temperature with DRVDD
Figure AD6653-150 Two-Tone SFDR/IMD3 Input Amplitude (AIN) with fIN1 29.12 MHz, fIN2 32.12 MHz, MSPS, fNCO
Rev. Page
06708-033
AD6653
150MSPS 169.12MHz -7dBFS 172.12MHz -7dBFS SFDR 83.6dBc (90.6dBFS) fNCO 177MHz
SFDR/IMD3 (dBc dBFS)
SFDR (dBc) IMD3 (dBc)
AMPLITUDE (dBFS)
06708-036
-100 -120 -140
SFDR (dBFS) -100 IMD3 (dBFS)
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure AD6653-150 Two-Tone SFDR/IMD3 Input Amplitude (AIN) with fIN1 169.12 MHz, fIN2 172.12 MHz, MSPS, fNCO
-100 -120 -140
Figure AD6653-150 Two-Tone with fIN1 169.12 MHz, fIN2 172.12 MHz, MSPS, fNCO
61.9dBc NOTCH 18.5MHz NOTCH WIDTH 3MHz
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
06708-037
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure AD6653-125, WCDMA Carriers with MHz, 122.88 MHz, fNCO 168.96
-100 -120 -140 FREQUENCY (MHz)
SNR/SFDR (dBc)
Figure AD6653-150 Noise Power Ratio (NPR)
150MSPS 29.12MHz -7dBFS 32.12MHz -7dBFS SFDR 91.1dBc (98.1dBFS) fNCO 22MHz
SFDR
AMPLITUDE (dBFS)
SAMPLE RATE (MSPS)
06708-038
Figure AD6653-150 Two-Tone with fIN1 29.12 MHz, fIN2 32.12 MHz, MSPS, fNCO
Figure AD6653-150 Single-Tone SNR/SFDR Sample Rate (fS) with
Rev. Page
06708-041
06708-040
-120
06708-039
-120
AD6653
0.21
NUMBER HITS (1M)
SFDR
SNR/SFDR (dBc)
06708-042
OUTPUT CODE
INPUT COMMON-MODE VOLTAGE
Figure AD6653 Grounded Input Histogram
Figure AD6653-150 SNR/SFDR Input Common Mode (VCM) with 30.3 MHz, fNCO
SFDR
SNR/SFDR (dBc)
SFDR
DUTY CYCLE
Figure AD6653-150 SNR/SFDR Duty Cycle with 30.3 MHz, fNCO
06708-043
Rev. Page
06708-044
AD6653 THEORY OPERATION
AD6653 analog input channels, decimating channels, digital output channels. intermediate frequency (IF) input signal passes through several stages before appearing output port(s) filtered, decimated digital signal. dual design used diversity reception signals, where ADCs operate identically same carrier from separate antennae. ADCs also operated with independent analog inputs. user sample fS/2 frequency segment from MHz, using appropriate low-pass band-pass filtering inputs with little loss performance. Operation analog input permitted occurs expense increased noise distortion. nondiversity applications, AD6653 used baseband receiver, where used input data, other used input data. Synchronization capability provided allow synchronized timing between multiple channels multiple devices. phase produce known offset relative another channel device. Programming control AD6653 accomplished using 3-bit SPI-compatible serial interface. clock signal alternatively switches between sample mode hold mode (see Figure 46). When switched into sample mode, signal source must capable charging sample capacitors settling within clock cycle. small resistor series with each input help reduce peak transient current required from output stage driving source. shunt capacitor placed across inputs provide dynamic charging currents. This passive network creates low-pass filter input; therefore, precise values dependent application. undersampling applications, shunt capacitors should reduced. combination with driving source impedance, shunt capacitors limit input bandwidth. Refer Application Note AN-742, Frequency Domain Response SwitchedCapacitor ADCs; Application Note AN-827, Resonant Approach Interfacing Amplifiers Switched-Capacitor ADCs; Analog Dialogue article, "Transformer-Coupled Front-End Wideband Converters," more information this subject (see www.analog.com). general, precise values dependent application.
VIN+ CPIN, VIN- CPIN,
ARCHITECTURE
AD6653 architecture consists front-end sample-and-hold amplifier (SHA), followed pipelined switched-capacitor ADC. quantized outputs from each stage combined into final 12-bit result digital correction logic. pipelined architecture permits first stage operate input sample remaining stages operate preceding samples. Sampling occurs rising edge clock. Each stage pipeline, excluding last, consists resolution flash connected switched-capacitor digitalto-analog converter (DAC) interstage residue amplifier (MDAC). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage simply consists flash ADC. input stage each channel contains differential that dc-coupled differential single-ended modes. output staging block aligns data, corrects errors, passes data output buffers. output buffers powered from separate supply, allowing adjustment output voltage swing. During power-down, output buffers into high impedance state.
Figure Switched-Capacitor Input
best dynamic performance, source impedances driving VIN+ VIN- should matched such that common-mode settling errors symmetrical. These errors reduced common-mode rejection ADC. internal differential reference buffer creates positive negative reference voltages that define input span core. output common mode reference buffer VCMREF (approximately
Input Common Mode
analog inputs AD6653 internally biased. ac-coupled applications, user must provide this bias externally. Setting device that 0.55 AVDD recommended optimum performance, device functions over wider range with reasonable performance (see Figure 45). on-board common-mode voltage reference included design available from pin. Optimum performance achieved when common-mode voltage analog input voltage (typically 0.55 AVDD).
ANALOG INPUT CONSIDERATIONS
analog input AD6653 differential switchedcapacitor that been designed optimum performance while processing differential input signal.
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AD6653
Differential Input Configurations
Optimum performance achieved while driving AD6653 differential input configuration. baseband applications, AD8138, ADA4937-2, ADA4938-2 differential drivers provide excellent performance flexible interface ADC. output common-mode voltage AD8138 easily with AD6653 (see Figure 47), driver configured Sallen-Key filter topology provide band limiting input signal.
49.9 VIN+ AVDD
signal characteristics must considered when selecting transformer. Most transformers saturate frequencies below megahertz (MHz). Excessive signal power also cause core saturation, which leads distortion. input frequencies second Nyquist zone above, noise performance most amplifiers adequate achieve true performance AD6653. applications where parameter, differential double balun coupling recommended input configuration (see Figure 49). alternative using transformer coupled input frequencies second Nyquist zone AD8352 differential driver, shown Figure AD8352 data sheet more information. addition, application requires amplifier with variable gain, AD8375 AD8376 digital variable gain amplifiers (DVGAs) provide good performance driving AD6653. configuration, value shunt capacitor, dependent input frequency source impedance need reduced removed. Table displays recommended values network. However, these values dependent input signal should used only starting guide. Table Example Network
Frequency Range (MHz) >300 Series Each) Differential (pF) Open
AD8138
0.1µF
AD6653
06708-049
VIN-
Figure Differential Input Configuration Using AD8138
baseband applications where parameter, differential transformer coupling recommended input configuration. example shown Figure bias analog input, voltage connected center secondary winding transformer.
49.9 VIN+
AD6653
VIN-
0.1µF
Figure Differential Transformer-Coupled Configuration
0.1µF
06708-050
0.1µF
VIN+
0.1µF
0.1µF
AD6653
VIN-
06708-051
06708-052
Figure Differential Double Balun Input Configuration
0.1µF ANALOG INPUT
0.1µF 0.1µF VIN+
AD8352
0.1µF 0.1µF
AD6653
VIN-
ANALOG INPUT 0.1µF
0.1µF
Figure Differential Input Configuration Using AD8352
Rev. Page
AD6653
Single-Ended Input Configuration
single-ended input provide adequate performance cost-sensitive applications. this configuration, SFDR distortion performance degrade large input commonmode swing. source impedances each input matched, there should little effect performance. Figure shows typical single-ended input configuration.
10µF AVDD 49.9 0.1µF VIN+
VIN+A/VIN+B VIN-A/VIN-B
CORE
VREF 1.0µF 0.1µF SELECT LOGIC
SENSE 0.5V
06708-054
AVDD 10µF 0.1µF
AD6653
AD6653
VIN-
06708-053
Figure Internal Reference Configuration
Figure Single-Ended Input Configuration
VOLTAGE REFERENCE
stable accurate voltage reference built into AD6653. input range adjusted varying reference voltage applied AD6653, using either internal reference externally applied reference voltage. input span tracks reference voltage changes linearly. various reference modes summarized sections that follow. Reference Decoupling section describes best practices layout reference.
resistor divider connected externally chip, shown Figure switch again sets SENSE pin. This puts reference amplifier noninverting mode with VREF output defined follows:
VREF input range always equals twice voltage reference either internal external reference.
VIN+A/VIN+B VIN-A/VIN-B
Internal Reference Connection
comparator within AD6653 detects potential SENSE configures reference into four possible modes, which summarized Table SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 52), setting VREF Connecting SENSE VREF switches reference amplifier output SENSE pin, completing loop providing reference output.
CORE
VREF 1.0µF 0.1µF SENSE SELECT LOGIC
0.5V
06708-055
AD6653
Figure Programmable Reference Configuration
Table Reference Configuration Summary
Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF VREF AGND Resulting VREF
(see Figure
Resulting Differential Span p-p) external reference VREF
Rev. Page
AD6653
internal reference AD6653 used drive multiple converters improve gain matching, loading reference other converters must considered. Figure depicts internal reference voltage affected loading.
VREF 0.5V
CLOCK INPUT CONSIDERATIONS
optimum performance, AD6653 sample clock inputs, CLK+ CLK-, should clocked with differential signal. signal typically ac-coupled into CLK+ CLK- pins transformer capacitors. These pins biased internally (see Figure require external bias.
AVDD
REFERENCE VOLTAGE ERROR
-0.25 VREF 1.0V -0.50
1.2V CLK+ CLK-
-0.75
06708-058
-1.00
Figure Equivalent Clock Input Circuit
LOAD CURRENT (mA)
06708-056
-1.25
Clock Input Options
AD6653 very flexible clock input structure. Clock input CMOS, LVDS, LVPECL, sine wave signal. Regardless type signal being used, clock source jitter most concern, described Jitter Considerations section. Figure Figure show preferred methods clocking AD6653 clock rates MHz). jitter clock source converted from single-ended signal differential signal, using transformer. back-to-back Schottky diodes across transformer secondary limit clock excursions into AD6653 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD6653 while preserving fast rise fall times signal, which critical jitter performance.
Mini-Circuits® ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSMS2822
Figure VREF Accuracy Load
External Reference Operation
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference both modes.
REFERENCE VOLTAGE ERROR (mV)
-0.5 -1.0 -1.5 -2.0
06708-057
0.1µF CLOCK INPUT
CLK+
AD6653
06708-059
CLK-
-2.5
TEMPERATURE (°C)
Figure Transformer-Coupled Differential Clock MHz)
Figure Typical VREF Drift
When SENSE tied AVDD, internal reference disabled, allowing external reference. internal reference buffer loads external reference with equivalent load (see Figure 18). internal buffer generates positive negative full-scale references core. Therefore, external reference must limited maximum
CLOCK INPUT
0.1µF CLK+ 0.1µF SCHOTTKY DIODES: HSMS2822
AD6653
06708-157
CLK-
Figure Balun-Coupled Differential Clock MHz)
Rev. Page
AD6653
jitter clock source available, another option ac-couple differential PECL signal sample clock input pins shown Figure AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
0.1µF 0.1µF CLK+
Input Clock Divider
AD6653 contains input clock divider with ability divide input clock integer values between divide ratio other than selected, duty cycle stabilizer automatically enabled. AD6653 clock divider synchronized using external SYNC input. Register 0x100 allow clock divider resynchronized every SYNC signal only first SYNC signal after register written. valid SYNC causes clock divider reset initial state.
CLOCK INPUT
AD951x
CLOCK INPUT 0.1µF PECL DRIVER
0.1µF
AD6653
CLK-
06708-060
Figure Differential PECL Sample Clock MHz)
This synchronization feature allows multiple parts have their clock dividers aligned guarantee simultaneous input sampling.
third option ac-couple differential LVDS signal sample clock input pins, shown Figure AD9510/ clock drivers offer excellent jitter performance.
Clock Duty Cycle
Typical high speed ADCs both clock edges generate variety internal timing signals and, result, sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD6653 contains duty cycle stabilizer (DCS) that retimes nonsampling (falling) edge, providing internal clock signal with nominal duty cycle. This allows user provide wide range clock input duty cycles without affecting performance AD6653. Noise distortion performance nearly flat wide range duty cycles with shown Figure Jitter rising edge input clock still paramount concern easily reduced internal stabilization circuit. duty cycle control loop does function clock rates less than nominally. loop time constant associated with that must considered when clock rate change dynamically. wait time required after dynamic clock frequency increase decrease before loop relocked input signal. During time period that loop locked, loop bypassed, internal device timing dependent duty cycle input clock signal. such applications, appropriate disable duty cycle stabilizer. other applications, enabling circuit recommended maximize performance.
CLOCK INPUT
0.1µF
0.1µF CLK+ LVDS DRIVER
AD951x
0.1µF
Figure Differential LVDS Sample Clock MHz)
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, CLK+ should driven directly from CMOS gate, CLK- should bypassed ground with capacitor parallel with resistor (see Figure 61). CLK+ driven directly from CMOS gate. Although CLK+ input circuit supply AVDD (1.8 this input designed withstand input voltages making selection drive logic voltage very flexible.
0.1µF CLOCK INPUT
CMOS DRIVER
AD951x
OPTIONAL 0.1µF
CLK+
AD6653
CLK-
06708-062
06708-061
CLOCK INPUT
0.1µF
AD6653
CLK-
Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fIN) jitter (tJ) calculated
0.1µF
Figure Single-Ended CMOS Sample Clock MSPS)
CLOCK INPUT 0.1µF 0.1µF
CMOS DRIVER
AD951x
OPTIONAL 0.1µF
CLK+
AD6653
CLK-
06708-063
equation, aperture jitter represents root mean square jitter sources, which include clock input, analog input signal, aperture jitter specification. undersampling applications particularly sensitive jitter, shown Figure
Figure Single-Ended CMOS Sample Clock MSPS)
Rev. Page
AD6653
1.50 TOTAL POWER MEASURED
(dBc)
TOTAL POWER
0.05ps 0.20ps
1.25 IAVDD
SUPPLY CURRENT SUPPLY CURRENT
06708-066 06708-065
1.00
0.50ps
0.75 IDVDD
1.00ps 1.50ps 2.00ps 2.50ps 3.00ps 1000
06708-064
0.50
0.25 IDRVDD
INPUT FREQUENCY (MHz)
SAMPLE RATE (MSPS)
Figure Input Frequency Jitter
Figure AD6653-150 Power Current Sample Rate
1.50
TOTAL POWER
clock input should treated analog signal cases where aperture jitter affect dynamic range AD6653. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter, crystal-controlled oscillators make best clock sources. clock generated from another type source gating, dividing, another method), should retimed original clock last step. Refer Application Note AN-501 Application Note AN-756 more information about jitter performance relates ADCs (see www.analog.com).
1.25 TOTAL POWER 1.00 IAVDD 0.75
0.50 IDVDD 0.25 IDRVDD SAMPLE RATE (MSPS)
POWER DISSIPATION STANDBY MODE
shown Figure Figure power dissipated AD6653 proportional sample rate. CMOS output mode, digital power dissipation determined primarily strength digital drivers load each output bit. maximum DRVDD current (IDRVDD) calculated IDRVDD VDRVDD fCLK where number output bits (26, case AD6653, assuming bits inactive). This maximum current occurs when every output switches every clock cycle, that full-scale square wave Nyquist frequency fCLK/2. practice, DRVDD current established average number output bits switching, which determined sample rate characteristics analog input signal. Reducing capacitive load presented output drivers minimize digital power consumption. data Figure Figure taken using same operating conditions those used Typical Performance Characteristics, with load each output driver.
Figure AD6653-125 Power Current Sample Rate
asserting PDWN (either through port asserting PDWN high), AD6653 placed power-down mode. this state, typically dissipates During power-down, output drivers placed high impedance state. Asserting PDWN returns AD6653 normal operating mode. Note that PDWN referenced digital output driver supply (DRVDD) should exceed that supply voltage level. PDWN driven with logic, even when DRVDD power dissipation power-down mode achieved shutting down reference, reference buffer, biasing networks, clock. Internal capacitors discharged when entering power-down mode then must recharged when returning normal operation. result, wake-up time related time spent power-down mode, shorter power-down cycles result proportionally shorter wake-up times.
Rev. Page
AD6653
When using port interface, user place power-down mode standby mode. Standby mode allows user keep internal reference circuitry powered when faster wake-up times required. Memory Register Description section Application Note AN-877, Interfacing High Speed ADCs www.analog.com additional details. SDO/OEB low, output data drivers enabled. SDO/OEB high, output data drivers placed high impedance state. This function intended rapid access data bus. Note that referenced digital output driver supply (DRVDD) should exceed that supply voltage. When using interface, data fast detect outputs each channel independently three-stated using output enable bit, Register 0x14.
DIGITAL OUTPUTS
AD6653 output drivers configured interface with CMOS logic families matching DRVDD digital supply interfaced logic. Alternatively, AD6653 outputs configured either ANSI LVDS reduced drive LVDS using DRVDD supply. CMOS output mode, output drivers sized provide sufficient output current drive wide variety logic families. However, large drive currents tend cause current glitches supplies that affect converter performance. Applications requiring drive large capacitive loads large fanouts require external buffers latches. output data format selected either offset binary twos complement setting SCLK/DFS when operating external mode (see Table 12). detailed Application Note AN-877, Interfacing High Speed ADCs SPI, data format selected offset binary, twos complement, gray code when using control. Table SCLK/DFS Mode Selection (External Mode)
Voltage AGND (default) AVDD SCLK/DFS Offset binary Twos complement SDIO/DCS disabled enabled
Interleaved CMOS Mode
Setting Register 0x14 enables interleaved CMOS output mode. this mode, output data routed through Port with Channel output data present rising edge Channel output data present falling edge DCO.
Timing
AD6653 provides latched data with pipeline delay that dependent which digital back features enabled. Data outputs available propagation delay (tPD) after rising edge clock signal. length output data lines loads placed them should minimized reduce transients within AD6653. These transients degrade converter dynamic performance. lowest typical conversion rate AD6653 MSPS. clock rates below MSPS, dynamic performance degrade.
Data Clock Output (DCO)
AD6653 also provides data clock output (DCO) intended capturing data external register. Figure through Figure show graphical timing description AD6653 output modes.
Digital Output Enable Function (OEB)
AD6653 flexible, three-state ability digital output pins. three-state modeis enabled using SDO/OEB through interface. Table Output Data Format
Input VIN+ VIN- VIN+ VIN- VIN+ VIN- VIN+ VIN- VIN+ VIN- Condition -VREF -VREF +VREF +VREF
Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111
Twos Complement Mode 1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111
Rev. Page
AD6653 DIGITAL DOWNCONVERTER
AD6653 includes digital processing section that provides filtering reduces output data rate. This digital processing section includes numerically controlled oscillator (NCO), half-band decimating filter, filter, second coarse (fADC/8 fixed value) output frequency translation. Each these processing blocks (except decimating half-band filter) control lines that allow independently enabled disabled provide desired processing function. digital downconverter configured output either real data complex output data. These blocks configured five recommended combinations implement different signal processing functions. maximum usable bandwidth 16.5 when using filter real mode (NCO bypassed) maximum usable bandwidth 33.0 when using filter complex mode (NCO enabled). optional fixed-coefficient filter provides additional filtering capability sharpen half-band roll-off enhance alias protection. removes negative frequency images avoid aliasing negative frequencies real outputs.
fADC/8 FIXED-FREQUENCY
fixed fADC/8 provided translate filtered, decimated signal from fADC/8 allow real output. Figure Figure show example input processed blocks AD6653.
DOWNCONVERTER MODES
Table details recommended downconverter modes operation AD6653.
Mode
NCO/Filter Half-band filter only Half-band filter filter half-band filter NCO, half-band filter, filter NCO, half-band filter, filter, fADC/8
Output Type Real Real Complex Complex Real
Figure Example AD6653 Real Bandwidth Input Signal Centered (fADC MHz)
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation accomplished with NCO. Each processing channels shares common NCO. Amplitude phase dither enabled chip improve noise spurious performance NCO. phase offset word available create known phase relationship between multiple AD6653s. Because decimation filter prevents usage half Nyquist spectrum, means needed translate sampled input spectrum into usable range decimation filter. achieve this, 32-bit, fine tuning, complex provided. This NCO/mixer allows input spectrum tuned where effectively filtered subsequent filter blocks prevent aliasing.
Figure Example AD6653 Bandwidth Input Signal Tuned Using (NCO Frequency MHz)
Figure Example AD6653 Bandwidth Input Signal with Negative Image Filtered Half-Band Filters
HALF-BAND DECIMATING FILTER FILTER
goal AD6653 digital filter block allow sample rate reduced factor while rejecting aliases that fall into band interest. half-band filter designed operate either low-pass high-pass filter provide greater than alias protection input rate structure. sample rate MSPS, this provides
06708-070
0.25
12.5
22.5
Figure Example AD6653 Bandwidth Input Signal Tuned fADC/8 Real Output
Rev. Page
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06708-068
06708-067
Table Downconverter Modes
AD6653 NUMERICALLY CONTROLLED OSCILLATOR (NCO)
FREQUENCY TRANSLATION
This processing stage comprises digital tuner consisting 32-bit complex numerically controlled oscillator (NCO). channels AD6653 share single NCO. optional bypassed clearing Register 0x11D. This block accepts real input from stage outputs frequency translated complex output. frequency programmed Register 0x11E, Register 0x11F, Register 0x120, Register 0x121. These four 8-bit registers make 32-bit unsigned frequency programming word. Frequencies between -CLK/2 +CLK/2 represented using following frequency words:
PHASE OFFSET
phase offset register Address 0x122 Address 0x123 adds programmable offset phase accumulator NCO. This 16-bit register interpreted 16-bit unsigned integer. 0x00 this register corresponds offset, 0xFFFF corresponds offset 359.995°. Each represents phase change 0.005°. This register allows multiple NCOs synchronized produce outputs with predictable phase differences. following equation calculate phase offset value: NCO_PHASE PHASE/360 where: NCO_PHASE decimal number equal 16-bit binary number programmed Register 0x122 Register 0x123. PHASE desired phase degrees.
0x8000 0000 represents frequency given -CLK/2. 0x0000 0000 represents (frequency Hz). 0x7FFF FFFF represents CLK/2 CLK/232.
following equation calculate frequency:
AMPLITUDE PHASE DITHER
block contains amplitude phase dither improve spurious performance. Amplitude dither improves performance randomizing amplitude quantization errors within angular-to-Cartesian conversion NCO. This option reduces spurs expense slightly raised noise floor. With amplitude dither enabled, SFDR >115 With amplitude dither disabled, increased cost SFDR performance, which reduced amplitude dither recommended enabled setting Register 0x11D.
NCO_FREQ
Mod(
where: NCO_FREQ 32-bit twos complement number representing frequency register. desired carrier frequency hertz (Hz). fCLK AD6653 clock rate hertz (Hz).
SYNCHRONIZATION
AD6653 NCOs within single part across multiple parts synchronized using external SYNC input. Register 0x100 allow resynchronized every SYNC signal only first SYNC signal after register written. valid SYNC causes restart programmed phase offset value.
Rev. Page
AD6653 DECIMATING HALF-BAND FILTER FILTER
goal AD6653 half-band digital filter allow sample rate reduced factor while rejecting aliases that fall into band interest. This filter designed operate either low-pass high-pass filter provide >100 alias protection input rate structure. Used conjunction with filter, halfband filter provide effective band-pass. sample rate MSPS, this provides maximum usable bandwidth MHz.
AMPLITUDE (dBc) -100
06708-072
HALF-BAND FILTER COEFFICIENTS
19-tap, symmetrical, fixed-coefficient half-band filter power consumption polyphase implementation. Table lists coefficients half-band filter. normalized coefficients used implementation decimal equivalent value coefficients also listed. Coefficients listed Table Table Fixed Coefficients Half-Band Filter
Coefficient Number Normalized Coefficient 0.0008049 -0.0059023 0.0239182 -0.0755024 0.3066864 Decimal Coefficient (20-Bit) -6189 25080 -79170 321584 524287
-110 FRACTION INPUT SAMPLE RATE
Figure Half-Band Filter, High-Pass Response
half-band filter ripple 0.000182 rejection alias rejection alias protected bandwidth input sample rate. both paths used, complex bandwidth input rate available. event even Nyquist zone sampling, half-band filter configured provide spectral reversal. Setting high Address 0x103 enables spectral reversal feature. half-band decimation phase selected such that half-band filter starts first second sample following synchronization. This shifts output from half-band between input sample clocks. decimation phase using Register 0x103.
HALF-BAND FILTER AD6653, half-band filter cannot disabled. filter low-pass high-pass response. highpass filter, Register 0x103 should set; low-pass response, this should cleared. low-pass response filter with respect normalized output rate shown Figure high-pass response shown Figure
AMPLITUDE (dBc) -100
06708-071
FIXED-COEFFICIENT FILTER
Following half-band filters 66-tap, fixed-coefficient filter. This filter useful providing extra alias protection decimating half-band filter. simple sum-of-products filter with filter taps 21-bit fixed coefficients. Note that this filter does decimate. normalized coefficients used implementation decimal equivalent value coefficients listed Table user either select bypass this filter, filter enabled only when half-band filter enabled. Writing Logic enable filter (Bit Register 0x102 bypasses this fixed-coefficient filter. filter necessary when using final with real output; bypassing when using other configurations results power savings.
-110 FRACTION INPUT SAMPLE RATE
Figure Half-Band Filter, Low-Pass Response
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AD6653
Table Filter Coefficients
Coefficient Number C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, Normalized Coefficient 0.0001826 0.0006824 0.0009298 0.0000458 -0.0012689 -0.0008345 0.0011806 0.0011387 -0.0018439 -0.0024557 0.0018063 0.0035825 -0.0021510 -0.0056810 0.0017405 0.0078602 -0.0013437 -0.0110626 -0.0000229 0.0146618 0.0018959 -0.0195594 -0.0053153 0.0255623 0.0104036 -0.0341468 -0.0192165 0.0471258 0.0354118 -0.0728111 -0.0768890 0.1607208 0.4396725 Decimal Coefficient (21-Bit) 1431 1950 -2661 -1750 2476 2388 -3867 -5150 3788 7513 -4511 -11914 3650 16484 -2818 -23200 30748 3976 -41019 -11147 53608 21818 -71611 -40300 98830 74264 -152696 -161248 337056 922060
COMBINED FILTER PERFORMANCE
combined response half-band filter filter shown Figure bandlimiting data with half-band filter ideally provides improvement expense sample rate available bandwidth output data. consequence finite math, additional quantization noise added system truncation half-band. consequence digital filter rejection out-of-band noise (assuming quantization filters with white noise floor from ADC), there should 3.16 improvement SNR. However, added quantization lessens improvement about 2.66
AMPLITUDE (dBc) -100
06708-073
-110 FRACTION INPUT SAMPLE RATE
Figure Half-Band Filter Filter Composite Response
FINAL
output 32-bit fine tuning complex typically centered frequency around This complex output carried through stages half-band filters provide proper antialiasing filtering. final provides means move this complex output signal away from that real output provided from AD6653. final NCO, enabled, translates output from frequency equal sampling frequency divided (fADC/8). This provides user decimated output signal centered fADC/8 frequency. Optionally, this final bypassed, dc-centered values output interleaved fashion.
SYNCHRONIZATION
AD6653 half-band filters within single part across multiple parts synchronized using external SYNC input. Register 0x100 allow half-bands resynchronized every SYNC signal only first SYNC signal after register written. valid SYNC causes half-band filter restart programmed decimation phase value.
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AD6653 OVERRANGE GAIN CONTROL
receiver applications, desirable have mechanism reliably determine when converter about clipped. standard overflow indicator provides after-the-fact information state analog input that limited usefulness. Therefore, helpful have programmable threshold below full scale that allows time reduce gain before clip actually occurs. addition, because input signals have significant slew rates, latency this function major concern. Highly pipelined converters have significant latency. good compromise output bits from first stage this function. Latency these output bits very low, overall resolution highly significant. Peak input signals typically between full scale below full scale. 3-bit 4-bit output provides adequate range resolution this function. Using port, user provide threshold above which overrange output active. long signal below that threshold, output should remain low. fast detect outputs also programmed port that pins functions traditional overrange customers currently this feature. this mode, bits converter examined traditional manner, output high condition normally defined overflow. either mode, magnitude data considered calculation condition (but sign data considered). threshold detection responds identically positive negative signals outside desired range (magnitude).
Table Fast Detect Mode Select Settings
Fast Detect Mode Select Bits (Register 0x104[3:1]) Information Presented Fast Detect (FD) Pins Each ADC1, FD[3] FD[2] FD[1] FD[0] fast magnitude (see Table fast magnitude (see Table F_LT fast magnitude (see Table C_UT F_LT fast magnitude (see Table C_UT F_UT F_LT F_UT
fast detect pins FD0A/FD0B FD3A/FD3B CMOS mode configuration FD0+/FD0- FD3+/FD3- LVDS mode configuration. Overrange (OR) Gain Switching sections more information about C_UT, F_UT, F_LT,
FAST MAGNITUDE
When fast detect output pins configured output fast magnitude (that when fast detect mode select bits 0b000), information presented level from early converter stage with latency only clock cycles CMOS output modes. LVDS output mode, fast detect bits have latency cycles fast detect modes. Using fast detect output pins this configuration provides earliest possible level indication information. Because this information provided early datapath, there significant uncertainty level indicated. nominal levels, along with uncertainty indicated fast magnitude, shown Table Because one-half sample rate, user obtain fast detect information sampling fast detect outputs both rising falling edges (see Figure timing information).
Table Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits
Fast Magitude FD[3:0] Pins 0000 0001 0010 0011 0100 0101 0110 0111 1000 Nominal Input Magnitude Below (dB) <-24 -14.5 -14.5 -3.25 -3.25 -1.8 -1.8 -0.56 -0.56 Nominal Input Magnitude Uncertainty (dB) Minimum -18.07 -30.14 -12.04 -18.07 -8.52 -12.04 -6.02 -8.52 -4.08 -6.02 -2.5 -4.08 -1.16 -2.5 -1.16
FAST DETECT OVERVIEW
AD6653 contains circuitry facilitate fast overrange detection, allowing very flexible external gain control implementations. Each four fast detect (FD) output pins that used output information about current state input level. function these pins programmable fast detect mode select bits fast detect enable Register 0x104, allowing range information output from several points internal data path. These output pins also indicate presence overrange underrange conditions, according programmable threshold levels. Table shows configurations available fast detect pins.
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AD6653
When fast detect mode select bits 0b001, 0b010, 0b011, subset fast detect output pins available. these modes, fast detect output pins have latency clock cycles, greater input samples output rate. Table shows corresponding input levels when fast detect mode select bits 0b001 (that when fast magnitude presented FD[3:1] pins). Table Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits
Fast Magitude FD[2:0] Pins Nominal Input Magnitude Below (dB) <-24 -14.5 -14.5 -3.25 -3.25 -1.8 -1.8 Nominal Input Magnitude Uncertainty (dB) Minimum -18.07 -30.14 -12.04 -18.07 -8.52 -12.04 -6.02 -8.52 -4.08 -6.02 -2.5 -4.08 -1.16 -2.5
such detect when about reach full scale with particular input condition. result provide indicator that used quickly insert attenuator that prevents overdrive.
Coarse Upper Threshold (C_UT)
coarse upper threshold indicator asserted fast magnitude input level greater than level programmed coarse upper threshold register (Address 0x105[2:0]). This value compared with Fast Magnitude Bits[2:0]. coarse upper threshold output output clock cycles after level exceeded input and, therefore, provides fast indication input signal level. coarse upper threshold levels shown Table This indicator remains asserted minimum clock cycles until signal drops below threshold level. Table Coarse Upper Threshold Levels
Coarse Upper Threshold Register[2:0] C_UT Active When Signal Magnitude Below Greater Than (dB) <-24 -14.5 -3.25 -1.8
When fast detect mode select bits 0b010 0b011 (that when fast magnitude presented FD[2:1] pins), provided. input ranges this mode shown Table Table Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits
Fast Magitude FD[2:1] Pins Nominal Input Magnitude Below (dB) <-14.5 -14.5 -3.25 -3.25 Nominal Input Magnitude Uncertainty (dB) Minimum -12.04 -18.07 -6.02 -8.52 -2.5 -4.08
Fine Upper Threshold (F_UT)
fine upper threshold indicator asserted input magnitude exceeds value programmed fine upper threshold register located Register 0x106 Register 0x107. 13-bit threshold register compared with signal magnitude output ADC. This comparison subject clock latency accurate terms converter resolution. fine upper threshold magnitude defined following equation: dBFS log(Threshold Magnitude/213)
OVERRANGE (OR)
overrange indicator asserted when overrange detected input ADC. overrange condition determined output pipeline and, therefore, subject latency clock cycles. overrange input indicated this clock cycles after occurs.
Fine Lower Threshold (F_LT)
fine lower threshold indicator asserted input magnitude less than value programmed fine lower threshold register located Register 0x108 Register 0x109. fine lower threshold register 13-bit register that compared with signal magnitude output ADC. This comparison subject clock latency accurate terms converter resolution. fine lower threshold magnitude defined following equation: dBFS log(Threshold Magnitude/213) operation fine upper threshold fine lower threshold indicators shown Figure
GAIN SWITCHING
AD6653 includes circuitry that useful applications either where large dynamic ranges exist where gain ranging converters employed. This circuitry allows digital thresholds such that upper threshold lower threshold programmed. Fast detect mode select bits through fast detect mode select bits support various combinations gain switching options.
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AD6653
Increment Gain (IG) Decrement Gain (DG)
increment gain decrement gain indicators intended used together provide information enable external gain control. decrement gain indicator works conjunction with coarse upper threshold bits, asserting when input magnitude greater than 3-bit value coarse upper threshold register (Address 0x105). increment gain indicator, similarly, corresponds fine lower threshold bits except that asserted only input magnitude less than value programmed fine lower threshold register after dwell time elapses. dwell time 16-bit dwell time value located Address 0x10A Address 0x10B units input clock cycles ranging from 65,535. fine lower threshold register 13-bit register that compared with magnitude output ADC. This comparison subject clock latency allows finer, more accurate comparison. fine upper threshold magnitude defined following equation: dBFS log(Threshold Magnitude/213) decrement gain output works from fast detect output pins, providing fast indication potential overrange conditions. increment gain uses comparison output ADC, requiring input magnitude remain below accurate, programmable level predefined period before signaling external circuitry increase gain. operation increment gain output decrement gain output shown graphically Figure
UPPER THRESHOLD (COARSE FINE)
DWELL TIME TIMER RESET RISE ABOVE F_LT
FINE LOWER THRESHOLD
DWELL TIME C_UT F_UT* F_LT
TIMER COMPLETES BEFORE SIGNAL RISES ABOVE F_LT
*C_UT F_UT DIFFER ONLY ACCURACY LATENCY. NOTE: OUTPUTS FOLLOW INSTANTANEOUS SIGNAL LEVEL ENVELOPE GUARANTEED ACTIVE MINIMUM CLOCK CYCLES.
Figure Threshold Settings C_UT, F_UT, F_LT,
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06708-074
AD6653 SIGNAL MONITOR
signal monitor block provides additional information about signal being digitized ADC. signal monitor computes input magnitude, peak magnitude, and/or number samples which magnitude exceeds particular threshold. Together, these functions used gain insight into signal characteristics estimate peak/average ratio even shape complementary cumulative distribution function (CCDF) curve input signal. This information used drive loop optimize range presence real-world signals. signal monitor result values obtained from part reading back internal registers Address 0x116 Address 0x11B, using port signal monitor SPORT output. output contents SPI-accessible signal monitor registers signal monitor mode bits signal monitor control register (Address 0x112). Both channels must configured same signal monitor mode. Separate SPI-accessible, 20-bit signal monitor result (SMR) registers provided each channel. combination signal monitor functions also output user serial SPORT interface. These outputs enabled using peak detector output enable, magnitude output enable, threshold crossing output enable bits signal monitor SPORT control register (Address 0x111). each signal monitor measurement, programmable signal monitor period register (SMPR) controls duration measurement. This time period programmed number input clock cycles 24-bit signal monitor period register located Address 0x113, Address 0x114, Address 0x115. This register programmed with period from samples 16.78 (224) million samples. Because offset significantly larger than signal interest (affecting results from signal monitor), correction circuit included part signal monitor block null offset before measuring power. current input signal magnitude. This comparison continues until monitor period timer reaches count When monitor period timer reaches count 13-bit peak level value transferred signal monitor holding register (not accessible user), which read through port output through SPORT serial interface. monitor period timer reloaded with value SMPR, countdown restarted. addition, magnitude first input sample updated peak level holding register, comparison update procedure, explained previously, continues. Figure block diagram peak detector logic. register contains absolute magnitude peak detected peak detector logic.
FROM MEMORY POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS CLEAR MAGNITUDE STORAGE REGISTER LOAD POWER MONITOR HOLDING REGISTER LOAD MEMORY INTERRUPT CONTROLLER COUNT
COMPARE
Figure Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
this mode, root-mean-square (rms) mean-square (ms) magnitude input port signal integrated adding accumulator) over programmable time period (determined SMPR) give magnitude input signal. This mode programming Logic signal monitor mode bits signal monitor control register setting magnitude output enable signal monitor SPORT control register. 24-bit SMPR, representing period over which integration performed, must programmed before activating this mode. After enabling rms/ms magnitude mode, value SMPR loaded into monitor period timer, countdown started immediately. Each input sample converted floating-point format squared. then converted 11-bit, fixed-point format added contents 24-bit accumulator. integration continues until monitor period timer reaches count When monitor period timer reaches count square root value accumulator taken transferred (after some formatting) signal monitor holding register, which read through port output through SPORT serial port. monitor period timer reloaded with value SMPR, countdown restarted.
PEAK DETECTOR MODE
magnitude input port signal monitored over programmable time period (determined SMPR) give peak value detected. This function enabled programming Logic signal monitor mode bits signal monitor control register setting peak detector output enable signal monitor SPORT control register. 24-bit SMPR must programmed before activating this mode. After enabling this mode, value SMPR loaded into monitor period timer, countdown started. magnitude input signal compared with value internal peak level holding register (not accessible user), greater updated current peak level. initial value peak level holding register
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06708-075
AD6653
addition, first input sample signal power updated accumulator, accumulation continues with subsequent input samples. Figure illustrates magnitude monitoring logic.
FROM MEMORY POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS CLEAR ACCUMULATOR LOAD POWER MONITOR HOLDING REGISTER MEMORY
06708-076
When monitor period timer reaches count value internal count register transferred signal monitor holding register, which read through port output through SPORT serial port. monitor period timer reloaded with value SMPR register, countdown restarted. internal count register also cleared value Figure illustrates threshold crossing logic. value register number samples that have magnitude greater than threshold register.
FROM MEMORY INTERRUPT CONTROLLER COUNT
INTERRUPT CONTROLLER COUNT
Figure Input Magnitude Monitoring Block Diagram
magnitude mode, value signal monitor result (SMR) register 20-bit fixed-point number. following equation used determine magnitude dBFS from value register. Note that signal monitor period (SMP) power second term equation becomes Magnitude ceil [log (SMP magnitude mode, value 20-bit fixedpoint number. following equation used determine magnitude dBFS from value register. Note that power second term equation becomes Magnitude ceil [log (SMP
POWER MONITOR PERIOD REGISTER
DOWN COUNTER LOAD
FROM INPUT PORTS FROM MEMORY
CLEAR COMPARE UPPER THRESHOLD REGISTER COMPARE
LOAD POWER MONITOR HOLDING REGISTER
MEMORY
Figure Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
additional flexibility signal monitoring process, control bits provided signal monitor control register. They signal monitor enable complex power calculation mode enable bit.
Signal Monitor Enable
signal monitor enable bit, located Register 0x112, enables operation signal monitor block. signal monitor function needed particular application, this should cleared conserve power.
THRESHOLD CROSSING MODE
threshold crossing mode operation, magnitude input port signal monitored over programmable time period (given SMPR) count number times crosses certain programmable threshold value. This mode programming Logic (where don't care bit) signal monitor mode bits signal monitor control register setting threshold crossing output enable signal monitor SPORT control register. Before activating this mode, user needs program 24-bit SMPR 13-bit upper threshold register each individual input port. same upper threshold register used both signal monitoring gain control (see Overrange Gain Control section). After entering this mode, value SMPR loaded into monitor period timer, countdown started. magnitude input signal compared with upper threshold register (programmed previously) each input clock cycle. input signal magnitude greater than upper threshold register, internal count register incremented initial value internal count register This comparison incrementing internal count register continues until monitor period timer reaches count
Complex Power Calculation Mode Enable
When this set, part assumes that Channel digitizing data Channel digitizing data complex input signal vice versa). this mode, power reported equal This result presented Signal Monitor Value Channel register signal monitor mode bits Signal Monitor Value Channel register continues compute Channel value.
CORRECTION
Because offset significantly larger than signal being measured, correction circuit included null offset before measuring power. correction circuit also switched into main signal path, this appropriate digitizing time-varying signal with significant content, such GSM.
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06708-077
AD6653
Correction Bandwidth
correction circuit high-pass filter with programmable bandwidth (ranging between 0.15 MSPS). bandwidth controlled writing 4-bit correction control register located Register 0x10C, Bits[5:2]. following equation used compute bandwidth value correction circuit:
SIGNAL MONITOR SPORT OUTPUT
SPORT serial interface with three output pins: SCLK (SPORT clock), SDFS (SPORT frame sync), (SPORT data output). SPORT master drives three SPORT output pins chip.
SCLK
data frame sync driven positive edge SCLK. SCLK three possible baud rates: 1/2, 1/4, clock rate, based SPORT controls. SCLK also gated when sending data, based SPORT SCLK sleep bit. Using this disable SCLK when needed reduce coupling errors back into signal path, these prove problem system. Doing however, disadvantage spreading frequency content clock. desired SCLK left running ease frequency planning.
Corr
where: 4-bit value programmed Bits[5:2] Register 0x10C (values between valid programming provides same result programming 13). fCLK AD6653 sample rate hertz (Hz).
Correction Readback
current correction value read back Register 0x10D Register 0x10E Channel Register 0x10F Register 0x110 Channel correction value 14-bit value that span entire input range ADC.
SDFS
SDFS serial data frame sync, defines start frame. SPORT frame includes data from both datapaths. data from Datapath sent just after frame sync, followed data from Datapath
Correction Freeze
Setting Register 0x10C freezes correction current state continues last updated value correction value. Clearing this restarts correction adds currently calculated value data.
serial data output block. data sent first next positive edge after SDFS. Each data output block includes more magnitude, peak level, threshold crossing values from each datapath stated order. enabled, data sent, first, followed peak threshold, shown Figure
GATED, BASED CONTROL
Correction Enable Bits
Setting Register 0x10C enables correction signal monitor calculations. calculated correction value added output data signal path setting Register 0x10C.
SCLK SDFS
RMS/MS
RMS/MS
RMS/MS
06708-078
CYCLES
CYCLES
CYCLES
CYCLES
CYCLES
CYCLES
Figure Signal Monitor SPORT Output Timing (RMS, Peak, Threshold Enabled)
GATED, BASED CONTROL SCLK
SDFS
RMS/MS
RMS/MS
RMS/MS
06708-079
CYCLES
CYCLES
CYCLES
CYCLES
Figure Signal Monitor SPORT Output Timing (RMS Threshold Enabled)
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AD6653 CHANNEL/CHIP SYNCHRONIZATION
AD6653 SYNC input that allows user flexible synchronization options synchronizing internal blocks. sync feature useful guaranteeing synchronized operation across multiple ADCs. input clock divider, NCO, half-band filters, signal monitor block synchronized using SYNC input. Each these blocks, except signal monitor, enabled synchronize single occurrence SYNC signal every occurrence. SYNC input internally synchronized sample clock. However, ensure that there timing uncertainty between multiple parts, SYNC input signal should synchronized input clock signal. SYNC input should driven using single-ended CMOS-type signal.
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AD6653 SERIAL PORT INTERFACE (SPI)
AD6653 serial port interface (SPI) allows user configure converter specific functions operations through structured register space provided inside ADC. gives user added flexibility customization, depending application. Addresses accessed using serial port written read from port. Memory organized into bytes that further divided into fields. These fields documented Memory section. detailed operational information, Application Note AN-877, Interfacing High Speed ADCs SPI, www.analog.com. data composed 8-bit words. first each individual byte serial data indicates whether read command write command issued. This allows serial data input/output (SDIO) change direction from input output. addition word length, instruction phase determines whether serial frame read write operation, allowing serial port used both program chip read contents on-chip memory. instruction readback operation, performing readback causes serial data input/ output (SDIO) change direction from input output appropriate point serial frame. Data sent MSB-first mode LSB-first mode. first default power-up changed port configuration register. more information about this other features, Application Note AN-877, Interfacing High Speed ADCs SPI, www.analog.com.
CONFIGURATION USING
Three pins define this ADC: SCLK/DFS pin, SDIO/DCS pin, (see Table 22). SCLK/DFS (serial clock) used synchronize read write data presented from/to ADC. SDIO/DCS (serial data input/ output) dual-purpose that allows data sent read from internal memory registers. (chip select bar) active-low control that enables disables read write cycles. Table Serial Port Interface Pins
SCLK SDIO Function Serial Clock. serial shift clock input, which used synchronize serial interface reads writes. Serial Data Input/Output. dual-purpose that typically serves input output, depending instruction being sent relative position timing frame. Chip Select Bar. active-low control that gates read write cycles.
HARDWARE INTERFACE
pins described Table comprise physical interface between user programming device serial port AD6653. SCLK function inputs when using interface. SDIO bidirectional, functioning input during write phases output during readback. interface flexible enough controlled either FPGAs microcontrollers. method configuration described detail Application Note AN-812, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit. port should active during periods when full dynamic performance converter required. Because SCLK signal, signal, SDIO signal typically asynchronous clock, noise from these signals degrade converter performance. on-board used other devices, necessary provide buffers between this AD6653 prevent these signals from transitioning converter inputs during critical sampling periods. Some pins serve dual function when interface being used. When pins strapped AVDD ground during device power-on, they associated with specific function. Digital Outputs section describes strappable functions supported AD6653.
falling edge CSB, conjunction with rising edge SCLK, determines start framing. example serial timing definitions found Figure Table Other modes involving available. held indefinitely, which permanently enables device; this called streaming. stall high between bytes allow additional external timing. When tied high, functions placed high impedance mode. This mode turns secondary functions. During instruction phase, 16-bit instruction transmitted. Data follows instruction phase length determined bit.
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AD6653
CONFIGURATION WITHOUT
applications that interface control registers, SDIO/DCS pin, SCLK/DFS pin, SDO/OEB pin, SCLK/PDWN serve standalone CMOScompatible control pins. When device powered assumed that user intends pins static control lines duty cycle stabilizer, output data format, output enable, power-down feature control. this mode, chip select should connected AVDD, which disables serial port interface. Table Mode Selection
SDIO/DCS SCLK/DFS SDO/OEB External Voltage AVDD (default) AGND AVDD AGND (default) AVDD AGND (default) AVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs high impedance Outputs enabled Chip power-down standby Normal operation
ACCESSIBLE Table provides brief description general features that accessible SPI. These features described Application Note AN-877, Interfacing High Speed ADCs (see www.analog.com). AD6653 part-specific features described Memory Register Description section. Table Features Accessible Using
Feature Name Modes Clock Offset Test Output Mode Output Phase Output Delay VREF Description Allows user either power-down mode standby mode Allows user access Allows user digitally adjust converter offset Allows user test modes have known data output bits Allows user outputs Allows user output clock polarity Allows user vary delay Allows user reference voltage.
SCLK/PDWN
tHIGH tLOW
tCLK
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Port Interface Timing Diagram
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06708-080
AD6653 MEMORY
READING MEMORY REGISTER TABLE
Each memory register table eight locations. memory roughly divided into four sections: chip configuration registers (Address 0x00 Address 0x02); channel index transfer registers (Address 0x05 Address 0xFF); functions registers, including setup, control, test (Address 0x08 Address 0x18); digital feature control registers (Address 0x100 Address 0x123). memory register table (see Table documents default hexadecimal value each hexadecimal address shown. column with heading (MSB) start default hexadecimal value given. example, Address 0x18, VREF select register, hexadecimal default value 0xC0. This means that remaining bits This setting default reference selection setting. default value uses reference. more information this function others, Application Note AN-877, Interfacing High Speed ADCs SPI. This document details functions controlled Register 0x00 Register 0xFF. remaining registers, from Register 0x100 Register 0x123, documented Memory Register Description section.
Logic Levels
explanation logic level terminology follows: "Bit set" synonymous with "bit Logic "writing Logic bit." "Clear bit" synonymous with "bit Logic "writing Logic bit."
Transfer Register
Address 0x08 Address 0x18 Address 0x11E Address 0x123 shadowed. Writes these addresses affect part operation until transfer command issued writing 0x01 Address 0xFF, setting transfer bit. This allows these registers updated internally simultaneously when transfer set. internal update takes place when transfer set, autoclears.
Channel-Specific Registers
Some channel setup functions, such signal monitor thresholds, programmed differently each channel. these cases, channel address locations internally duplicated each channel. These registers bits designated Table local. These local registers bits accessed setting appropriate Channel Channel bits Register 0x05. both bits set, subsequent write affects registers both channels. read cycle, only Channel Channel should read registers. both bits during read cycle, part returns value Channel Registers bits designated global Table affect entire part channel features where independent settings allowed between channels. settings Register 0x05 affect global registers bits.
Open Locations
address locations that included Table currently supported this device. Unused bits valid address location should written with Writing these locations required only when part address location open (for example, Address 0x18). entire address location open (for example, Address 0x13), this address location should written.
Default Values
After AD6653 reset, critical registers loaded with default values. default values registers given memory register table, Table
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AD6653
MEMORY REGISTER TABLE
address locations that included Table currently supported this device.
Table Memory Registers
Addr. Register (Hex) Name (MSB) Chip Configuration Registers 0x00 Port Configuration (Global) first Soft reset Soft reset first (LSB) Default Value (Hex) 0x18 Default Notes/ Comments nibbles mirrored that LSB-first MSB-first mode registers correctly, regardless shift mode Default unique chip different each device; this read-only register Speed grade used differentiate devices; this read-only register Bits determine which device chip receives next write command; applies local registers Synchronously transfers data from master shift register slave Determines various generic modes chip operation
0x01
Chip (Global)
8-bit Chip ID[7:0] (AD6653 0x0E) (default)
0x0E
0x02
Chip Grade (Global)
Open
Open
Speed Grade ID[4:3] MSPS MSPS
Open
Open
Open
Open
Channel Index Transfer Registers 0x05 Open Open Channel Index
Open
Open
Open
Open
Data Channel (default)
Data Channel (default)
0x03
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
Functions Registers 0x08 Open Power Modes
Open
0x09
Global Clock (Global)
Open
Open
External powerdown function (global) pdwn stndby Open
Open
Open
Open
Internal power-down mode (local) normal operation full power-down standby normal operation Open Duty cycle stabilize (default)
0x00
Open
Open
Open
0x01
0x0B
Clock Divide (Global)
Open
Open
Open
Open
Open
Clock divide ratio divide divide divide divide divide divide divide divide
0x00
Clock divide values other than automatically activate duty cycle stabilization
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AD6653
Addr. (Hex) 0x0D Register Name Test Mode (Local) (MSB) Open Open Reset long sequence Output test mode (default) midscale short positive negative alternating checkerboard long sequence short sequence one/zero word toggle Offset adjust LSBs from (twos complement format) Reset short sequence Open (LSB) Default Value (Hex) 0x00 Default Notes/ Comments When enabled, test data placed output pins place output data
0x10
0x14
Offset Adjust (Local) Output Mode
Open
Open
0x00
0x16
Clock Phase Control (Global)
Drive strength CMOS ANSI LVDS CMOS reduced LVDS (global) Invert clock
Output type CMOS LVDS (global)
Interleaved CMOS (global)
Output enable (local)
Open
Output invert (local)
offset binary twos complement gray code offset binary (local)
0x00
Configures outputs format data
Open
Open
Open
Open
0x17
Output Delay (Global)
Open
Open
Open
0x18
Reference voltage selection 1.25 1.75 (default) Digital Feature Control Registers 0x100 Sync Control Signal Half-band monitor next sync (Global) sync only enable 0x101 Open Open fS/8 Output Control (Global) 0x102 Open Open Filter Output Mode Control (Global) 0x103 Digital Filter Control (Global) Fast Detect Control (Local) Open Open
VREF Select (Global)
Open
Open
Input clock divider phase adjust delay input clock cycle input clock cycles input clock cycles input clock cycles input clock cycles input clock cycles input clock cycles clock delay (delay 2500 register value/31) 00000 00001 00010 11110 2419 11111 2500 Open Open Open Open
0x00
Allows selection clock delays into input clock divider
0x00
0xC0
Half-band sync enable
NCO32 next sync only
NCO32 sync enable Open
Clock divider next sync only Open
fS/8 start state
Clock divider sync enable fS/8 next sync only
Master sync enable fS/8 sync enable filter enable
0x00
0x00
Open
Open
Open
Open
0x104
Open
Open
Open
Open
gain fS/8 output Complex disable output gain enable gain Half-band Spectral High-pass/ decimation reversal low-pass phase select Fast Detect Mode Select[2:0]
0x00
Open
0x01
Fast detect enable
0x00
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AD6653
Addr. (Hex) 0x105 Register Name Coarse Upper Threshold (Local) Fine Upper Threshold Register (Local) Fine Upper Threshold Register (Local) Fine Lower Threshold Register (Local) Fine Lower Threshold Register (Local) Increase Gain Dwell Time Register (Local) Increase Gain Dwell Time Register (Local) Signal Monitor Correction Control (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor SPORT Control (Global) Signal Monitor Control (Global) (MSB) Open Open Open Open Open (LSB) Coarse Upper Threshold[2:0] Default Value (Hex) 0x00 Default Notes/ Comments
0x106
Fine Upper Threshold[7:0]
0x00
0x107
Open
Open
Open
Fine Upper Threshold[12:8]
0x00
0x108
Fine Lower Threshold[7:0]
0x00
0x109
Open
Open
Open
Fine Lower Threshold[12:8]
0x00
0x10A
Increase Gain Dwell Time[7:0]
0x00
clock cycles
0x10B
Increase Gain Dwell Time[15:8]
0x00
clock cycles
0x10C
Open
correction freeze
Correction Bandwidth(k:[3:0])
correction signal path enable
correction signal monitor enable
0x00
0x10D
Value Channel A[7:0]
Read only
0x10E
Open
Open
Value Channel A[13:8]
Read only
0x10F
Value Channel B[7:0]
Read only
0x110
Open
Open
Value Channel B[13:8]
Read only
0x111
Open
magnitude output enable Open
Peak detector output enable Open
Threshold crossing output enable Open
0x112
Complex power calculation mode enable
SPORT SCLK divide SPORT SCLK Undefined sleep divide divide divide Signal monitor mode Signal monitor rms/ms magnitude rms/ms peak detector select threshold crossing threshold crossing
Signal monitor SPORT output enable Signal monitor enable
0x04
0x00
Rev. Page
AD6653
Addr. (Hex) 0x113 Register Name Signal Monitor Period Register (Global) Signal Monitor Period Register (Global) Signal Monitor Period Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (Global) Signal Monitor Value Channel Register (global) Signal Monitor Value Channel Register (Global) Control (Global) Frequency Frequency Frequency Frequency Phase Offset Phase Offset (MSB) Signal Monitor Period[7:0] (LSB) Default Value (Hex) 0x80 Default Notes/ Comments clock cycles
0x114
Signal Monitor Period[15:8]
0x00
clock cycles
0x115
Signal Monitor Period[23:16]
0x00
clock cycles
0x116
Signal Monitor Result Channel A[7:0]
Read only
0x117
Signal Monitor Result Channel A[15:8]
Read only
0x118
Open
Open
Open
Open
Signal Monitor Result Channel A[19:16]
Read only
0x119
Signal Monitor Result Channel B[7:0]
Read only
0x11A
Signal Monitor Result Channel B[15:8]
Read only
0x11B
Open
Open
Open
Open
Signal Monitor Result Channel B[19:16]
Read only
0x11D
Open
Open
Open
Open
Open
NCO32 phase dither enable
NCO32 amplitude dither enable
NCO32 enable
0x00
0x11E 0x11F 0x120 0x121 0x122 0x123
Frequency Value[7:0] Frequency Value[15:8] Frequency Value[23:16] Frequency Value[31:24] Phase Value[7:0] Phase Value[15:8]
0x00 0x00 0x00 0x00 0x00 0x00
Rev. Page
AD6653
MEMORY REGISTER DESCRIPTION
more information functions controlled Register 0x00 Register 0xFF, Application Note AN-877, Interfacing High Speed ADCs SPI, www.analog.com.
fS/8 Output Control (Register 0x101) Bits[7:6]-Reserved Bits[5:4]-fS/8 Start State
starting phase fS/8 output mix.
SYNC Control (Register 0x100) 7-Signal Monitor Sync Enable
enables sync pulse from external sync input signal monitor block. sync signal passed when high. This continuous sync mode.
Bits[3:2]-Reserved 1-fS/8 Next Sync Only
master sync enable (Register 0x100, fS/8 sync enable (Register 0x101, high, allows fS/8 output synchronize following first sync pulse receives ignore rest. Register 0x100 resets after synchronizes.
6-Half-Band Next Sync Only
master sync enable (Register 0x100, halfband sync enable (Register 0x100, high, allows NCO32 synchronize following first sync pulse receives ignore rest. set, Register 0x100 resets after this sync occurs.
0-fS/8 Sync Enable
gates sync pulse fS/8 output mix. This sync active only when master sync enable (Register 0x100, high. This continuous sync mode.
5-Half-Band Sync Enable
gates sync pulse half-band filter. When high, sync signal causes half-band resynchronize, starting half-band decimation phase selected Register 0x103, This sync active only when master sync enable (Register 0x100, high. This continuous sync mode.
Filter Output Mode Control (Register 0x102) Bits[7:4]-Reserved 3-FIR Gain
When high, filter path, enabled, gain When low, filter path gain
4-NCO32 Next Sync Only
master sync enable (Register 0x100, NCO32 sync enable (Register 0x100, high, allows NCO32 sync following first sync pulse receives ignores rest. Register 0x100 resets after sync occurs set.
2-fS/8 Output Disable
disables fS/8 output when enabled. should along with enable complex output mode.
1-Complex Output Mode Enable
Setting high enables complex output mode.
3-NCO32 Sync Enable
gates sync pulse 32-bit NCO. When this high, sync signal causes resynchronize, starting phase offset value. This sync active only when master sync enable (Register 0x100, high. This continuous sync mode.
0-FIR Filter Enable
When high, enables filter. When cleared, filter bypassed shut down power savings.
2-Clock Divider Next Sync Only
master sync enable (Register 0x100, clock divider sync enable (Register 0x100, high, allows clock divider synchronize following first sync pulse receives ignore rest. Register 0x100 resets after synchronizes.
Digital Filter Control (Register 0x103) Bits[7:4]-Reserved 3-Half-Band Decimation Phase
When high, uses alternate phase decimating half-band filter.
2-Spectral Reversal
enables spectral reversal feature half-band filter.
1-Clock Divider Sync Enable
gates sync pulse clock divider. sync signal passed when high. This continuous sync mode.
1-High-Pass/Low-Pass Select
enables high-pass mode half-band filter when high. Setting this enables low-pass mode (default).
0-Master Sync Enable
must high enable sync functions.
0-Reserved
reads back
Rev. Page
AD6653
Fast Detect Control (Register 0x104) Bits[7:4]-Reserved Bits[3:1]-Fast Detect Mode Select
Bits[3:1] mode fast detect output bits according Table
Signal Monitor Correction Control (Register 0x10C) 7-Reserved 6-DC Correction Freeze
When high, correction longer updated signal monitor block, which holds last value calculated.
0-Fast Detect Enable
used enable fast detect output pins. When outputs disabled, outputs into high impedance state. LVDS mode when outputs interleaved, outputs high-Z only both channels turned (power-down/ standby/output disabled). only channel turned (power-down/standby/output disabled), fast detect outputs repeat data active channel.
Bits[5:2]-DC Correction Bandwidth
Bits[5:2] averaging time signal monitor correction function. This 4-bit word sets bandwidth correction block, according following equation:
Corr
fCLK
Coarse Upper Threshold (Register 0x105) Bits[7:3]-Reserved Bits[2:0]-Coarse Upper Threshold
These bits level required assert coarse upper threshold indication (see Table 21).
where: value programmed Bits[5:2] Register 0x10C (values between valid programming provides same result programming 13). fCLK AD6653 sample rate hertz (Hz).
1-DC Correction Signal Path Enable
Setting this high causes output measurement block summed with data signal path remove offset from signal path.
Fine Upper Threshold (Register 0x106 Register 0x107) Register 0x107, Bits[7:5]-Reserved Register 0x107, Bits[4:0]-Fine Upper Threshold Bits[12:8] Register 0x106, Bits[7:0]-Fine Upper Threshold Bits[7:0]
These registers provide fine upper limit threshold. 13-bit value compared with 13-bit magnitude from block and, magnitude exceeds this threshold value, F_UT indicator set.
0-DC Correction Signal Monitor Enable
This enables correction function signal monitor block. correction averaging function that used signal monitor remove offset signal. Removing this from measurement allows more accurate power reading.
Fine Lower Threshold (Register 0x108 Register 0x109) Register 0x109, Bits[7:5]-Reserved Register 0x109, Bits[4:0]-Fine Lower Threshold Bits[12:8] Register 0x108, Bits[7:0]-Fine Lower Threshold Bits[7:0]
These registers provide fine lower limit threshold. This 13-bit value compared with 13-bit magnitude from block and, magnitude less than this threshold value, F_LT indicator set.
Signal Monitor Value Channel (Register 0x10D Register 0x10E) Register 0x10E, Bits[7:6]-Reserved Register 0x10E, Bits[5:0]-DC Value Channel A[13:8] Register 0x10D, Bits[7:0]-DC Value Channel A[7:0]
These read-only registers hold latest offset value computed signal monitor Channel
Increase Gain Dwell Time (Register 0x10A Register 0x10B) Register 0x10B, Bits[7:0]-Increase Gain Dwell Time Bits[15:8] Register 0x10A, Bits[7:0]-Increase Gain Dwell Time Bits[7:0]
These register values minimum time sample clock cycles (after clock divider) that signal needs stay below fine lower threshold limit before F_LT asserted high.
Signal Monitor Value Channel (Register 0x10F Register 0x110) Register 0x110, Bits[7:6]-Reserved Register 0x110, Bits[5:0]-Channel Value Bits[13:8] Register 0x10F, Bits[7:0]-Channel Value Bits [7:0]
These read-only registers hold latest offset value computed signal monitor Channel
Signal Monitor SPORT Control (Register 0x111) 7-Reserved 6-RMS/MS Magnitude Output Enable
enables 20-bit magnitude measurement output SPORT.
Rev. Page
AD6653
5-Peak Detector Output Enable
enables 13-bit peak measurement output SPORT.
Signal Monitor Result Channel (Register 0x116 Register 0x118) Register 0x118, Bits[7:4]-Reserved Register 0x118, Bits[3:0]-Signal Monitor Result Channel A[19:16] Register 0x117, Bits[7:0]-Signal Monitor Result Channel A[15:8] Register 0x116, Bits[7:0]-Signal Monitor Result Channel A[7:0]
This 20-bit value contains power value calculated signal monitor block Channel content dependent settings Register 0x112, Bits[2:1].
4-Threshold Crossing Output Enable
enables 13-bit threshold measurement output SPORT.
Bits[3:2]-SPORT SCLK Divide
values these bits SPORT SCLK divide ratio from input clock. value 0x01 sets divide-by-2 (default), value 0x10 sets divide-by-4, value 0x11 sets divide-by-8.
1-SPORT SCLK Sleep
Setting high causes SCLK remain when signal monitor block data transfer.
0-Signal Monitor SPORT Output Enable
When set, enables signal monitor SPORT output begin shifting result data from signal monitor block.
Signal Monitor Result Channel (Register 0x119 Register 0x11B) Register 0x11B, Bits[7:4]-Reserved Register 0x11B, Bits[3:0]-Signal Monitor Result Channel B[19:16] Register 0x11A, Bits[7:0]-Signal Monitor Result Channel B[15:8] Register 0x119, Bits[7:0]-Signal Monitor Result Channel B[7:0]
This 20-bit value contains power value calculated signal monitor block Channel content dependent settings Register 0x112, Bits[2:1].
Signal Monitor Control (Register 0x112) 7-Complex Power Calculation Mode Enable
This mode assumes data present channel data present alternate channel. result reported complex power measured
Bits[6:4]-Reserved 3-Signal Monitor RMS/MS Select
Setting selects power measurement mode. Setting high selects power measurement mode.
Control (Register 0x11D) Bits[7:3]-Reserved 2-NCO32 Phase Dither Enable
When set, phase dither enabled. When cleared, phase dither disabled.
Bits[2:1]-Signal Monitor Mode
mode signal monitor data output registers Address 0x116 through Address 0x11B. Setting these bits 0x00 selects rms/ms magnitudde output, setting these bits 0x01 selects peak detector output, setting 0x10 0x11 selects threshold crossing output.
1-NCO32 Amplitude Dither Enable
When set, amplitude dither enabled. When cleared, amplitude dither disabled.
0-NCO32 Enable
When set, this enables 32-bit operating frequency programmed into frequency register. When cleared, bypassed shuts down power savings.
0-Signal Monitor Enable
Setting high enables signal monitor block.
Signal Monitor Period (Register 0x113 Register 0x115) Register 0x115 Bits 7:0-Signal Monitor Period[23:16] Register 0x114 Bits 7:0-Signal Monitor Period[15:8] Register 0x113 Bits 7:0-Signal Monitor Period[7:0]
This 24-bit value sets number clock cycles over which signal monitor performs operation. minimum value this register cycles (programmed values less than revert 128).
Rev. Page
AD6653
Frequency (Register 0x11E Register 0x121) Register 0x11E, Bits[7:0]-NCO Frequency Value[7:0] Register 0x11F, Bits [7:0]-NCO Frequency Value[15:8] Register 0x120, Bits[7:0]-NCO Frequency Value[23:16] Register 0x121, Bits[7:0]-NCO Frequency Value[31:24]
This 32-bit value used program tuning frequency. frequency value programmed given following equation:
fCLK NCO_FREQ fCLK
Phase Offset (Register 0x122 Register 0x123) Register 0x122, Bits[7:0]-NCO Phase Value[7:0] Register 0x123, Bits[7:0]-NCO Phase Value[15:8]
16-bit value programmed into phase value register loaded into block each time started when SYNC signal received. This process allows started with known nonzero phase. following equation calculate phase offset value: NCO_PHASE PHASE/360 where: NCO_PHASE decimal number equal 16-bit binary number programmed Register 0x122 Register 0x123. PHASE desired phase degrees.
where: NCO_FREQ 32-bit twos complement number representing frequency register. desir
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