BH616UV1611 Wide operation voltage 1.65V 3.6V Ultra power consump
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Ultra Power/High Speed CMOS SRAM 8-bit
BH616UV1611
Wide operation voltage 1.65V 3.6V Ultra power consumption 3.6V Operation current 10mA (Max.) 55ns (Max.) 1MHz Standby current 5.0uA (Typ.) 3.0V/25OC 1.2V Data retention current 1.5uA(Typ.) 25OC High speed access time 55ns (Max.) VCC=1.65~3.6V 70ns (Max.) VCC=1.65~3.6V Automatic power down when chip deselected Easy expansion with CE1, options Configuration x8/x16 selectable pin. Three state outputs compatible Fully static operation, clock, refresh Data retention supply voltage 1.0V
DESCRIPTION
BH616UV1611 high performance, ultra power CMOS Static Random Access Memory organized 1,048,576 bits operates wide range 1.65V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical operating current 1.5mA 1MHz 3.0V/25OC maximum access time 55ns 1.65V/85OC. Easy memory expansion provided active chip enable (CE1), active HIGH chip enable (CE2) active output enable (OE) three-state output drivers. BH616UV1611 automatic power down feature, reducing power consumption significantly when chip deselected. BH616UV1611 available DICE form, JEDEC standard 48-pin TSOP-I 48-ball package.
POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY
BH616UV1611DI BH616UV1611BI BH616UV1611TI Industrial -40OC +85OC 30uA 25uA 10mA 1.5mA
OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
TYPE
VCC=1.8V 10MHz fMax.
VCC=3.6V
VCC=1.8V
1MHz
VCC=3.6V 10MHz
fMax.
1MHz
DICE BGA-48-0810 TSOP I-48
CONFIGURATIONS
DQ14 DQ15 BYTE DQ15/A20 DQ14 DQ13 DQ12 DQ11 DQ10
BLOCK DIAGRAM
Address Input Buffer
Decoder
1024
Memory Array
1024 16384
BH616UV1611TI
16384 DQ15 Data Input Buffer Data Output Buffer 1024 Column Decoder Control Address Input Buffer Column Write Driver Sense
DQ10 DQ11 DQ12 DQ13
CE2,
48-ball view
Brilliance Semiconductor, Inc. reserves right change products specifications without notice.
Detailed product characteristic test report available upon request being accepted.
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
DESCRIPTIONS
Name
Function
Address Input (word mode) These address inputs select 1,024K RAM, BYTE HIGH Address Input (byte mode) These address inputs select 2,048K RAM, BYTE (TSOP only) active active HIGH. Both chip enables must active when Chip Enable Input data read from write device. either chip enable active, device Chip Enable Input
deselected standby power mode. pins will high impedance state when device deselected.
Write Enable Input
write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location. output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impendence state when inactive. Lower byte upper byte data input/output control pins.
Output Enable Input
Data Byte Control Input BYTE Byte Enable Input (TSOP only) DQ0-DQ15 Data Input/Output Ports
This input selects organization SRAM. 1,024K 16-bit configuration selected BYTE HIGH. 2,048K 8-bit configuration selected BYTE bi-directional ports used read data from write data into RAM.
Power Supply
Ground
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
TRUTH TABLE Byte Mode (TSOP only) MODE
Chip De-selected (Power Down) Output Disabled Read (byte mode) Write (byte mode)
BYTE DQ0~DQ7 DQ8~DQ14 DQ15
High High High DOUT High High High High High High High
CURRENT
ICCSB, ICCSB1 ICCSB, ICCSB1
Word Mode MODE
Chip De-selected (Power Down) Output Disabled Read (word mode)
BYTE DQ0~DQ7 DQ8~DQ14 DQ15
High High High High DOUT High DOUT High High High High DOUT DOUT High High High High High DOUT DOUT High
CURRENT
ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1
Write (word mode)
NOTES: means VIH; means VIL; means don't care (Must state) 48BGA ignore BYTE condition.
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG IOUT
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
RATING
-0.5(2) 4.6V +125 +150
RANG
Industrial
AMBIENT TEMPERATURE
-40OC 85OC
1.65V 3.6V
CAPACITANCE
1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. -2.0V case pulse width less than Input Capacitance Input/Output Capacitance VI/O
This parameter guaranteed 100% tested.
ELECTRICAL CHARACTERISTICS
PARAMETER NAME PARAMETER
Power Supply
VCC=1.8V
TEST CONDITIONS
MIN.
1.65 -0.3(2)
TYP.(1)
MAX.
UNITS
Input Voltage
VCC=3.6V VCC=1.8V
Input High Voltage
VCC=3.6V
VCC+0.3(3)
Input Leakage Current
VCC, VI/O Max, 0.2mA Max, 2.0mA
VCC=1.8V
Output Leakage Current
ICC1 ICCSB ICCSB1
Output Voltage
-VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current
Min, -0.1mA Min, -1.0mA VIH, 0mA, FMAX(4)
VCC-0.2
VCC=3.6V VCC=1.8V
VIH, 0mA, 1MHz VIH, VIL,
-VCC=3.6V VCC=1.8V
-VCC=3.6V VCC=1.8V
-4.0 5.0(5)
Standby Current CMOS
CE1VCC-0.2V CE20.2V, VINV CC-0.2V VIN0.2V
-VCC=3.6V
Typical characteristics TA=25OC 100% tested. Undershoot: -1.0V case pulse width less than Overshoot: VCC+1.0V case pulse width less than FMAX=1/tRC. VCC=3.0V R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
DATA RETENTION CHARACTERISTICS
SYMBOL ICCDR tCDR PARAMETER
Data Retention
TEST CONDITIONS
CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V
VCC=1.2V
MIN.
TYP.
MAX.
UNITS
Data Retention Current Chip Deselect Data Retention Time
Retention Waveform
Operation Recovery Time
Typical characteristics TA=25OC 100% tested. Read Cycle Time.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
VDR1.0V
tCDR
CE1VCC 0.2V
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode VDR1.0V
tCDR
CE20.2V
TEST CONDITIONS
(Test Load Input/Output Reference) Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1, tCHZ2, tBDO, tOHZ, tWHZ, Output Load Others 1V/ns 0.5Vcc 5pF+1TTL 30pF+1TTL INPUT PULSES Output CL(1)
SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST STEADY CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED DOES APPLY OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOW CENTER LINE HIGH INPEDANCE "OFF" STATE
Rise Time: 1V/ns
Fall Time: 1V/ns
Including scope capacitance.
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
BYTE FUNCTION
PARAMETER NAME
BYTE Setup Time BYTE Recovery Time
PARAMETER
MIN.
MAX.
UNITS
BYTE
ELECTRICAL CHARACTERISTICS READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME 55ns DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable Output Valid Chip Select Output Chip Select Output Data Byte Control Output Output Enable Output Chip Deselect Output High Chip Deselect Output High (CE1) (CE2) (CE1) (CE2) (LB, (CE1) (CE2) (LB, MIN. TYP. -MAX. -CYCLE TIME 70ns MIN. TYP. -MAX. -UNITS
tAVAX tAVQX tE1LQV tE2LQV tBLQV tGLQV tE1LQX tE2LQX tBLQX tGLQX tE1HQZ tE2HQZ tBHQZ tGHQZ tAVQX
tACS1 tACS2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tBDO tOHZ
Data Byte Control Output High (LB, Output Disable Output High Data Hold from Address Change
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE
(1,2,4)
ADDRESS DOUT
(1,3,4)
READ CYCLE
tACS1 tCLZ DOUT
tACS2
(5,6)
tCHZ
READ CYCLE
ADDRESS tCLZ1 tCLZ2
tOLZ tACS1 tOHZ tCHZ
(1,5)
tACS2
tCHZ2 tBDO
(2,5)
DOUT
NOTES: high read Cycle. Device continuously selected when CE2= VIH. Address valid prior coincident with transition and/or transition high. VIL. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
ELECTRICAL CHARACTERISTICS WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Address Time Address Valid Write Chip Select Write Data Byte Control Write Write Pulse Width Write Recovery Time Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE1, (CE2) (LB, CYCLE TIME 55ns MIN. TYP. -MAX. -CYCLE TIME 70ns MIN. TYP. -MAX. UNITS
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWR1 tWR2 tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE
ADDRESS
(11)
tWR1
tOHZ DOUT
(4,10)
(11)
tWR2
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
WRITE CYCLE ADDRESS
(11) (1,6)
(12)
(11)
tWHZ DOUT
(4,10)
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap active low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high going write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition high transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously VIL). DOUT same phase write data this write cycle. DOUT read data next address. high during this period, pins output state. Then data input signals opposite phase outputs must applied them. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. measured from later going going high write.
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
ORDERING INFORMATION
BH616UV1611
SPEED 55ns 70ns MATERIAL Normal Green, RoHS Compliant free, RoHS Compliant GRADE -40oC +85oC
PACKAGE Dice BGA-48-0810 TSOP I-48
Note: Brilliance Semiconductor Inc. (BSI) assumes responsibility application product circuit described herein. does authorize products critical components application which failure product expected result significant injury death, including life-support systems critical medical instruments.
PACKAGE DIMENSIONS
0.25 0.05
NOTES: CONTROLLING DIMENSIONS MILLIMETERS. PIN#1 MARKING LASER PRINT. SYMBOL NUMBER SOLDER BALLS.
Max.
SIDE VIEW
10.0 5.25 3.75 0.75
SOLDER BALL
0.35 0.05
VIEW
mini-BGA 10mm)
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
PACKAGE DIMENSIONS
TSOP I-48 (12mm 20mm)
R0201-BH616UV1611
Revision Otc. 2006
BH616UV1611
Revision History Revision History Initial Production Version Change I-grade operation temperature range from -25OC -40OC Part Number 70ns DICE form TSOP-I package type Change package dimension single chip solution form 8x10mm Improve Spec. ICC(MAX.) from 12mA 10mA VCC=3.6V ICCsb1(TYP.) from 5.0uA 4.0uA VCC=1.8V ICCDR(TYP.) from 2.5uA 1.5uA VCC=1.2V tOE(MIN.) from 30ns 25ns tAW(MIN.) from 45ns 40ns tCW(MIN.) from 45ns 40ns tBW(MIN.) from 45ns 40ns Draft Date 10,2006 2006 Remark Initial
July 2006 2006
R0201-BH616UV1611
Revision Otc. 2006
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