BH62UV4000 Wide operation voltage 1.65V 3.6V Ultra power consumpt
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Ultra Power/High Speed CMOS SRAM 512K
BH62UV4000
Wide operation voltage 1.65V 3.6V Ultra power consumption 3.6V Operation current 10mA (Max.)at 55ns (Max.) 1MHz Standby current 2.0uA (Typ.) 3.0V/25OC 1.2V Data retention current 1.0uA 25OC High speed access time 55ns (Max.) VCC=1.65~3.6V Automatic power down when chip deselected Easy expansion with options Three state outputs compatible Fully static operation, clock, refresh Data retention supply voltage 1.0V
DESCRIPTION
BH62UV4000 high performance, ultra power CMOS Static Random Access Memory organized 524,288 bits operates wide range 1.65V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical operating current 1.5mA 1MHz 3.6V/25OC maximum access time 55ns 1.65V/85OC. Easy memory expansion provided active chip enable (CE) active output enable (OE) three-state output drivers. BH62UV4000 automatic power down feature, reducing power consumption significantly when chip deselected. BH62UV4000 available DICE form, JEDEC standard 450mil Plastic SOP, 400mil TSOP-II, 600mil Plastic DIP, 8mmx13.4mm STSOP, 8mmx20mm TSOP 36-ball package.
POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY
BH62UV4000DI BH62UV4000EI BH62UV4000HI BH62UV4000PI BH62UV4000SI BH62UV4000STI BH62UV4000TI Industrial -40OC +85OC 10uA 10uA 10mA 1.5mA
OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
TYPE
VCC=1.8V 10MHz fMax.
VCC=3.6V
VCC=1.8V
VCC=3.6V 1MHz 10MHz fMax. 1MHz
DICE TSOP-II BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32
CONFIGURATIONS
BLOCK DIAGRAM
BH62UV4000STI BH62UV4000TI
Address Input Buffer
Decoder
1024
Memory Array
1024 4096
4096
BH62UV4000EI BH62UV4000PI BH62UV4000SI
Data Input Buffer
Column Write Driver Sense Column Decoder
Data Output Buffer
Control
Address Input Buffer
36-ball view
Brilliance Semiconductor, Inc. reserves right change products specifications without notice.
Detailed product characteristic test report available upon request being accepted.
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
DESCRIPTIONS
Name
A0-A18 Address Input Chip Enable Input
Function
These address inputs select 524,288
active LOW. Chip enable must active when data read from write device. chip enable active, device deselected standby power mode. pins will high impedance state when device deselected. write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location. output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impendence state when inactive. bi-directional ports used read data from write data into RAM.
Write Enable Input
Output Enable Input
DQ0-DQ7 Data Input/Output Ports
Power Supply Ground
TRUTH TABLE MODE
Chip De-selected (Power Down) Output Disabled Read Write
OPERATION
High High DOUT
CURRENT
ICCSB, ICCSB1
NOTES: means VIH; means VIL; means don't care (Must state)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG IOUT
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
RATING
-0.5(2) 4.6V +125 +150
RANG
Industrial
AMBIENT TEMPERATURE
-40OC 85OC
1.65V 3.6V
CAPACITANCE
1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. -2.0V case pulse width less than R0201-BH62UV4000 Input Capacitance Input/Output Capacitance VI/O
This parameter guaranteed 100% tested.
Revision Aug. 2006
BH62UV4000
ELECTRICAL CHARACTERISTICS
PARAMETER NAME ICC1 ICCSB ICCSB1 PARAMETER
Power Supply Input Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current Standby Current CMOS VCC, VI/O Max, 0.1mA Max, 2.0mA Min, -0.1mA Min, -1.0mA VIL, 0mA, FMAX(4) VIL, 0mA, 1MHz VIH, CEVCC-0.2V, VINV CC-0.2V VIN0.2V
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
TEST CONDITIONS
MIN.
1.65 -0.3(2) -VCC-0.2
TYP.(1)
-1.0 -2.0 2.0(5)
MAX.
VCC+0.3(3)
UNITS
Typical characteristics TA=25OC 100% tested. Undershoot: -1.0V case pulse width less than Overshoot: VCC+1.0V case pulse width less than FMAX=1/tRC. VCC=3.0V
DATA RETENTION CHARACTERISTICS
SYMBOL ICCDR tCDR PARAMETER
Data Retention Data Retention Current Chip Deselect Data Retention Time Operation Recovery Time
TEST CONDITIONS
CEVCC-0.2V, VINVCC-0.2V VIN0.2V CEVCC-0.2V, VINVCC-0.2V VIN0.2V
VCC=1.2V
MIN.
TYP.
-1.0
MAX.
-5.0
UNITS
Retention Waveform
Typical characteristics TA=25OC 100% tested. Read Cycle Time.
DATA RETENTION WAVEFORM Controlled)
Data Retention Mode
VDR1.0V
tCDR
CEVCC 0.2V
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
TEST CONDITIONS
(Test Load Input/Output Reference) Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tWHZ, Output Load Others 1V/ns 0.5Vcc 5pF+1TTL 30pF+1TTL INPUT PULSES Output CL(1)
SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST STEADY CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED DOES APPLY OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOW CENTER LINE HIGH INPEDANCE "OFF" STATE
Rise Time: 1V/ns
Fall Time: 1V/ns
Including scope capacitance.
ELECTRICAL CHARACTERISTICS READ CYCLE
JEDEC PARAMETER NAME PARANETER NAME CYCLE TIME 55ns DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Output Enable Output Valid Chip Select Output Output Enable Output Chip Select Output High Output Enable Output High Data Hold from Address Change MIN. TYP. -MAX. -UNITS
tAVAX tAVQX tE1LQV tGLQV tE1LQX tGLQX tE1HQZ tGHQZ tAVQX
tACS tCLZ tOLZ tCHZ tOHZ
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE
(1,2,4)
ADDRESS DOUT
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
READ CYCLE
(1,3,4)
tACS tCLZ DOUT
tCHZ
READ CYCLE
ADDRESS
tOLZ tACS tCLZ tOHZ tCHZ
(1,5)
DOUT
NOTES: high read Cycle. Device continuously selected when Address valid prior coincident with transition and/or transition high. VIL. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested.
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
ELECTRICAL CHARACTERISTICS WRITE CYCLE
JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION Write Cycle Time Address Time Address Valid Write Chip Select Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE, CYCLE TIME 55ns MIN. TYP. -MAX. UNITS
tAVAX tAVWL tAVWH tELWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE
ADDRESS
(11)
tOHZ DOUT
(4,10)
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
WRITE CYCLE
(1,6)
ADDRESS
(11)
tWHZ DOUT
(4,10)
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously VIL). DOUT same phase write data this write cycle. DOUT read data next address. during this period, pins output state. Then data input signals opposite phase outputs must applied them. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. measured from later going write.
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
ORDERING INFORMATION
BH62UV4000
SPEED 55ns
MATERIAL Normal Green, RoHS Compliant
GRADE -40oC +85oC PACKAGE DICE TSOP-II BGA-36-0608 PDIP Small TSOP (8mm 13.4mm) TSOP (8mm 20mm)
Note: Brilliance Semiconductor Inc. (BSI) assumes responsibility application product circuit described herein. does authorize products critical components application which failure product expected result significant injury death, including life-support systems critical medical instruments.
PACKAGE DIMENSIONS
WITH PLATING
BASE METAL
SECTION
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
PACKAGE DIMENSIONS (continued)
STSOP
TSOP
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
PACKAGE DIMENSIONS (continued)
PDIP
NOTES CONTROLLING DIMENSIONS MILLIMETERS. PIN#1 MARKING LASER PRINT. SYMBOL NUMBER SOLDER BALLS.
Max.
BALL PITCH 0.75 5.25 3.75
VIEW
mini-BGA 8mm)
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
PACKAGE DIMENSIONS (continued)
DIMENSION (MM) MIN.
DIMENSION (INCH) MAX.
1.20
NOM.
MIN.
NOM.
MAX.
0.047
0.05 0.95 0.30 0.30 0.12 0.10 20.82 11.56 10.03
0.10 1.00 0.40 0.127 20.95 11.76 10.16 1.27 BASIC
0.15 1.05 0.52 0.45 0.21 0.16 21.08 11.96 10.29
0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394
0.004 0.039 0.016 0.005 0.825 0.463 0.400 0.050 BASIC
0.006 0.042 0.020 0.018 0.008 0.006 0.830 0.471 0.405
0.20
0.40
0.50 0.25 BASIC
0.60
0.016
0.020 0.010 BASIC 0.031
0.024
0.12 0.12
0.25
0.005 0.005 0.037
0.010
0.95 0.10
SEATING PLANE
0.004
0.44
GAGE PLANE
WITH PLATING
BASE METAL
NOTE: CONTROLLING DIMENSION MILLIMETERS. REFREENCE DOCUMENT JEDEC MS-024 DIMENSION DOES INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL EXCEED 0.15(0.006") SIDE. DIMENSION DOES INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL EXCEED 0.25(0.01") SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDER THAN DIMENSION MORE THAN 0.13mm DAMBAR INTRUSION SHALL CAUSE LEAD NARROWER THAN DIMENSION MORE THAN 0.07mm.
DETAIL
0.44
SECTION
TSOP
R0201-BH62UV4000
Revision Aug. 2006
BH62UV4000
Revision History Revision History Initial Production Version Change I-grade operation temperature range from -25OC -40OC PDIP package type TSOP-II package type 36-ball package type Improve spec. from 12mA 10mA Draft Date Dec. 21,2005 May. 2006 Remark Initial
Aug. 2006
R0201-BH62UV4000
Revision Aug. 2006
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