Data Sheet December 2007 FN6383.1 Triple, 180° Out-of-Phase, Step

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Data Sheet December 2007 FN6383.1 Triple, 180° Out-of-Phase, Step

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ISL9440, ISL9440A, ISL9441
Data Sheet December 2007 FN6383.1
Triple, 180° Out-of-Phase, Step-Down Single Linear Controller
ISL9440, ISL9440A ISL9441 quad-output synchronous buck controllers that integrate controllers drop-out linear regulator controller, which full featured designed provide multi-rail power products such cable satellite set-top boxes, VoIP gateways, cable modems, other home connectivity products well variety industrial general purpose applications. Each output adjustable down 0.8V. PWMs synchronized 180° phase thus reducing input current ripple voltage. ISL9440, ISL9440A ISL9441 offer internal soft-start, independent enable inputs ease supply rail sequencing, integrated UV/OV/OC/OT protections space conscious 5mmx5mm package. ISL9440 ISL9440A offer early warning function output logic signal warn system back data when input voltage falls below certain level. ISL9440, ISL9440A ISL9441 utilize internal loop compensation keep minimum peripheral components compact design total solution cost. These devices implemented with current mode control with feed forward cover various applications even with fixed internal compensations. table below shows difference terms ISL9440, ISL9440A ISL9441 features.
PART NUMBER ISL9440 ISL9440A ISL9441 EARLY WARNING SWITCHING FREQUENCY (kHz)
Features
Three Integrated Synchronous Buck Controllers Internal Bootstrap Diodes Internal Compensation Internal Soft-Start Independent Control Each Regulator Programmable Output Voltages; Independent Enable/Shutdown Fixed Switching Frequency: 300kHz (ISL9440, ISL9441); 600kHz (ISL9440A) Adaptive Shoot Through Protection Synchronous Buck Controllers Independently Programmable Voltage Outputs Out-of-Phase Switching Reduce Input Capacitance (0°/180°/0°) External Current Sense Resistor Uses Lower MOSFET's rDS(ON) Current Mode Controller with Voltage Feed Forward Complete Protection Overcurrent, Overvoltage, Undervoltage Lockout, Over-Temperature Cycle Cycle Current Limiting Wide Input Voltage Range Input Rail Powers Pin: 5.6V Input Rail Powers VCC_5V (VIN tied VCC_5V, input applications): 4.5V 5.6V Early Warning (ISL9440, ISL9440A) Input Voltage Failure Integrated Reset Function (ISL9440, ISL9440A) Pb-free (RoHS compliant)
Applications
Satellite Cable Set-Top Boxes Cable Modems Gateway Devices NAS/SAN Devices
Related Literature
Technical Brief TB389 "PCB Land Pattern Design Surface Mount Guidelines (MLFP) Packages"
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. Rights Reserved other trademarks mentioned property their respective owners.
ISL9440, ISL9440A, ISL9441 Ordering Information
PART NUMBER (Note) ISL9440IRZ* PART MARKING ISL9440IRZ TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG.
PHASE1
Pinout
ISL9440, ISL9440A, ISL9441 QFN) VIEW
PHASE2 ISEN2 PGND LGATE3 UGATE3 BOOT3 PHASE3 ISEN3 LDOFB SGND OCSET2 OCSET3
FN6383.1 December 2007
UGATE1
BOOT1
ISL9440AIRZ* 9440AIRZ ISL9441IRZ* ISL9441IRZ
L32.5x5B L32.5x5B
ISEN1 PGOOD VCC_5V OCSET1
*Add "-T" tape reel. Please refer TB347 details reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate PLUS ANNEAL termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
BOOT2
L32.5x5B
UGATE2
LGATE1
LGATE2
Block Diagram
BOOT1 VCC_5V UGATE1 PHASE1 ADAPTIVE DEAD-TIME VCC_5V LGATE1 PGND ENABLE BIAS SUPPLIES 0.8V REFERENCE
gm*VE
PGOOD
VCC_5V PGND
VCC_5V
BOOT2 UGATE2 PHASE2 ADAPTIVE DEAD-TIME SAMPLE TIMING VCC_5V LGATE2
SAMPLE TIMING
180k 0.8V ISEN1 CURRENT SAMPLE OCSET1
PGND BOOT3 VCC_5V UGATE3
REFERENCE FAULT LATCH
SOFT-START EARLY WARNING (see note ADAPTIVE DEAD-TIME SAMPLE TIMING
PHASE3
VCC_5V LGATE3
1400k
18.5pF
PGOOD
PGND
ERROR
PWM1
UV/OV
PWM3
ISEN3
OCSET3 DUTY CYCLE RAMP GENERATOR CHANNEL PHASE CONTROL PWM2
CHANNEL
CURRENT SAMPLE
1.75V REFERENCE
ISEN2
FN6383.1 December 2007
SAME STATE CLOCK CYCLES REQUIRED LATCH OVERCURRENT FAULT
OCSET2
CHANNEL
SGND VCC_5V
CHANNEL
ISL9440, ISL9440A, ISL9441 Typical Application ISL9440, ISL9441
+12V 4.7µF 10µF 0.1µF BOOT1 VCC_5V 10µF 0.1µF 56µF
BOOT2
UGATE1 PHASE1
UGATE2 PHASE2 ISEN2 8.45k
VOUT1 +2.5V, 330µF 330µF
3.3µH
8.45k
ISEN1
2.2µH 330µF 330µF
VOUT2 +1.5V, 4.02k
LGATE1
10.2k
IRF7907
LGATE2 IRF7907
4.75k 0.01µF
+12V ISL9440/ISL9441 BOOT3 0.1µF 4.53k
VOUT3
VOUT4 +3.3V, 500mA 68µF IRF7404
UGATE3 PHASE3 ISEN3 2.8k
LDOFB
15µH 330µF 24.3k
VOUT3 +5V, 2.2nF
4.75k OCSET1 OCSET2 OCSET3
LGATE3 VCC_5V VCC_5V PGOOD IRF7907
301k 301k 261k
4.53k
PGOOD
PGND SGND
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441 Typical Application ISL9440A
+12V 4.7µF 10µF 0.1µF BOOT1 VCC_5V 10µF 0.1µF 56µF
BOOT2
UGATE1 PHASE1
UGATE2 PHASE2 ISEN2 8.45k
VOUT1 +2.5V, 330µF 330µF
1.8µH
8.45k
ISEN1
1.2µH 330µF 330µF
VOUT2 +1.5V, 4.02k
LGATE1
10.2k
IRF7907
LGATE2 IRF7907
4.75k 0.01µF
+12V ISL9440A BOOT3 0.1µF 4.53k
VOUT3
VOUT4 +3.3V, 500mA 68µF IRF7404
UGATE3 PHASE3 ISEN3 2.8k
LDOFB
8.2µH 330µF 24.3k
VOUT3 +5V,
4.75k OCSET1 OCSET2 OCSET3
LGATE3 VCC_5V VCC_5V PGOOD IRF7907
301k 301k 261k
4.53k
PGOOD
PGND SGND
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Absolute Maximum Ratings
VCC_5V -0.3V VCC_5V Output Current 100mA -0.3V +28V BOOT/UGATE PHASE -0.3V VCC_5V 0.3V PHASE1,2,3 ISEN1, 2,3, .-5V (<100ns, 10µJ)/-0.3V (DC) +28V EN1,EN2, EN3, FB1, FB2, FB3, -0.3V VCC_5V 0.3V LDOFB, OCSET1, OCSET2, OCSET3, LGATE1, LGATE2, LGATE3, GND. -0.3V VCC_5V 0.3V PGOOD, RST, -0.3V Rating Human Body Model .2000V Machine Model .200V
Thermal Information
Thermal Resistance (Typical) JA(oC/W) JC(oC/W) Package (Note Maximum Junction Temperature .-55°C +150°C Maximum Operating Temperature .-40°C +85°C Maximum Storage Temperature. .-65°C +150°C Pb-free reflow profile .see link below
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTE: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, C_VCC_5V 4.7µF, -40°C +85°C (Note Typical values +25°C, unless otherwise specified. TEST CONDITIONS UNITS
PARAMETER SUPPLY Input Voltage Range Input Voltage Range VCC_5V SUPPLY (Note Operation Voltage Internal Output Voltage Maximum Supply Current Internal SUPPLY CURRENT Shutdown Current (Note Operating Current (Note REFERENCE SECTION Internal Reference Voltage Reference Voltage Accuracy CONTROLLER ERROR AMPLIFIERS Gain (Note Gain-BW Product (Note Slew Rate (Note REGULATOR Switching Frequency (ISL9440, ISL9441) Maximum Duty Cycle (ISL9440, ISL9441) Minimum Duty Cycle (ISL9440, ISL9441) Switching Frequency (ISL9440A) Maximum Duty Cycle (ISL9440A)
VCC_5V (Note
12.0
24.0
5.6V, 60mA
=12V
Across specified temperature range Across specified temperature range
V/µs
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, C_VCC_5V 4.7µF, -40°C +85°C (Note Typical values +25°C, unless otherwise specified. (Continued) TEST CONDITIONS 5.5V Ramp Offset Soft-start Period GATE DRIVER CHANNEL (UGATE1, LGATE (Note Source Current Sink Current Upper Drive Pull-Up Upper Drive Pull-Down Lower Drive Pull-Up Lower Drive Pull-Down Rise Time Fall Time GATE DRIVER CHANNEL (UGATE3; LGATE (Note Sink/Source Current Upper Drive Pull-Up Upper Drive Pull-Down Lower Drive Pull-Up Lower Drive Pull-Down Rise Time Fall Time DROP CONTROLLER Drive Sink Current Threshold Voltage Amplifier Trans-conductance LDOFB Input Leakage Current (Note ENABLE1, ENABLE2, ENABLE3 THRESHOLD Enable Logic Input Enable Logic Input High POWER GOOD MONITORS PGOOD Upper Threshold, PGOOD Lower Threshold, PGOOD Linear Controller PGOOD Level Voltage PGOOD Leakage Current I_SINK PGOOD 0.025 105.5 115.5 LDOFB 0.8V LDOFB 0.76V 21mA 0.800 VCC_5V 5.0V VCC_5V 5.0V VCC_5V 5.0V VCC_5V 5.0V COUT 1000pF COUT 1000pF VCC_5V 5.0V VCC_5V 5.0V VCC_5V 5.0V VCC_5V 5.0V COUT 1000pF COUT 1000pF 2000 0.667 UNITS
PARAMETER Minimum Duty Cycle (ISL9440A) Bias Current (Note Peak-to-Peak Saw-tooth Amplitude (Note
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, C_VCC_5V 4.7µF, -40°C +85°C (Note Typical values +25°C, unless otherwise specified. (Continued) TEST CONDITIONS RPULLUP 3.3V RPULLUP 3.3V 0.05 0.05 UNITS
PARAMETER PGOOD Rise Time PGOOD Fall Time EARLY WARNING FUNCTIONS Undervoltage Lockout Rising (VCC_5V Pin) Undervoltage Lockout Falling (VCC_5V Pin) Early Warning Voltage Rising (VIN Pin; ISL9440, ISL9440A only) Early Warning Voltage Falling (VIN Pin; ISL9440, ISL9440A only) Voltage Leakage Current Rise Time Fall Time PGOOD/RST TIMING RISING VIN/VOUT Rising Threshold PGOOD High Rising PGOOD Rising Rising PGOOD/RST TIMING FALLING VIN/VOUT Falling Threshold PGOOD Falling PGOOD Falling Falling OVER VOLTAGE PROTECTION Trip Point OVER CURRENT PROTECTION Overcurrent Threshold (OCSET_) (Note Full Scale Input Current (ISEN_) (Note Overcurrent Voltage (OCSET_) OVER-TEMPERATURE Over-Temperature Shutdown Over-Temperature Hysteresis NOTES:
4.25 3.95
4.45 4.20 5.75
4.50 4.40 5.90
5.30
5.55
I_SINK RPULLUP 3.3V RPULLUP 3.3V 0.025 0.05 0.05
ROCSET
1.70 1.75 1.80
normal operation, where device supplied with voltage pin, VCC_5V provides output capable 60mA (min). When VCC_5V used supply input, internal regulator disabled input must connected VCC_5V pin. (Refer Descriptions section more details.) This total shutdown current with 24V. Operating current supply current consumed when device active switching. does include gate drive current. Limits established characterization production tested. Check Note VCC_5V configurations ±10% input applications. ISL9440, ISL9440A's PGOOD signal will fall when voltage drops below 5.55V (TYP), which results from early warning detection voltage. ISL9441 doesn't have early warning function, when voltage below 5.55V, PGOOD will pulled LOW; ISL9441's PGOOD only shows output voltage regulation status.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441 Descriptions
BOOT3, BOOT2, BOOT1 (Pin
These pins bootstrap pins provide bias high side driver. bootstrap diodes integrated help reduce total cost reduce layout complexity.
(Pin
this power device with external supply voltage with range 5.6V 24V. ±10% operation, connect this VCC_5V. ISL9440 ISL9440A, voltage this monitored early warning function. voltage this drop below 5.55V, PGOOD will pulled low. will after PGOOD toggles 5.5µs (TYP). Refer Figure detailed time sequence. ISL9441 doesn't have early warning functions, which means voltage monitored.
UGATE3, UGATE2, UGATE1 (Pin
These pins provide gate drive upper MOSFETs.
PHASE3, PHASE2, PHASE1 (Pin
These pins connected junction upper MOSFET's source, output filter inductor, lower MOSFET's drain.
VCC_5V (Pin
This output internal linear regulator. This output supplies bias side gate drivers, external boot circuitry high side gate drivers. powered directly from single (±10%) supply this pin. When used supply input, this must externally connected VIN. VCC_5V must always decoupled power ground with minimum 4.7F ceramic capacitor, placed very close pin.
LGATE3, LGATE2, LGATE1 (Pin
These pins provide gate drive lower MOSFETs.
PGND (Pin
This provides power ground connection lower gate drivers PWM1, PWM2 PWM3. This should connected sources lower MOSFETs terminals external input capacitors.
FB3, FB2, FB1, LDOFB (Pin
These pins connected feedback resistor divider provide voltage feedback signals respective controller. They output voltage converter. addition, PGOOD circuit uses these inputs monitor output voltage status.
EN3, EN2, (Pin
These pins provide enable/disable function their respective output. output enabled when this floating pulled HIGH, disabled when pulled LOW.
ISEN3, ISEN2, ISEN1 (Pin
These pins used monitor voltage drop across lower MOSFET current loop feedback overcurrent protection.
(Pin
This open drain output linear regulator controller.
OCSET3, OCSET2, OCSET1 (Pin
resistor from this ground sets overcurrent threshold respective PWM.
PGOOD (Pin
This open drain logic output used indicate status output voltages input voltage (voltage pin; early warning ISL9440 ISL9440A). This pulled when either three outputs within respective nominal voltage, linear controller output less than it's nominal value, voltage drops below 5.55V. ISL9440 ISL9440A's PGOOD also indicates status early warning function. voltage drops below 5.55V, this will pulled low.
(Pin
Reset pulse output. This outputs logic signal after PGOOD toggles 5.5µs (TYP). used reset system. Refer Figure detailed time sequence ISL9440 ISL9440A with early warning function. ISL9441 doesn't have early warning functions, which means voltage monitored. still output signal following PGOOD LOW.
SGND (Pin
This small-signal ground, common controllers, suggested routed separately from high current ground (PGND). case whole solid ground noisy current going through around chip, SGND PGND tied same ground copper plane. voltage levels measured with respect this pin. small ceramic capacitor should connected right next this noise decoupling.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
VOLTAGE 6.5µs TIME (NOT SCALE) 100µs 2.4V 0.4V PGOOD 5.5V RISING/ 5.5V RISING/ VOUT REGULATION VOUT REGULATION 200ms
5.5V FALLING/ VOUT REGULATION
VIN/VOUT
FIGURE PGOOD TIMING
Typical Performance Curves
(Oscilloscope Plots Taken Using ISL9440EVAL1Z Evaluation Board, Unless Otherwise Noted.)
2.55 2.54 OUTPUT VOLTAGE 2.53 EFFICIENCY 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45
LOAD CURRENT
LOAD CURRENT
FIGURE PWM1 LOAD REGULATION
FIGURE PWM1 EFFICIENCY LOAD 2.5V), 12V, DUAL SO-8 MOSFET (IRF7907) UPPER LOWER MOSFETS
1.55 1.54 OUTPUT VOLTAGE 1.53 EFFICIENCY 1.52 1.51 1.50 1.49 1.48 1.47 1.46 1.45
LOAD CURRENT
LOAD CURRENT
FIGURE PWM2 LOAD REGULATION
FIGURE PWM2 EFFICIENCY LOAD 1.5V), 12V, DUAL SO-8 MOSFET (IRF7907) UPPER LOWER MOSFETS
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441 Typical Performance Curves
5.10 5.10 OUTPUT VOLTAGE 5.09 EFFICIENCY 5.09 5.08 5.08 5.07 5.07 5.06 5.06 5.05 LOAD CURRENT LOAD CURRENT
(Continued)
(Oscilloscope Plots Taken Using ISL9440EVAL1Z Evaluation Board, Unless Otherwise Noted.)
FIGURE PWM3 LOAD REGULATION
FIGURE PWM3 EFFICIENCY LOAD 5V), 12V, DUAL SO-8 MOSFET (IRF7907) UPPER LOWER MOSFETS
VOUT1 50mV/DIV, COUPLED
VOUT3 1V/DIV
VOUT2 50mV/DIV, COUPLED
VOUT4 (LDO) 1V/DIV
VOUT3 50mV/DIV, COUPLED
VOUT1 1V/DIV
VOUT2 1V/DIV
VOUT4 50mV/DIV, COUPLED
0.2ms/DIV
5µs/DIV
FIGURE SOFT-START WAVEFORMS
FIGURE OUTPUT RIPPLE UNDER MAXIMUM LOAD (IO1 0.5A)
VIN, 1V/DIV, VIN, 1V/DIV,
RST, 5V/DIV, RST, 5V/DIV,
PGOOD, 5V/DIV, 100µs/DIV 10µs/DIV
PGOOD, 5V/DIV,
FIGURE FALLING PGOOD FALLING DELAY TIME
FIGURE PGOOD FALLING FALLING
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441 Typical Performance Curves
(Continued)
(Oscilloscope Plots Taken Using ISL9440EVAL1Z Evaluation Board, Unless Otherwise Noted.)
VOUT1, 100mV/DIV, 1.6A/µs
VIN, 1V/DIV,
VOUT2, 100mV/DIV, 1.6A/µs
RST, 1V/DIV,
VOUT3, 100mV/DIV, 1A/µs
PGOOD, 5V/DIV,
VOUT4 (LDO), 100mV/DIV, 0.5A, 1A/µs
500ns/DIV
500µs/DIV
FIGURE PGOOD RISING RISING
FIGURE OUTPUT RIPPLE UNDER TRANSIENT LOAD
PWM1, 5V/DIV
Vo1, 1V/DIV
PWM2, 5V/DIV
Vo2, 1V/DIV
Vo3, 1V/DIV 5ms/DIV
PWM3, 5V/DIV 1µs/DIV
FIGURE THREE CHANNEL HARD-SHORT SAME TIME
FIGURE PHASE NODE WAVEFORMS,
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441 Functional Description
General Description
ISL9440, ISL9440A ISL9441 integrate control circuits three synchronous buck converters linear controller. three synchronous bucks operate phase substantially reduce input ripple thus reduce input filter requirements. chip control lines (EN1, EN3), which provide independent control each synchronous buck outputs. buck controllers employ free-running frequency 300kHz (ISL9440 ISL9441) 600kHz (ISL9440A). current mode control scheme with input voltage feedforward ramp input modulator provides excellent rejection input voltage variations provides simplified loop compensations. linear controller drive either PFET provide ultra low-dropout regulation with programmable voltages. start done four outputs regulations.
Output Voltage Programming
ISL9440, ISL9440A ISL9441 precision internal reference voltage output voltage. Based this internal reference, output voltage thus from 0.8V level determined input voltage, maximum duty cycle, conversion efficiency circuit. resistive divider from output ground sets output voltage either channel. center point divider shall connected pin. output voltage value determined Equation
OUTx 0.8V (EQ.
where resistor feedback divider network resistor connected from ground.
Internal Linear Regulator (VCC_5V)
ISL9440, ISL9440A ISL9441 functions internally powered from on-chip, dropout regulator. maximum regulator input voltage 24V. Bypass regulator's output (VCC_5V) with 4.7µF capacitor ground. dropout voltage this typically 600mV, when greater than 5.6V, VCC_5V typically ISL9440, ISL9440A ISL9441 also employ undervoltage lockout circuit that disables both regulators when VCC_5V falls below 4.4V. internal source over 60mA supply power side gate drivers charge external boot capacitor. When driving large FETs especially 300kHz (ISL9440, ISL9441)/600kHz (ISL9440A) frequency, little regulator current available external loads. example, single large with 15nC total gate charge requires 15nC 300kHz 4.5mA (15nC 600kHz 9mA). Also, higher input voltages with larger FETs, power dissipation across internal will increase. Excessive dissipation across this regulator must avoided prevent junction temperature rise. Larger FETs used with ±10% input applications. thermal overload protection circuit will triggered, VCC_5V output short-circuit. Connect VCC_5V ±10% input applications.
Out-of-Phase Operation
reduce input ripple current, Channel Channel operate 180° out-of-phase, Channel keeps phase degree with Channel Channel Channel typically output higher load compared Channel because their stronger drivers. This reduces input capacitor ripple current requirements, reduces power supply-induced noise, improves EMI. This effectively helps lower component cost, save board space reduce EMI. Triple PWMs typically operate in-phase turn both upper FETs same time. input capacitor must then support instantaneous current requirements three switching regulators simultaneously, resulting increased ripple voltage current. higher ripple current lowers efficiency power loss associated with input capacitor. This typically requires more low-ESR capacitors parallel minimize input voltage ripple ESR-related losses, meet required ripple current rating. With synchronized out-of-phase operation, high-side MOSFETs turn 180° out-of-phase. instantaneous input current peaks both regulators longer overlap, resulting reduced ripple current input voltage ripple. This reduces required input capacitor ripple current rating, allowing fewer less expensive capacitors, reducing shielding requirements EMI. typical operating curves show synchronized 180° out-of-phase operation.
Digital Enable Signals
typical applications ISL9440, ISL9440A ISL9441 using digital sequencing controllers power rails. Using digital enable rather than analog softstart provides well controlled method sequencing down power rails.
Input Voltage Range
ISL9440, ISL9440A ISL9441 designed operate from input supplies ranging from 4.5V 24V. ±10% input applications, ISL9441 suggested. reason that VCC_5V should tied together this input application. early warning function will pull PGOOD ISL9440 ISL9440A. ISL9441 been implemented with early warning function.
FN6383.1 December 2007
Soft-Start Operation
ISL9440, ISL9440A ISL9441 have fixed soft-start time, 1.7ms (TYP). PGOOD will toggle high until soft-
ISL9440, ISL9440A, ISL9441
input voltage range effectively limited available maximum duty cycle (DMAX ISL9440 ISL9441, DMAX ISL9440A).
0.93 (EQ.
BOOT UGATE PHASE
VCC_5V
where, parasitic voltage drops inductor discharge path, including lower FET, inductor board. voltage drops charging path, including upper FET, inductor board resistances. maximum input voltage minimum output voltage limited minimum on-time (tON(min)).
300kHz (EQ.
ISL9440, ISL9440A, ISL9441
FIGURE
where, tON(min) 30ns
Gate Control Logic
gate control logic translates generated signals into gate drive signals providing amplification, level shifting shoot-through protection. gate drivers have some circuitry that helps optimize performance over wide range operational conditions. MOSFET switching times vary dramatically from type type with input voltage, gate control logic provides adaptive dead time monitoring real gate waveforms both upper lower MOSFETs. Shoot-through control logic provides 20ns dead-time ensure that both upper lower MOSFETs will turn simultaneously cause shoot-through condition.
start-up, low-side MOSFET turns forces PHASE ground order charge BOOT capacitor After low-side MOSFET turns off, high-side MOSFET turned closing internal switch between BOOT UGATE. This provides necessary gate-tosource voltage turn upper MOSFET, action that boosts gate drive signal above VIN. current required drive upper MOSFET drawn from internal regulator.
Adaptive Dead Time
ISL9440, ISL9440A ISL9441 incorporate adaptive dead time algorithm synchronous buck controllers that optimizes operation with varying MOSFET conditions. This algorithm provides approximately 20ns dead time between switching upper lower MOSFET's. This dead time adaptive allows operation with different MOSFET's without having externally adjust dead time using resistor capacitor. During turn-off lower MOSFET, LGATE voltage monitored until reaches threshold, which time UGATE released rise. Adaptive dead time circuitry monitors upper MOSFET gate voltage during UGATE turn-off. Once upper MOSFET gate-to-source voltage dropped below threshold LGATE allowed rise.
Gate Drivers
low-side gate driver supplied from VCC_5V provides peak sink current 2A/2A/200mA source current 800mA/800mA/400mA Channels 1/2/3 respectively. high-side gate driver also capable delivering same current those low-side gate driver. Gate-drive voltages upper N-Channel MOSFET generated flying capacitor boot circuit. boot capacitor connected from BOOT PHASE node provides power high side MOSFET driver. limit peak current external resistor placed between UGATE gate external MOSFET. This small series resistor also damps oscillations caused resonant tank parasitic inductances traces board FET's input capacitance.
Internal Bootstrap Diode
ISL9440, ISL9440A ISL9441 have integrated bootstrap diodes help reduce total cost reduce layout complexity. Simply adding external capacitor across BOOT PHASE pins completes bootstrap circuit. bootstrap capacitor must have maximum voltage rating above maximum battery voltage plus bootstrap capacitor chosen from Equation
GATE BOOT BOOT (EQ.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Where QGATE amount gate charge required fully charge gate upper MOSFET. VBOOT term defined allowable droop rail upper drive. example, suppose upper MOSFET gate charge (QGATE) 25nC also assume droop drive voltage over cycle 200mV. will find that bootstrap capacitance least 0.125µF required. next larger standard value capacitance 0.22µF. good quality ceramic capacitor recommended.
Overvoltage Protection
switching controllers within ISL9440, ISL9440A ISL9441 have fixed overvoltage points. overvoltage point 118% output voltage feedback resistors. case overvoltage event, will attempt bring output voltage back into regulation keeping upper MOSFET turned modulating lower MOSFET consecutive cycles. overvoltage condition been corrected cycles, ISL9440, ISL9440A ISL9441 will turn lower MOSFET until overvoltage been cleared, power path interrupted opening fuse.
Protection Circuits
converter output monitored protected against overload, short circuit undervoltage conditions. sustained overload output sets PGOOD initiates hiccup mode.
Over-Temperature Protection
incorporates over-temperature protection circuit that shuts down when temperature +150°C reached. Normal operation resumes when temperatures drops below +130°C through initiation full soft-start cycle.
Undervoltage Lockout
ISL9440, ISL9440A ISL9441 include UVLO protection that will keep devices reset condition until proper operating voltage applied that will also shut down ISL9440, ISL9440A ISL9441 operating voltage drops below pre-defined value. controllers disabled when UVLO asserted. When UVLO asserted, PGOOD will valid de-asserted.
Feedback Loop Compensation
reduce number external components simplify process determining compensation components, controllers have internally compensated error amplifiers. make internal compensation possible several design measures were taken. First, ramp signal applied comparator proportional input voltage provided pin. This keeps modulator gain constant with variation input voltage. Second, load current proportional signal derived from voltage drop across lower MOSFET during time interval subtracted from amplified error signal comparator input. This creates internal current control loop. resistor connected ISEN sets gain current feedback loop. following expression estimates required value current sense resistor depending maximum operating load current value MOSFET's rDS(ON).
-15A (EQ.
Overcurrent Protection
controllers lower MOSFET's on-resistance, rDS(ON) monitor current converter. sensed voltage drop compared with threshold resistor connected from OCSETx ground.
OCSET (EQ.
where, desired overcurrent protection threshold, value current sense resistor connected ISENx pin. overcurrent detected consecutive clock cycles then enters hiccup mode turning gate drivers entering into soft-start. will cycle times through soft-start before trying restart. will continue cycle through soft-start until overcurrent condition removed. Hiccup mode active during soft-start care must taken ensure that peak inductor current does exceed overcurrent threshold during soft-start. Because nature this current sensing technique, accommodate wide range rDS(ON) variations, value overcurrent threshold should represent overload current about 150% 180% maximum operating current. more accurate current protection desired, place current sense resistor series with lower MOSFET source.
Choosing provide 15µA current current sample hold circuitry recommended values down 100µA used. higher sampling current will help stabilize loop. current loop feedback, modulator single pole response with -20dB slope frequency determined load.
(EQ.
where load resistance load capacitance. this type modulator, Type compensation circuit usually sufficient.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Figure shows Type amplifier response along with responses current mode modulator converter. Type amplifier, addition pole origin, zero-pole pair that causes flat gain region frequencies between zero pole.
6kHz 600kHz
CONVERTER TYPE 17.5dB
MODULATOR
(EQ.
input, controller sinks 21mA current. external transistor PFET pass element used. dominant pole loop placed base gate PFET), capacitor from emitter base (source gate PFET). Better load transient response achieved however, dominant pole placed output, with capacitor ground output regulator. Under no-load conditions, leakage currents from pass transistors supply output capacitors, even when transistor off. Generally this problem since feedback resistor drains excess charge. However, charge build output capacitor making VLDO rise above point. Care must taken insure that feedback resistor's current exceeds pass transistors leakage current over entire temperature range. linear regulator output supplied output PWMs. When using PFET, output linear regulator will track supply after output rises voltage greater than threshold PFET pass device. voltage differential between linear output will load current times rDS(ON).
(EQ.
18dB
ERROR AMPLIFIER SINK CURRENT (mA)
FIGURE FEEDBACK LOOP COMPENSATION
0.79
zero frequency, amplifier high-frequency gain, modulator gain chosen satisfy most typical applications. crossover frequency will appear point where modulator attenuation equals amplifier high frequency gain. only task that system designer complete specify output filter capacitors position load main pole somewhere within decade lower than amplifier zero frequency. With this type compensation plenty phase margin easily achieved zero-pole pair phase `boost'. Conditional stability occur only when main load pole positioned much left side frequency axis excessive output filter capacitance. this case, zero placed within 1.2kHz 30kHz range gives some additional phase `boost'. Some phase boost also achieved connecting capacitor parallel with upper resistor divider that sets output voltage value. Please refer "Output Inductor Selection" page "Input Capacitor Selection" page further details.
0.82 0.83 0.81 FEEDBACK VOLTAGE
0.84
0.85
FIGURE LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
high-impedance base driver susceptible system noise, especially when linear regulator lightly loaded. Capacitively coupled switching noise inductively coupled onto base drive causes fluctuations base current, which appear noise linear regulator's output. Keep base drive traces away from step-down converter, short possible, minimize noise coupling. resistor series with gate drivers reduces switching noise generated PWM. Additionally, bypass capacitor placed across base-to-emitter resistor. This bypass capacitor, addition transistor's input capacitor, could bring second pole that will destabilize linear regulator. Therefore, stability
Linear Regulator
linear regulator controller trans-conductance amplifier with nominal gain 2A/V. N-channel MOSFET output device sink minimum 50mA. reference voltage 0.8V. With zero volts differential it's
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
requirements determine maximum base-to-emitter capacitance. output capacitors should placed close load possible. short wide copper regions connect output capacitors load avoid inductance resistances. copper filled polygons wide short trace connect junction upper FET, Lower output inductor. Also keep PHASE node connection short. unnecessarily oversize copper islands PHASE node. Since phase nodes subjected very high dv/dt voltages, stray capacitor formed between these islands surrounding circuitry will tend couple switching noise. Route high speed switching nodes away from control circuitry. Create separate small analog ground plane near Connect SGND this plane. small signal grounding paths including feedback resistors, current limit setting resistors pull-down resistors should connected this SGND plane. Ensure feedback connection output capacitor short direct.
Layout Guidelines
Careful attention layout requirements necessary successful implementation ISL9440, ISL9440A ISL9441 based DC/DC converter. ISL9440, ISL9440A ISL9441 switch very high frequency therefore switching times very short. these switching frequencies, even shortest trace significant impedance. Also, peak gate drive current rises significantly extremely short time. Transition speed current from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. These voltage spikes degrade efficiency, generate EMI, increase device overvoltage stress ringing. Careful component selection proper board layout minimizes magnitude these voltage spikes. There three sets critical components DC/DC converter using ISL9440, ISL9440A ISL9441: controller, switching power components small signal components. switching power components most critical from layout point view because they switch large amount energy they tend generate large amount noise. critical small signal components those connected sensitive nodes those supplying critical bias currents. multi-layer printed circuit board recommended.
Component Selection Guidelines
MOSFET Considerations
logic level MOSFETs chosen optimum efficiency given potentially wide input voltage range output power requirements. N-Channel MOSFETs used each synchronous-rectified buck converters outputs. These MOSFETs should selected based upon rDS(ON), gate supply requirements, thermal management considerations. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty cycle (see following equations). conduction losses main component power dissipation lower MOSFETs. Only upper MOSFET significant switching losses, since lower device turns into near zero voltage. equations assume linear voltage-current transitions model power loss reverse-recovery lower MOSFET's body diode.
UPPER (EQ. LOWER
Layout Considerations
Input capacitors, Upper FET, Lower FET, Inductor Output capacitor should placed first. Isolate these power components topside board with their ground terminals adjacent another. Place input high frequency decoupling ceramic capacitor very close MOSFETs. separate ground planes power ground small signal ground. Connect SGND PGND together close connect them together anywhere else. loop formed Input capacitor, bottom must kept small possible. Ensure current paths from input capacitor MOSFET, output inductor output capacitor short possible with maximum allowable trace widths. Place controller close lower FET. LGATE connection should short wide. best placed over quiet ground area. Avoid switching ground loop current this area. Place VCC_5V bypass capacitor very close VCC_5V connect ground PGND plane. Place gate drive components BOOT diode BOOT capacitors together near controller
(EQ.
large gate-charge increases switching time, tSW, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal-resistance specifications.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Output Capacitor Selection
output capacitors each output have unique requirements. general, output capacitors should selected meet dynamic regulation requirements including ripple voltage load transients. Selection output capacitors also dependent output inductor, some inductor analysis required select output capacitors. parameters limiting converter's response load transient time required inductor current slew it's level. ISL9440, ISL9440A ISL9441 will provide either maximum duty cycle response load transient. response time time interval required slew inductor current from initial current value load current level. During this interval difference between inductor current transient current level must supplied output capacitor(s). Minimizing response time minimize output capacitance required. Also, load transient rise time slower than inductor response time, hard drive drive, reduces requirement output capacitor. maximum capacitor value required provide full, rising step, transient load current during response time inductor
TRAN
(ISL9440/ISL9441)/600kHz (ISL9440A) bulk capacitors. most cases, multiple small-case electrolytic capacitors perform better than single large-case capacitor. stability requirement selection output capacitor that `ESR zero' between 1.2kHz 30kHz. This range internal, single compensation zero 6kHz. zero factor five either side internal zero still contribute increased phase margin control loop. Therefore:
(EQ.
conclusion, output capacitors must meet three criteria: They must have sufficient bulk capacitance sustain output voltage during load transient while output inductor current slewing value load transient. must sufficiently meet desired output voltage ripple output inductor current. zero should placed, rather large range, provide additional phase margin. recommended output capacitor value ISL9440, ISL9440A ISL9441 between 150F 680F, meet stability criteria with external compensation. aluminum electrolytic (POSCAP) tantalum type capacitors recommended. ceramic capacitors possible would take more rigorous loop analysis ensure stability.
(EQ.
where, COUT output capacitor(s) required, output inductor, ITRAN transient load current step, input voltage, output voltage, DVOUT drop output voltage allowed during load transient. High frequency capacitors initially supply transient current slow load rate-of-change seen bulk capacitors. bulk filter capacitor values generally determined (Equivalent Series Resistance) voltage rating requirements well actual capacitance requirements. output voltage ripple inductor ripple current output capacitors defined
RIPPLE (EQ.
Output Inductor Selection
converters require output inductors. output inductor selected meet output voltage ripple requirements. inductor value determines converter's ripple current ripple voltage function ripple current output capacitor(s) ESR. ripple voltage expression given capacitor selection section ripple current approximated Equation
(EQ.
where, calculated "Output Inductor Selection" page High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load circuitry specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications 300kHz
ISL9440, ISL9440A ISL9441, inductor values between 1.2µH 10µH recommended when using Typical Application Schematic. Other values used thorough stability study should done. smaller volume combination with inductor will more prone stability issues. more phase margin small (typically 10nF) parallel with upper resistor voltage sense resistor divider. example, ISL9440, ISL9440A Application Schematic, output 15µH inductor with which system phase margin less than 45°. resistor capacitor added with upper resistor divider more phase margin.
FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Input Capacitor Selection
important parameters bulk input capacitor(s) voltage rating current rating. reliable operation, select bulk input capacitors with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage times conservative guideline. Input current varies with load. total current supplied input capacitance
RMS1 RMS2 INPUT CURRENT 3.3V PHASE PHASE
(EQ.
3.3V LOAD CURRENT
where,
RMSx
(EQ. FIGURE INPUT CURRENT LOAD
duty cycle respective PWM. Depending specifics input power impedance, most all) this current supplied input capacitor(s). Figure shows advantage having converters operating phase. converters were operating phase, combined current would algebraic sum, which much larger value shown. combined out-of-phase current square root square individual reflected currents significantly less than combined in-phase current.
input bypass capacitors control voltage ripple across MOSFETs. ceramic capacitors high frequency decoupling bulk capacitors supply current. Small ceramic capacitors placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. board designs that allow through-hole components, Sanyo OS-CON® series offer good temperature performance. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surgecurrent power-up. series available from surge current tested.
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FN6383.1 December 2007
ISL9440, ISL9440A, ISL9441
Package Outline Drawing
L32.5x5B
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 11/07
5.00 INDEX AREA 0.50 INDEX AREA
5.00
(4X) 0.15
0.10 0.23 0.05
0.07
0.40 0.10
VIEW
BOTTOM VIEW
DETAIL
0.10
BASE PLANE
SEATING PLANE 0.08
SIDE VIEW
(32X
MIN. MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL
NOTES: Dimensions millimeters. Dimensions Reference Only. Dimensioning tolerancing conform AMSE Y14.5m-1994. Unless otherwise specified, tolerance Decimal 0.05 Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. Tiebar shown present) non-functional feature. configuration identifier optional, must located within zone indicated. identifier either mold mark feature.
FN6383.1 December 2007

Data Sheet December 2007 FN6383.1 Triple, 180° Out-of-Phase, Step

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