1364 1362 world's first fully compliant Serial Digital Video Output (S

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1364 1362 world's first fully compliant Serial Digital Video Output (S

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1364 1362 PanelLink Transmitters
1364 1362 world's first fully compliant Serial Digital Video Output (SDVO)-based transmitters that support full operating range Intel's SDVO input port (1-2 GHz) full scalable output bandwidth (25-165 MHz). Incorporating latest PanelLink® technology, 1362 1364 support display resolutions ranging from UXGA (1600x1200) single link interface. Both chips designed explicitly accommodate Gbps ultra-high speeds required SDVO signaling. With Integrated Graphics Chipset (IGC) market shifting Express, transmitter solution required support Intel's SDVO interface.The 1364 1362 address this market need transmitters compatible with Express chipsets implementing SDVO. 1364 available low-cost 64-pin TQFP package, 1362 available low-cost 48-pin LQFP package. 1362 targeted desktop notebook motherboard applications requires configuration content programmed into system BIOS ROM. Targeted ADD2 card applications, 1364 requires dedicated external EEPROM store configuration data. incorporating most advanced PanelLink technology available today, 1364 1362 transmitters bring highest performance your applications.
DVI-compliant Quality
specification defines precise system-level signaling output transmitter system input receiver system. result, DVI-compliant host will always interoperate with DVI-compliant display.The most comprehensive method determine quality compliance transmitter measure TMDS "eye" diagram defined specification Test Measurement Guide. Only highperformance PanelLink transmitters, such 1364 1362, yield consistently robust differential signal "eyes" that exceed minimum "eye" width height requirements specification full bandwidth 25-165 MHz.
3.3V
Applications
Motherboards Notebook Add-In-Boards
Host
(PC, Graphics Board)
UAIM BIOS EEPROM
Display
(LCD Monitor, Projector, Plasma Display)
HotPlug
SDVO
Video Source
1364
INT# 2.5V
PanelLink Transmitter
Channels
PanelLink Receiver
Pixel data Clock HSYNC VSYNC
Digital Display
Clock Channel (I2C)
SCLDDC
SDADDC
TEST
HTPLG
1364/1362
SDAROM SCLROM Pass-Through Buffer
PanelLink TMDS Core
Registers Configuration Logic
SWING Tx0± Tx1± Tx2± TxC±
Slave
SDVO Receiver Core
SDR± SDG± SDB± SDC± SDI±
SDSDA
SDSCL RESET#
1364 1362 Features
PanelLink Transmitters
General
Scalable output bandwidth from Supports Intel SDVO technology slave interface access internal registers Dual pass-through interfaces host access EDID (via DDC) configuration EEPROM ADD2 Card) Low-voltage input signaling interface: 175mV 1.2V Monitor detection supported through Plug Receiver Sense
Cable distance support greater than meters compliant, with significantly greater margin than competitive solutions 1362: 48-pin LQFP package without EEPROM interface (motherboard applications) 1364: 64-pin TQFP package with EEPROM interface (ADD2 card applications)
Silicon Image 1364 Starter
1364 starter available evaluation from Silicon Image. details this starter kit, please StarterKits/Reference Designs Silicon Image website www.siliconimage.com
Power Management
Low-power 1.8V core operation Built-in ACPI power management Power Down mode
Part Number
1364CTU: 64-pin TQFP package 1362CLU: 48-pin LQFP package Silicon Image, Inc. 1060 Arques, Sunnyvale, 94085 408.616.4000 408.830.9530 www.siliconimage.com
©2004 Silicon Image, Inc. rights reserved. Silicon Image, Silicon Image logo, SiI, 1364, 1362, PanelLink, PanelLink logo TMDS trademarks registered trademarks Silicon Image, Inc. United States other countries. Other trademarks property their respective holders. Product specifications subject change without notice. Printed U.S.A. 6/04 PB-0048

1364 1362 world's first fully compliant Serial Digital Video Output (S

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