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PIC32MX Family Data Sheet
64/100-Pin General Purpose, 32-Bit Flash Microcontrollers
2007 Microchip Technology Inc.
DS61143A
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2007, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS61143A-page
2007 Microchip Technology Inc.
PIC32MX FAMILY
64/100-Pin General Purpose, 32-Bit Flash Microcontrollers
High-Performance RISC CPU:
M4K32-Bit Core with 5-Stage Pipeline Single-Cycle Multiply High-Performance Divide Unit MIPS16eMode Smaller Code Size User Kernel Modes Enable Robust Embedded System 32-Bit Core Register Files Reduce Interrupt Latency Prefetch Cache Module Speed Execution from Flash MIPS32®
Analog Features:
16-Channel 10-Bit Analog-to-Digital Converter: ksps conversion rate Conversion available during Sleep, Idle Analog Comparators
Peripheral Features:
Atomic SET, CLEAR INVERT Operation Select Peripheral Registers 4-Channel Hardware Controller with Automatic Data Size Detection I2CModules UART Modules with: RS-232, RS-485 support IrDA® with on-chip hardware encoder decoder Parallel Master Slave Port (PMP/PSP) with 8-Bit 16-Bit Data Address Lines Hardware Real-Time Clock/Calendar (RTCC) Five 16-Bit Timers/Counters (two 16-bit pairs combine create 32-bit timers) Five Capture Inputs Five Compare/PWM Outputs Five External Interrupt pins Tolerant Input Pins Sink/Source Select Pins Configurable Open-Drain Output Digital Pins
Special Microcontroller Features:
Operating Voltage Range 2.5V 3.6V 32-512K Flash 8-32K Data Memory Additional Boot Flash Memory Pin-Compatible with most PIC24/dsPIC® Devices Multiple Power Management Modes Multiple Interrupt Vectors with Individually Programmable Priority Fail-Safe Clock Monitor Mode Configurable Watchdog Timer with On-Chip, Low-Power Oscillator Reliable Operation Programming Debugging Interfaces: 2-wire interface with unintrusive access real-time data exchange with application 4-wire MIPS standard enhanced JTAG interface Unintrusive Hardware-Based Instruction Trace IEEE 1149.2 Compatible (JTAG) Boundary Scan
General Purpose Program/ Data Memory (KB) 32/8 64/16 128/16 256/32 128/16 256/32 512/32 Comparators Channels Timers/ Capture/ Compare 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 EUART/ SPI/ I2C2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 PMP/PSP Prefetch Cache
VREG
Trace
Device
Pins
10-Bit (ch)
PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F256H PIC32MX320F128L PIC32MX360F256L PIC32MX360F512L
2007 Microchip Technology Inc.
DS61143A-page
JTAG
PIC32MX FAMILY
Diagram (64-Pin General Purpose)
64-Pin TQFP (General Purpose)
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/VREF-/AN1/CN3/RB1 PGD1/PMA6/VREF+/AN0/CN2/RB0
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC32MX3XXH
PGC2/AN6/OCFA/RB6 PGD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
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2007 Microchip Technology Inc.
PIC32MX FAMILY
Diagram (100-Pin General Purpose)
100-Pin TQFP (General Purpose)
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD0/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE CN16/PMD15/RD7 CN15/PMD14/RD6 CN14/PMRD/RD5 OC5/CN13/PMWR/RD4 CN19/PMD13/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/AN1/CN3/RB1 PGD1/AN0/CN2/RB0
PIC32MX3XXL
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
2007 Microchip Technology Inc.
PGC2/AN6/OCFA/RB6 PGD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
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PIC32MX FAMILY
Table Contents
10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 Device Overview PIC32MX Instruction Prefetch Direct Memory Access (DMA) Controller Memory Organization Flash Program Memory Resets Interrupts Oscillators. Power Saving Ports Timer1 Timers 2,3,4,5 Input Capture. Output Compare Serial Peripheral Interface (SPI). Inter-Integrated Circuit (I2CTM) Universal Asynchronous Receiver Transmitter (UART) Parallel master port Real-Time Clock Calendar (RTCC) Analog-Digital Converter Comparator Comparator Reference Special Features Watchdog Timer Programming diagnostics Development Support. Electrical Characteristics Packaging Information.
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2007 Microchip Technology Inc.
PIC32MX FAMILY
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
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2007 Microchip Technology Inc.
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PIC32MX FAMILY
NOTES:
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2007 Microchip Technology Inc.
PIC32MX FAMILY
64/100-Pin General Purpose, 32-Bit Flash Microcontrollers
DEVICE OVERVIEW
Power-Saving Technology
This document contains device specific information following devices: PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX320F128L PIC32MX340F256H PIC32MX360F256L PIC32MX360F512L devices PIC32MX Family incorporate range features that significantly reduce power consumption during operation. features include: On-the-Fly Clock Switching: device clock changed under software control four clock sources during operation. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
This family introduces line Microchip devices: 32-bit RISC microcontroller family with broad peripheral feature enhanced computational performance. PIC32MX Family offers migration option those high-performance applications which outgrowing their 16-bit platforms.
Communications
Easy Migration
PIC32MX Family designed provide easy migration path application needs change. consistent pinout scheme used throughout entire family aids migrating next larger device. This true when moving between devices with same count, even jumping from 64-pin 100-pin devices. PIC32MX Family compatible with Microchip PIC24FJ128GA010 devices.
PIC32MX Family incorporates range serial communication peripherals handle range application requirements. devices equipped with independent UARTs with built-in IrDA encoder/decoders. There also independent modules, independent modules that support both Master Slave modes operation.
10-Bit Converter
Converter features 400+ ksps maximum sample rate. This configurable module incorporates userselectable scan list auto-convert functions allow acquisitions without processor intervention. Multiple trigger sources user-selectable: timer event, external pin, manual auto-convert.
1.2.1
Core Features
32-BIT RISC ARCHITECTURE
External Interface
Central PIC32MX Family devices 32-bit MIPS32 core, offering wide range features, such DMIPS/MHz 32-bit Address Data paths 32-bit Linear (program space) addressing thirty-two element 32-bit core register files Single-cycle multiply high-performance divide unit 32-bit integer math 32-bit instructions, optimized high-level languages, such
Parallel Master Port Parallel Slave Port enables 8/16bit parallel data communications Master mode with address lines; 8-bit Slave modes also supported.
Real-Time Clock/Calendar
This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application.
2007 Microchip Technology Inc.
DS61143A-page
PIC32MX FAMILY
Oscillator Options Features
devices PIC32MX Family offer four different oscillator options, allowing users range choices developing application hardware. These include: Primary Oscillator (POSC) with External Crystal modes using crystals ceramic resonators. External Clock modes with selectable peripheral clock output. Fast Internal Oscillator (FRC) with nominal output. On-board postscalers and/or provide clock speeds ranging from maximum specified frequency. Secondary Oscillator (SOSC) designed operate with external 32.768 crystal. This oscillator also used with Timer1 integrated RTCC. Internal Low-Power oscillator (LPRC) having fixed output, which provides low-power option timing-insensitive applications. oscillator block also provides stable reference source user-controlled Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
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PIC32MX FAMILY
Device Features, Block Diagrams Pinout Tables
DEVICE FEATURES PIC32MX3XXFXXX GENERAL PURPOSE FAMILY
PIC32MX300F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F256H PIC32MX320F128L PIC32MX360F256L PIC32MX360F512L 512K Instruction, Data POR, BOR, MCLR, WDT, (Software Reset), (Configuration Mismatch) (PWRT, OST, Lock) MIPS32® Enhanced Architecture (Release MIPS16eCode Compression Packages 64-pin TQFP 100-pin TQFP
TABLE 1-1:
Features
Operating Frequency Program Memory (Bytes) Data Memory (Bytes) Interrupt Sources/Vectors Ports Total Pins Channels Timers: Total number (16-bit) 32-bit (paired 16-bit) 32-bit core timer Input Capture Channels Output Compare/PWM Channels Input Change Interrupt Notification Serial Communications: Enhanced UART (3-wire/4-wire)
2C
128K
256K Ports Ports 128K 256K
Parallel Communications (PMP/PSP) JTAG Boundary Scan JTAG Debug Program ICSP2-Wire Debug Program Instruction Trace Hardware Break Points 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Internal Resets (and delays) Instruction Support
2007 Microchip Technology Inc.
DS61143A-page
PIC32MX FAMILY
FIGURE 1-1: PIC32MX FAMILY BLOCK DIAGRAM (GENERAL PURPOSE)
OSC2/CLKO OSC1/CLKI VDDCORE/VCAP OSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS Precision Band Reference SYSCLK PBCLK ENVREG Voltage Regulator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(3)
VDD, MCLR
Timing Generation
Peripheral Clocked SYSCLK CN1-22(1) PORTA(1,4) JTAG BSCAN Interrupt Controller OC1-5 DMAC(2) MIPS32® M4KCPU Core PORTC(1) PORTD(1) Matrix PORTE(1) Prefetch Module(2)
Data
Peripheral Clocked PBCLK
PORTB
EJTAG
IC1-5
SPI1,2(1)
I2C1,2 Peripheral Bridge PMP(1)
PORTF(1)
128-Bit Wide Program Flash Memory Flash Controller
UART1,2
PORTG(1)
Comparators
Peripheral Clocked PBCLK
Timer1
Timer2
Timer3
Timer4
Timer5
RTCC
10-Bit
Note
pins features implemented device pinout configurations. Table port descriptions. Some features available certain devices. functionality provided when on-board voltage regulator enabled. PORTA present 64-pin devices
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PIC32MX FAMILY
TABLE 1-2:
Function AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE
Number 64-pin 100-pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Positive Supply Analog Modules. Ground Reference Analog Modules. UART1 IrDA® Baud Clock. UART2 IrDA Baud Clock. Comparator Negative Input. Comparator Positive Input. Comparator Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. Analog Inputs. Description
input buffer Analog level input/output
2007 Microchip Technology Inc.
DS61143A-page
PIC32MX FAMILY
TABLE 1-2:
Function CN18 CN19 CN20 CN21 CVREF ENVREG INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 PMA0/ PMALL
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer Output Compare Fault Input. Output Compare Fault Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data. In-Circuit Debugger ICSPProgramming Clock. In-Circuit Debugger ICSP Programming Data. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Master Clear (Device Reset) Input. Bring this line cause Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. Enable On-Chip Voltage Regulator. Input Capture Inputs. Interrupt-on-Change Inputs. Description
PMA1/ PMALH
Legend:
input buffer Analog level input/output
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PIC32MX FAMILY
TABLE 1-2:
Function PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1/ PMA14 PMCS2/ PMA15 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD/ PMRD/PMWR PMWR/ PMENB Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe (Master Mode Parallel Master Port Read/Write Strobe (Master Mode Parallel Master Port Write Strobe (Master Mode Parallel Master Port Enable Strobe (Master Mode Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Parallel Master Port Chip Select Strobe/Address Parallel Master Port Chip Select Strobe/Address Parallel Master Port Data (Demultiplexed Master mode) Address/ Data (Multiplexed Master modes). Description Parallel Master Port Address (Demultiplexed Master modes).
input buffer Analog level input/output
2007 Microchip Technology Inc.
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PIC32MX FAMILY
TABLE 1-2:
Function RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description
input buffer Analog level input/output
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2007 Microchip Technology Inc.
PIC32MX FAMILY
TABLE 1-2:
Function RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13 Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description
input buffer Analog level input/output
2007 Microchip Technology Inc.
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PIC32MX FAMILY
TABLE 1-2:
Function RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK TRCLK TRD0 TRD1 TRD2 TRD3 Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer
Description PORTG Digital I/O.
Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. Trace Clock. Trace Data Trace Data Trace Data Trace Data Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
input buffer Analog level input/output
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PIC32MX FAMILY
TABLE 1-2:
Function U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCAP VDDCORE VREFVREF+ Legend:
PIC32MX FAMILY PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number 64-pin 100-pin Input Buffer UART1 Clear Send Input. UART1 Request Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear Send Input. UART2 Request Send Output. UART Receive Input. UART2 Transmit Output. Positive Supply Peripheral Digital Logic pins. External Filter Capacitor Connection (regulator enabled). Positive Supply Microcontroller Core Logic (regulator disabled). Comparator Reference Voltage (Low) Input. Comparator Reference Voltage (High) Input. Ground Reference Logic pins. Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Description
input buffer Analog level input/output
2007 Microchip Technology Inc.
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PIC32MX FAMILY
NOTES:
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2007 Microchip Technology Inc.
PIC32MX
Note:
PIC32MX
This data sheet summarizes features PIC32MX devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description this peripheral.
module heart PIC32MX processor. fetches instructions, decodes each instruction, fetches source operands, executes each instruction, writes results instruction execution proper destinations.
Features
5-stage pipeline 32-bit Address Data Paths MIPS32 Enhanced Architecture (Release Multiply-Accumulate Multiply-Subtract Instructions Targeted Multiply Instruction Zero/One Detect Instructions Wait Instruction Conditional Move Instructions (MOVN, MOVZ) Vectored interrupts Programmable exception vector base Atomic interrupt enable/disable shadow registers minimize latency interrupt handlers field manipulation instructions MIPS16eCode Compression encodings instructions improve code density Special PC-relative instructions efficient loading addresses constants SAVE RESTORE macro instructions setting tearing down stack frames within subroutines Improved support handling data types
Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Interface Independent 32-bit address data busses Transactions aborted improve interrupt latency Autonomous Multiply/Divide Unit Maximum issue rate 32x16 multiply clock Maximum issue rate 32x32 multiply every other clock Early-in iterative divide. Minimum maximum clock latency (dividend (rs) sign extension-dependent) Power Control Minimum frequency: Low-Power mode (triggered WAIT instruction) Extensive local gated clocks EJTAG Debug Instruction Trace Support single stepping Virtual instruction data address/value breakpoints tracing trace compression
2007 Microchip Technology Inc.
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PIC32MX
Architecture Overview
PIC32MX core contains several logic blocks working together parallel, providing efficient high performance computing engine. blocks included with PIC32MX core follows: Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal interfaces Power Management MIPS16e support Enhanced JTAG (EJTAG) Controller
FIGURE 2-1:
BLOCK DIAGRAM
EJTAG Trace
Trace Off-Chip Debug
Interface
Dual
System Coprocessor
Power Mgmt
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2007 Microchip Technology Inc.
Matrix
Execution Core (RF/ALU/Shift)
PIC32MX
2.2.1 EXECUTION UNIT 2.2.2 MULTIPLY/DIVIDE UNIT (MDU)
PIC32MX core execution unit implements load/ store architecture with single-cycle operations (logical, shift, add, subtract) autonomous multiply/divide unit. PIC32MX core contains thirtytwo 32-bit general-purpose registers used integer operations address calculation. additional register file shadow (containing thirty-two registers) added minimize context switching overhead during interrupt/exception processing. register file consists read ports write port fully bypassed minimize operation latency pipeline. execution unit includes: 32-bit adder used calculating data address Address unit calculating next instruction address Logic branch determination branch target address calculation Load aligner Bypass multiplexers used avoid stalls when executing instructions streams where data producing instructions followed closely consumers their results Leading Zero/One detect unit implementing instructions Arithmetic Logic Unit (ALU) performing bitwise logical operations Shifter Store Aligner PIC32MX core includes multiply/divide unit (MDU) that contains separate pipeline multiply divide operations. This pipeline operates parallel with integer unit (IU) pipeline does stall when pipeline stalls. This allows operations partially masked system stalls and/ other integer unit instructions. high-performance consists 32x16 booth recoded multiplier, result/accumulation registers LO), divide state machine, necessary multiplexers control logic. first number shown (`32' 32x16) represents operand. second number (`16' 32x16) represents operand. PIC32MX core only checks value latter (rt) operand determine many times operation must pass through multiplier. 16x16 32x16 operations pass through multiplier once. 32x32 operation passes through multiplier twice. supports execution 16x16 32x16 multiply operation every clock cycle; 32x32 multiply operations issued every other clock cycle. Appropriate interlocks implemented stall issuance back-to-back 32x32 multiply operations. multiply operand size automatically determined logic built into MDU. Divide operations implemented with simple clock iterative algorithm. early-in detection checks sign extension dividend (rs) operand. bits wide, iterations skipped. 16bit-wide iterations skipped, 24-bitwide iterations skipped. attempt issue subsequent instruction while divide still active causes pipeline stall until divide operation completed. Table lists repeat rate (peak issue rate cycles until operation reissued) latency (number cycles until result available) PIC32MX core multiply divide instructions. approximate latency repeat rates listed terms pipeline clocks.
2007 Microchip Technology Inc.
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PIC32MX
TABLE 2-1: PIC32MX CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU DIV/DIVU Operand Size (mul (div bits bits bits bits bits bits bits bits MIPS architecture defines that result multiply divide operation placed registers. Using Move-From-HI (MFHI) MoveFrom-LO (MFLO) instructions, these values transferred general-purpose register file. addition HI/LO targeted operations, MIPS32 architecture also defines multiply instruction, MUL, which places least significant results primary register file instead HI/LO register pair. avoiding explicit MFLO instruction, required when using register, supporting multiple destination registers, throughput multiply-intensive operations increased. other instructions, multiply-add (MADD) multiply-subtract (MSUB), used perform multiply-accumulate multiply-subtract operations. MADD instruction multiplies numbers then adds product current contents registers. Similarly, MSUB instruction multiplies operands then subtracts product from registers. MADD MSUB operations commonly used algorithms. Latency Repeat Rate
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2.2.3 SYSTEM CONTROL COPROCESSOR (CP0)
MIPS architecture, responsible virtual-to-physical address translation, exception control system, processor's diagnostics capability, operating modes (kernel, user, debug), whether interrupts enabled disabled. Configuration information, such presence options like MIPS16e, also available accessing registers, listed Table 2-2.
TABLE 2-2:
COPROCESSOR REGISTERS
Function Reserved PIC32MX core Enables access RDHWR instruction selected hardware registers Reports address most recent address-related exception Processor cycle count Reserved PIC32MX core Timer interrupt control Processor status control Interrupt system status control Shadow register status control Provides mapping from vectored interrupt shadow Cause last general exception Program counter last exception Processor identification revision Exception vector base register Configuration register Configuration register Configuration register Configuration register Reserved PIC32MX core Debug control exception status Program counter last debug exception. Reserved PIC32MX core. Program counter last error. Debug handler scratchpad register.
Register Register Number Name 17-22 25-29 Note Reserved HWREna BadVAddr(1) Count(1) Reserved Compare Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1)
PRId EBASE Config Config1 Config2 Config3 Reserved Debug
DEPC(2) Reserved ErrorEPC(1) DESAVE(2)
Registers used exception processing. Registers used during debug.
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Coprocessor also contains logic identifying managing exceptions. Exceptions caused variety sources, including alignment errors data, external events, program errors. Table shows exception types order priority.
TABLE 2-3:
Exception Reset DINT Interrupt AdEL DDBL DDBS AdEL AdES DDBL
PIC32MX CORE EXCEPTION TYPES
Description Assertion MCLR Power-On Reset (POR) EJTAG Debug Single Step. EJTAG Debug Interrupt. Caused assertion external EJ_DINT input, setting EjtagBrk register. Assertion signal. Assertion unmasked hardware software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference protected address. Instruction fetch error. EJTAG Breakpoint (execution SDBBP instruction). Execution SYSCALL instruction. Execution BREAK instruction. Execution Reserved Instruction. Execution coprocessor instruction coprocessor that enabled. Execution CorExtend instruction when CorExtend enabled. Execution arithmetic instruction that overflowed. Execution trap (when trap condition true). EJTAG Data Address Break (address only) EJTAG Data Value Break Store (address value). Load address alignment error. Load reference protected address. Store address alignment error. Store protected address. Load store error. EJTAG data hardware breakpoint matched load data compare.
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2.2.4 INTERRUPT HANDLING 2.2.5 SHADOW REGISTERS
PIC32MX core includes support peripheral interrupts, software interrupts, timer interrupt. PIC32MX uses MIPS External Interrupt Controller (EIC) mode, which redefines which interrupts handled provide full support external interrupt controller handling prioritization vectoring interrupts. This presence this mode denoted VEIC Config3 register. PIC32MX core, VEIC always indicate presence external interrupt controller. Note: Although mode designated "External", interrupt controller onchip. Release MIPS32 Architecture optionally removes need save restore GPRs entry high priority interrupts exceptions, provide specified processor modes with same capability. This done introducing multiple copies GPRs, called shadow sets, allowing privileged software associate shadow with entry kernel mode interrupt vector exception. normal GPRs logically considered shadow zero. PIC32MX core implements sets registers, normal GPRs, shadow set. This indicated SRSCtlHSS field.
interrupt controller specifies which shadow should used upon entry particular vector. shadow registers further improve interrupt latency avoiding need save context when invoking interrupt handler.
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Modes Operation
PIC32MX core supports three modes operation: user mode, kernel mode, debug mode. User mode most often used applications programs. Kernel mode typically used handling exceptions operating system kernel functions, including management device accesses. additional Debug mode used during system bring-up software development. Refer EJTAG specification more information debug mode.
FIGURE 2-2:
PIC32MX CORE VIRTUAL ADDRESS
0xFFFFFFFF
Fixed Mapped
0xFF400000 0xFF3FFFFF 0xFF200000 0xF1FFFFFF 0xE0000000 0xDFFFFFFF
Memory/EJTAG(1) Fixed Mapped Kernel Virtual Address Space Fixed Mapped, Kernel Virtual Address Space Unmapped, Uncached Kernel Virtual Address Space Unmapped,
kseg3
kseg2
0xC0000000 0xBFFFFFFF
kseg1
0xA0000000 0x9FFFFFFF
kseg0
0x80000000 0x7FFFFFFF
User Virtual Address Space Fixed Mapped, 2048
kuseg
0x00000000
Note This space mapped memory user kernel mode, EJTAG module Debug mode.
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2.3.1 FIXED MAPPING TRANSLATION
PIC32MX core provides simple Fixed Mapping Translation (FMT) mechanism that smaller simpler than full Translation Lookaside Buffer (TLB) found other MIPS cores. Like TLB, performs virtual-to-physical address translation provides attributes different segments. Those segments that unmapped implementation (kseg0 kseg1) translated identically FMT. Figure shows implemented PIC32MX core.
FIGURE 2-3:
ADDRESS TRANSLATION DURING MEMORY ACCESS
Virtual Address Physical Address
Instruction Address Calculator
Instn SRAM SRAM Interface Data SRAM
Virtual Address Physical Address
Data Address Calculator
general, also determines cacheability each segment. These attributes controlled bits Config register. Table shows encoding (bits 30:28), (bits 27:25), (bits 2:0) fields Config register. PIC32MX core passes these Config fields Prefetch Cache module determine cacheability Program Memory Flash accesses. Table shows cacheability virtual address segments controlled these fields.
TABLE 2-4:
CACHE COHERENCY ATTRIBUTES
Cache Coherency Attribute Uncached. Cacheable
Config Register Fields K23,
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PIC32MX core, translation exceptions taken, although address errors still possible.
TABLE 2-5:
Segment useg/kuseg
CACHEABILITY SEGMENTS WITH FIXED MAPPING TRANSLATION
Virtual Address Range 0x0000_0000-0x7FFF_FFFF Cacheability Controlled field (bits 27:25) Config register. Figure mapping. This segment always uncached when Controlled field (bits 2:0) Config register. Figure mapping. Always uncacheable. Controlled field (bits 30:28) Config register. Figure mapping. Controlled field (bits 30:28) Config register. Figure mapping.
kseg0 kseg1 kseg2 kseg3
0x8000_0000- 0x9FFF_FFFF 0xA000_0000-0xBFFF_FFFF 0xC000_0000-0xDFFF_FFFF 0xE000_0000-0xFFFF_FFFF
performs simple translation from virtual addresses physical addresses. This mapping shown Figure 2-4.
FIGURE 2-4:
MEMORY (ERL PIC32MX CORE
Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000
Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000
useg/kuseg
useg/kuseg
0x4000_0000 reserved 0x2000_0000
0x0000_0000
kseg0/kseg1 0x0000_0000
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When useg kuseg become unmapped (virtual address identical physical address) uncached. This behavior same there TLB. This mapping shown Figure 2-5.
FIGURE 2-5:
PIC32MX CORE MEMORY (ERL
Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000
reserved 0x8000_0000
useg/kuseg
useg/kuseg
0x0000_0000
kseg0/kseg1 0x0000_0000
2.3.2
DUAL INTERNAL INTERFACES
2.3.3
MIPS16E EXECUTION
SRAM interface includes dual instruction data interfaces. dual interface enables independent connection instruction data devices. yields highest performance, since pipeline generate simultaneous requests which then serviced parallel. internal buses connected Matrix unit, which switch fabric that provides this parallel operation.
When core operating MIPS16e mode, instruction fetches only require 16-bits data returned. improved efficiency, however, core will fetch 32-bits instruction data whenever address word-aligned. Thus sequential MIPS16e code, fetches only occur every other instruction, resulting better performance reduced system power.
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Power Management
2.5.1 DEBUG REGISTERS
PIC32MX core offers number power management features, including low-power design, active power management, power-down modes operation. core static design that supports slowing halting clocks, which reduces system power consumption during idle periods. Three debug registers (DEBUG, DEPC, DESAVE) have been added MIPS Coprocessor (CP0) register set. DEBUG register shows cause debug exception used setting singlestep operations. DEPC, Debug Exception Program Counter, register holds address which debug exception taken. This used resume program execution after debug operation finishes. Finally, DESAVE, Debug Exception Save, register enables saving general-purpose registers used during execution debug exception handler. exit debug mode, Debug Exception Return (DERET) instruction executed. When this instruction executed, system exits debug mode, allowing normal execution application system code resume.
2.4.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
mechanism invoking power-down mode through execution WAIT instruction. more information power management, 11.0 "Power Saving".
2.4.2
LOCAL CLOCK GATING
majority power consumed PIC32MX core clock tree clocking registers. PIC32MX uses extensive local gated-clocks reduce this dynamic power consumption.
2.5.2
EJTAG HARDWARE BREAKPOINTS
EJTAG Debug Support
PIC32MX core provides Enhanced JTAG (EJTAG) interface software debug application kernel code. addition standard user mode kernel modes operation, PIC32MX core provides Debug mode that entered after debug exception (derived from hardware breakpoint, single-step exception, etc.) taken continues until debug exception return (DERET) instruction executed. During this time, processor executes debug exception handler routine. EJTAG interface operates through Test Access Port (TAP), serial communication port used transferring test data PIC32MX core. addition standard JTAG instructions, special instructions defined EJTAG specification define what registers selected they used.
There several types simple hardware breakpoints defined EJTAG specification. These stop normal operation force system into debug mode. There types simple hardware breakpoints implemented PIC32MX core: Instruction breakpoints Data breakpoints. PIC32MX core data instruction breakpoints Instruction breaks occur instruction fetch operations, break virtual address. mask applied virtual address breakpoints range instructions. Data breakpoints occur load/store transactions. Breakpoints virtual address values, similar Instruction breakpoint. Data breakpoints load, store, both. Data breakpoints also based value load/store operation. Finally, masks applied both virtual address load/store value.
2.5.3
INSTRUCTION TRACING
PIC32MX core includes Trace support real-time tracing instruction addresses. trace information collected off-chip memory, post-capture processing trace regeneration software. Off-chip trace memory accessed through special trace probe that consists data pins plus clock.
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Initialization
Software required initialize following parts device after reset event.
2.6.1
GENERAL-PURPOSE REGISTERS
register file powers unknown state with exception which always Initializing rest register file required proper operation hardware. Depending software environment however, several registers need initialized. Some these are: Stack Pointer Global Pointer Frame Pointer
2.6.2
COPROCESSOR STATE
Miscellaneous states need initialized prior leaving boot code. There various exceptions which blocked which cleared Reset. These cleared avoid taking spurious exceptions when leaving boot code.
TABLE 2-6:
Register Cause Config
INITIALIZATION
Action
(Watch Pending), SW0/1 (Software Interrupts) should cleared. Typically, fields should desired Cache Coherency Algorithm (CCA) value prior accessing corresponding memory regions. core, values treated identically, hardware reset value these fields need modified. Count(1) Should known value Timer Interrupts used. Compare(1) Should known value Timer Interrupts used. write compare will also clear pending Timer Interrupts (Thus, Count should before Compare avoid unexpected interrupts). Status Desired state device should set. Other state Other registers should written before they read. Some registers explicitly writeable, only updated by-product instruction execution taken exception. Uninitialized bits should masked after reading these registers. Note When Count register equal Compare register timer interrupt signaled. There mask interrupt controller disable passing this interrupt desired.
Configuration
module EJTAG pins that configured user-available pins. EJTAG used debug, important make sure that software does clear DDPCON<JTAGEN>.
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INSTRUCTION
PIC32MX family instruction complies with MIPS32 Release instruction architecture. PIC32MX does support following features: CoreExtend instructions Coprocessor instructions Coprocessor instructions Table provides summary instructions implemented PIC32MX family core.
TABLE 3-1:
Instruction ADDI ADDIU ADDIUPC ADDU ANDI BEQL
PIC32MX FAMILY INSTRUCTION
Description Integer Integer Immediate Unsigned Integer Immediate Unsigned Integer Immediate (MIPS16eonly) Unsigned Integer Logical Logical Immediate Unconditional Branch (Assembler idiom for: offset) Branch Link (Assembler idiom for: BGEZAL offset) Branch Equal Branch Equal Likely Function Immed Immed Immed (016 Immed) (int)offset GPR[31> (int)offset (int)offset (int)offset else Ignore Next Instruction !Rs[31> (int)offset GPR[31> !Rs[31> (int)offset GPR[31> !Rs[31> (int)offset else Ignore Next Instruction !Rs[31> (int)offset else Ignore Next Instruction !Rs[31> (int)offset !Rs[31> (int)offset else Ignore Next Instruction Rs[31> (int)offset
BGEZ BGEZAL
Branch Greater Than Equal Zero Branch Greater Than Equal Zero Link
BGEZALL
Branch Greater Than Equal Zero Link Likely
BGEZL
Branch Greater Than Equal Zero Likely
BGTZ BGTZL
Branch Greater Than Zero Branch Greater Than Zero Likely
BLEZ
Branch Less Than Equal Zero
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TABLE 3-1:
Instruction BLEZL
PIC32MX FAMILY INSTRUCTION (CONTINUED)
Description Branch Less Than Equal Zero Likely Function Rs[31> (int)offset else Ignore Next Instruction Rs[31> (int)offset GPR[31> Rs[31> (int)offset GPR[31> Rs[31> (int)offset else Ignore Next Instruction Rs[31> (int)offset else Ignore Next Instruction (int)offset (int)offset else Ignore Next Instruction Break Exception NumLeadingOnes(Rs) NumLeadingZeroes(Rs) Software User's Manual DEPC Exit Debug Mode Status; StatusIE (int)Rs (int)Rt (int)Rs (int)Rt (uns)Rs (uns)Rt (uns)Rs (uns)Rt Stop instruction execution until execution hazards cleared Status; StatusIE SR[2> ErrorEPC else SR[1> SR[2> ExtractField(Rs, pos, size) InsertField(Rs, pos, size) PC[31:28> offset<<2
BLTZ BLTZAL
Branch Less Than Zero Branch Less Than Zero Link
BLTZALL
Branch Less Than Zero Link Likely
BLTZL
Branch Less Than Zero Likely
BNEL
Branch Equal Branch Equal Likely
BREAK COP0 DERET DIVU
Breakpoint Count Leading Ones Count Leading Zeroes Coprocessor Operation Return from Debug Exception Atomically Disable Interrupts Divide Unsigned Divide Execution Hazard Barrier
ERET
Atomically Enable Interrupts Return from Exception
Extract Field Insert Field Unconditional Jump
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TABLE 3-1:
Instruction JALR JALR.HB JALRC JR.HB Jump Link Jump Link Register Jump Link Register with Hazard Barrier Jump Link Register Compact execute instruction jump delay slot (MIPS16eonly) Jump Register Jump Register with Hazard Barrier
PIC32MX FAMILY INSTRUCTION (CONTINUED)
Description Function GPR[31> PC[31:28> offset<<2 Like JALR, also clears execution instruction hazards Like also clears execution instruction hazards
Jump Register Compact execute instruction jump delay slot (MIPS16e only) Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word (byte)Mem[Rs+offset> (ubyte))Mem[Rs+offset> (half)Mem[Rs+offset> (uhalf)Mem[Rs+offset> Mem[Rs+offset> LLAdr offset immediate Mem[Rs+offset> Mem[PC+offset> Architecture Reference Manual Architecture Reference Manual (int)Rs (int)Rt (uns)Rs (uns)Rt CPR[0, sel> then then (int)Rs (int)Rt (uns)Rs (uns)Rt CPR[0, Sel> =Unpredictable ((int)Rs (int)Rt)31.0 (int)Rs (int)Rd (uns)Rs (uns)Rd
LWPC MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MULT MULTU
Load Upper Immediate Load Word Load Word, relative Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move From Coprocessor Move From Move From Move Conditional Zero Move Conditional Zero Multiply-Subtract Multiply-Subtract Unsigned Move Coprocessor Move Move Multiply with register write Integer Multiply Unsigned Multiply Operation (Assembler idiom for: Logical Logical
~(Rs
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TABLE 3-1:
Instruction RDHWR RDPGPR RESTORE ROTR ROTRV SAVE
PIC32MX FAMILY INSTRUCTION (CONTINUED)
Description Logical Immediate Read Hardware Register Read from Previous Shadow Restore registers deallocate stack frame (MIPS16eonly) Rotate Word Right Rotate Word Right Variable Store Byte Store Conditional Word Function Immed Allows unprivileged access registers enabled HWREna register SGPR[SRSCtlPSS, Architecture Reference Manual Rtsa-1.0 Rt31.sa
RtRs-1.0 Rt31.Rs Save registers allocate stack frame (MIPS16e only) Architecture Reference Manual (byte)Mem[Rs+offset> mem[Rs+offset> Trap Debug Handler (byte)Rs (half)Rs (half)Mem[Rs+offset> Rs[4:0> (int)Rs (int)Rt else (int)Rs (int)Immed else (uns)Rs (uns)Immed else (uns)Rs (uns)Immed else (int)Rt (int)Rt Rs[4:0> (uns)Rt (uns)Rt Rs[4:0> (int)Rs (int)Rd (uns)Rs (uns)Rd Mem[Rs+offset> Architecture Reference Manual Architecture Reference Manual Software User's Manual SystemCallException
SDBBP SLLV
Software Debug Break Point Sign-Extend Byte Sign-Extend Half Store Half Shift Left Logical Shift Left Logical Variable Less Than
SLTI
Less Than Immediate
SLTIU
Less Than Immediate Unsigned
SLTU
Less Than Unsigned
SRAV SRLV SSNOP SUBU SYNC SYSCALL
Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit Operation Integer Subtract Unsigned Subtract Store Word Store Word Left Store Word Right Synchronize System Call
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TABLE 3-1:
Instruction TEQI TGEI TGEIU TGEU TLTI TLTIU TLTU TNEI WAIT WRPGPR WSBH XORI Trap Equal Trap Equal Immediate Trap Greater Than Equal Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Greater Than Equal Unsigned Trap Less Than Trap Less Than Immediate Trap Less Than Immediate Unsigned Trap Less Than Unsigned Trap Equal Trap Equal Immediate Wait Interrupts Write Previous Shadow Word Swap Bytes Within Halfwords Exclusive Exclusive Immediate Zero-extend byte (MIPS16eonly) Zero-extend half (MIPS16e only)
PIC32MX FAMILY INSTRUCTION (CONTINUED)
Description Function TrapException (int)Immed TrapException (int)Rs (int)Rt TrapException (int)Rs (int)Immed TrapException (uns)Rs (uns)Immed TrapException (uns)Rs (uns)Rt TrapException (int)Rs (int)Rt TrapException (int)Rs (int)Immed TrapException (uns)Rs (uns)Immed TrapException (uns)Rs (uns)Rt TrapException TrapException (int)Immed TrapException Stall until interrupt occurs SGPR[SRSCtlPSS, Rt23.16 Rt31.24 Rt7.0 Rt15.8 (uns)Immed (ubyte) (uhalf)
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NOTES:
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Note:
PREFETCH CACHE
This data sheet summarizes features PIC32MX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description this peripheral.
Features
Prefetch cache increases performance applications executing cacheable program flash memory region implementing instruction caching, data caching, instruction prefetching.
Fully Associative Lockable Cache Lines 16-byte Cache Lines Cache Lines allocated Data Cache Lines with Address Mask hold repeated instructions Pseudo replacement policy Cache Lines software writable 16-byte parallel memory fetch Predictive Instruction Prefetch
FIGURE 4-1:
PREFETCH MODULE BLOCK DIAGRAM
BMX/CPU
CTRL Logic Cache Line
CTRL
Ctrl Cache Ctrl Prefetch Ctrl Miss Logic PreFetch Pre-Fetch CTRL PreFetch Pre-Fetch RDATA Cache Line Address Encode
BMX/CPU
RDATA
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TABLE 4-1:
Virtual Address
PREFETCH SUMMARY
Name 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PFMWS<2:0> DCSZ<1:0> 24/16/8/0 CHECOH
BF88_4000 CHECON
PREFEN<1:0>
BF88_4004 CHECONCLR BF88_4008 CHECONSET BF88_400C CHECONINV BF88_4010 CHEACC
31:0 31:0 31:0 31:24 23:16 15:8 CHEWEN
Clears selected bits CHECON, read yields undefined value Sets selected bits CHECON, read yields undefined value Inverts selected bits CHECON, read yields undefined value
CHEIDX<3:0>
BF88_4014 CHEACCCLR BF88_4018 CHEACCSET BF88_401C CHEACCINV BF88_4020 CHETAG
31:0 31:0 31:0 31:24 23:16 15:8 LTAGBOOT
Clears selected bits CHEACC, read yields undefined value Sets selected bits CHEACC, read yields undefined value Inverts selected bits CHEACC, read yields undefined value LTAG<23:16> LTAG<15:8> LTAG<7:4> LVALID LLOCK LTYPE Clears selected bits CHETAG, read yields undefined value Sets selected bits CHETAG, read yields undefined value Inverts selected bits CHETAG, read yields undefined value LMASK<7:5> LMASK<15:8> Clears selected bits CHEMSK, read yields undefined value Sets selected bits CHEMSK, read yields undefined value Inverts selected bits CHEMSK, read yields undefined value CHEW0<31:24> CHEW0<23:16> CHEW0<15:8> CHEW0<7:0> CHEW1<31:24> CHEW1<23:16> CHEW1<15:8> CHEW1<7:0> CHEW2<31:24> CHEW2<23:16> CHEW2<15:8> CHEW2<7:0> CHEW3<31:24> CHEW3<23:16> CHEW3<15:8> CHEW3<7:0> CHELRU<24> CHELRU<23:16> CHELRU<15:8> CHELRU<7:0>> CHEHIT<31:24> CHEHIT<23:16> CHEHIT<15:8> CHENIT<7:0>
BF88_4024 CHETAGCLR BF88_4028 CHETAGSET BF88_402C CHETAGINV BF88_4030 CHEMSK
31:0 31:0 31:0 31:24 23:16 15:8
BF88_4034 CHEMSKCLR BF88_4038 CHEMSKSET BF88_403C CHEMSKINV BF88_4040 CHEW0
31:0 31:0 31:0 31:24 23:16 15:8
BF88_4050 CHEW1
31:24 23:16 15:8
BF88_4060 CHEW2
31:24 23:16 15:8
BF88_4070 CHEW3
31:24 23:16 15:8
BF88_4080 CHELRU
31:24 23:16 15:8
BF88_4090 CHEHIT
31:24 23:16 15:8
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TABLE 4-1:
Virtual Address
PREFETCH SUMMARY (CONTINUED)
Name 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_40A0 CHEMIS
CHEMIS<31:24> CHEMIS<23:16> CHEMIS<15:8> CHEMIS<7:0> PFABT<31:24> PFABT<23:16> PFABT<15:8> PFABT<7:0>
BF88_40C0 PFABT
31:24 23:16 15:8
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Prefetch Registers
CHECON: CACHE CONTROL REGISTER
R/W-0 CHECOH R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 PFMWS<2:0> R/W-1 Legend: Readable Unimplemented 31-17 Writable Programmable Reserved Value POR: (`0', `1', Unknown)
REGISTER 4-1:
DCSZ<1:0>
PREFEN<1:0>
Unimplemented: Read CHECOH: Cache Coherency setting Program Cycle Invalidate data instruction lines Invalidate data lnes instruction lines that locked Unimplemented: Read Reserved: Must written with zeros Unimplemented: Read DCSZ<1:0>: Data Cache Size Lines bits Enable data caching with size Lines Enable data caching with size Lines Enable data caching with size Line Disable data caching Changing this field causes lines re-initialized "invalid" state. Unimplemented: Read PREFEN<1:0>: Predictive Prefetch Cache Enable bits Enable predictive prefetch cache both cacheable non-cacheable regions Enable predictive prefetch cache non-cacheable regions only Enable predictive prefetch cache cacheable regions only Disable predictive prefetch cache Unimplemented: Read
15-14 13-12 11-10
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REGISTER 4-1:
CHECON: CACHE CONTROL REGISTER (CONTINUED)
PFMWS<2:0>: Access Time Defined terms SYSLK Wait states bits Seven Wait states Wait states Five Wait state Four Wait states Three Wait states Wait states Wait state Zero Wait states
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REGISTER 4-2:
R/W-0 CHEWEN Legend: Readable Unimplemented Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 R/W-0 R/W-0
CHEACC: CACHE ACCESS
R/W-0
CHEIDX<3:0>
CHEWEN: Cache Access Enable bits registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, CHEW3 cache line selected CHEIDX writable cache line selected CHEIDX writable Unimplemented: Read CHEIDX<3:0>: Cache Line Index bits value selects cache line reading writing.
30-4
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REGISTER 4-3:
R/W-0 LTAGBOOT R/W-x R/W-x R/W-x Legend: Readable Unimplemented Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-0 LVALID R/W-0 LLOCK R/W-1 LTYPE R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHETAG(1): CACHE REGISTER
R/W-x R/W-x
LTAG<23:16>
LTAG<15:8>
LTAG<7:4>
LTAGBOOT: Line Address Boot line 0x1D000000 (physical) area memory line 0x1FC00000 (physical) area memory Unimplemented: Read LTAG<23:4>: Line Address bits LTAG bits compared against physical address <23:4> determine hit. Because address range position Flash kernel space user space, LTAG Flash address identical virtual addresses, (system) physical addresses, Flash physical addresses. LVALID: Line Valid line valid compared physical address detection line valid compared physical address detection LLOCK: Line Lock line locked will replaced line locked replaced LTYPE: Line Type line caches instruction words line caches data words Reserved: Status Line pointed CHEIDX (CHEACC<3:0>).
30-24 23-4
Note
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REGISTER 4-4:
R/W-0 R/W-0 Legend: Readable Unimplemented 31-16 15-5 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 LMASK<7:5> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHEMSK(1): CACHE MASK REGISTER
R/W-0
LMASK<15:8>
Unimplemented: Read LMASK<15:5>: Line Mask bits Enables mask logic force match corresponding position LTAG (CHETAG<23:4>) physical address. Only writeable values CHEIDX (CHEACC<3:0>) equal OxOA OxOB. Disables mask logic. Unimplemented: Read Mask Line pointed CHEIDX (CHEACC<3:07>).
Note
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REGISTER 4-5:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW0: CACHE WORD
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW0<31:24>
CHEW0<23:16>
CHEW0<15:8>
CHEW0<7:0>
CHEW0<31:0>: Word cache line selected CHEACC.CHEIDX Readable only device code-protected.
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REGISTER 4-6:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1: CACHE WORD
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<31:24>
CHEW1<23:16>
CHEW1<15:8>
CHEW1<7:0>
CHEW1<31:0>: Word cache line selected CHEACC.CHEIDX Readable only device code-protected.
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REGISTER 4-7:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2 CACHE WORD
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW2<31:24>
CHEW2<23:16>
CHEW2<15:8>
CHEW2<7:0>
CHEW2<31:0>: Word cache line selected CHEACC.CHEIDX Readable only device code-protected.
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REGISTER 4-8:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Note Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3(1): CACHE WORD
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<31:24>
CHEW3<23:16>
CHEW3<15:8>
CHEW3<7:0>
CHEW3<31:0>: Word cache line selected CHEACC.CHEIDX Readable only device code-protected. This register window into cache data array readable only device code-protected.
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REGISTER 4-9:
Legend: Readable Unimplemented 31-25 24-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown)
CHELRU: CACHE REGISTER
CHELRU<24>
CHELRU<23-16>
CHELRU<15-8>
CHELRU<7-0>
Unimplemented: Read CHELRU<24:0>: Cache Least Recently Used State Encoding bits CHELRU indicates Pseudo-LRU state cache.
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REGISTER 4-10:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEHIT: CACHE STATISTICS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24>
CHEHIT<23:16>
CHEHIT<15:8>
CHEHIT<7:0>
CHEHIT<31:0>: Cache Count bits Incremented each time processor issues instruction fetch load that hits prefetch cache from cacheable region. Non-cacheable accesses modify this value.
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REGISTER 4-11:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEMIS: CACHE MISS STATISTICS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEMIS<31:24>
CHEMIS<23:16>
CHEMIS<15:8>
CHEMIS<7:0>
CHEMIS<31:0>: Cache Miss Count bits Incremented each time processor issues instruction fetch from cacheable region that misses prefetch cache. Non-cacheable accesses modify this value.
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REGISTER 4-12:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PFABT: PREFETCH CACHE ABORT STATISTICS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PFABT<31:24>
PFABT<23:16>
PFABT<15:8>
PFABT<7:0>
PFABT<31:0>: Prefab Abort Count bits Incremented each time automatic prefetch cache aborted non-sequential instruction fetch, load store.
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Prefetch Configuration
TABLE 4-2:
DCSZ<1:0> CHECON register controls configurations available instruction data caching Program Flash Memory. addition normal instruction caching, prefetch cache ability cache lines specifically Flash Memory data. CHECON.DCSZ field controls number lines allocated program data caching. Table shows cache line relationship values DCSZ. data caching capability read only data such constants, parameters, table data, etc., that modified.
PROGRAM DATA CACHE
Lines Allocated Program Data None Cache Line Number Cache Line Number Cache Line Number through
CHECON.PREFEN field controls predictive prefetching, which allows prefetch module speculatively fetch next 16-byte aligned instructions. prefetch module loads data into data array only accesses cacheable regions (CCA bits
EXAMPLE 4-1:
EXAMPLE CODE: INITIALIZATION CODE PREFETCH MODULE
Prefetch Cache Initialization _CP0_GET_CONFIG(); read CONFIG register kseg0 cacheable _CP0_SET_CONFIG(tmp); write CONFIG register CHECON (1<<4) wait-states, Prefetching enabled cached memory
4.3.1
LINE LOCKING
Each line cache locked hold contents. line locked both LVALID=1 LLOCK=1. LVALID=0 LLOCK=1, prefetch module issues preload request (see below). Locking cache lines reduce performance general program flow. However, functions calls consume significant percent overall processing, locking their address provide improved performance. Though number lines locked, cache works most efficiently when locking either lines. locking lines, choose lines whose line number divide have same quotient. This locks entire group which benefits algorithm. example, lines each have quotient when divided
cache lines manually filled, recommended that following sequence used. Choose cache line fill. Lock Valid bits cache line writing CHETAG. Write each word cache line writing CHEW0, CHEW1, CHEW2, CHEW3.
EXAMPLE 4-2:
EXAMPLE CODE: LOCKING LINE PREFETCH MODULE
#define LOCKED_LINE_NUM lock first line func1() cache CHEACC (1<<31) LOCKED_LINE_NUM; (unsigned long)func1; ltagboot (tmp 0x00c00000) 0x9fc????? 0x9d0????? CHETAG (ltagboot<<31) (tmp 0x0007fff0) locked invalid
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4.3.2 PRELOAD BEHAVIOR 4.3.3 ADDRESS MASK
Application code direct prefetch module preform preload cache line lock with instructions data from flash. Preload function uses CHEACC.CHEIDX register field select cache line into which load directed. Setting CHEACC.CHEWEN enables writes CHETAG register. Writing CHETAG.LVALID CHETAG.LLOCK causes preload request prefetch module. controller acknowledges request cycle after write possible stops outstanding flash access stalls load from cache Flash. When finished stalled previous transaction, initiates flash read fetch instructions data requested using address CHETAG.LTAG. After programmed number wait states defined CHECON.PFMWS, controller updates data array with values read from flash. update sets CHETAG.LVALID state line affected. Once controller finishes updating cache, allows requests complete. this request misses cache, controller initiates flash read which incurs full flash access time. Cache lines allow masking address address force match corresponding bits. CHEMSK.LMASK field compliment interrupt vector spacing field CPU. This feature allows boot code lock first four instruction vector cache. vectors contain identical instructions their first four locations, then setting CHEMSK.LMASK match vector spacing LTAG match vector base address causes vector addresses cache. prefetch module responds with zero wait states immediately initiates fetch next four instruction requesting vector prefetch enabled. Using CHEMSK.LMASK restricted aligned address ranges. size allows range 32KB minimum spacing 32B. Using lines, conjunction provides ability have different ranges different spacing. Setting address mask such that more than line will match address causes undefined results. Therefore, highly recommended masking before entering cacheable code.
EXAMPLE 4-3:
EXAMPLE CODE: DUPLICATION CODE USING MASK REGISTERS
#define INT_LINE_NUM CHEACC (1<<31) INT_LINE_NUM; (unsigned long)intbase; ltagboot (tmp 0x00c00000) 0x9fc????? 0x9d0????? CHETAG (ltagboot<<31) (tmp 0x0007fff0) locked invalid CHEMSK 0xe0; first instructions intbase() replicated times 32-byte boundaries
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4.3.4 PREDICTIVE PREFETCH BEHAVIOR 4.3.5 COHERENCY SUPPORT
When configured predictive prefetch cacheable addresses, module predicts next line address returns into pseudo line cache. enabled, prefetch function starts predicting based first instruction fetch. When first line placed cache, module simply increments address next 16-byte aligned address starts flash access. When running linear code (i.e. jumps), flash returns next instructions into prefetch buffer before instructions executed from previous line. time during predicted flash access, address does match predicted one, flash access will changed correct address. This behavior does cause access take longer than without prediction. access that misses cache hits prefetch buffer, instructions placed pseudo line along with address tag. pseudo value marked most recently used line other lines updated accordingly. access misses both cache prefetch buffer, access passes flash those returning instructions placed pseudo line. When configured predictive prefetch non-cacheable addresses, controller only uses prefetch buffer. cache line updated hits fills cache remains intact. linear code, enabling predictive prefetch non-cacheable addresses allows fetch instructions zero wait states. useful non-cacheable predictive prefetching when accesses flash zero wait states. controller holds prefetched instructions output flash clock cycles (while fetching from buffer). This consumes more power without benefit zero wait state flash accesses. Predictive data prefetching supported. However, data access middle predictive instruction fetch causes prefetch controller stop flash access instruction fetch start data load from flash. predictive prefetch does resume, instead waits another instruction fetch. which time, either fills buffer because miss, starts prefetch because hit. possible execute cache while programming flash memory. flash controller stalls cache during programming sequence. Therefore, user code that initiates programming sequence must located cacheable address region. CHECON.CHECOH then coherency strictly supported invalidating, unlocking, clearing masks lines whenever Flash Program Memory written programmed. CHECON.CHECOH then only lines that locked forced invalid. Lines that locked retained.
Prefetch Module Interrupts Exceptions
prefetch module does generate interrupts. Exceptions occur cache lines marked valid manually writing individual CHETAG registers then executing code that hits these lines containing invalid instructions. Also manually placing data into un-locked cache line cause coherency problem from eviction cache miss middle loading algorithm.
4.4.1
CONFIGURATION
prefetch module does external pins.
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NOTES:
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Note:
DIRECT MEMORY ACCESS (DMA) CONTROLLER
This data sheet summarizes features PIC32MX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description this peripheral.
PIC32MX Direct Memory Access (DMA) controller master module useful data transfers between different devices without intervention. source destination transfer memory mapped modules existent PIC32MX (such Peripheral (PBUS) devices: SPI, UART, I2CTM, etc.) memory itself. Following some features controller module: Four Identical Channels, each featuring: Auto-Increment Source Destination Address registers Source Destination Pointers Automatic Word-Size Detection: Transfer granularity down byte level Bytes need word-aligned source destination Fixed Priority Channel Arbitration Flexible Channel Operating modes: Manual (software) automatic (interrupt) requests One-Shot Auto-Repeat Block Transfer modes Channel-to-channel chaining
Flexible Requests: request selected from peripheral interrupt sources Each channel select (appropriate) observable interrupt request source transfer abort selected from peripheral interrupt sources Pattern (data) match transfer termination Multiple Channel Status Interrupts: channel block transfer complete Source empty half empty Destination full half full transfer aborted external event Invalid address generated Debug Support Features: Most recent address accessed channel Most recent channel transfer data Generation Module: module assigned available channels module highly configurable Extended Addressing mode: Extended Addressing mode allows large memory memory copies
TABLE 5-1:
CONTROLLER FEATURES
Different Source Destination Sizes Memory Peripheral Transfers Channel Auto-Enable Unaligned Transfers Memory Memory Transfers Channel Chaining Events Start/Stop
Available Modes
Normal Addressing Mode
256B
Extended Addressing Mode
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Calculation
Transfer Length
Pattern Match Detection
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FIGURE 5-1: CONTROLLER BLOCK DIAGRAM
Controller
System
Peripheral
Address Decoder
Channel Control
Channel Control
Interface
Device Arbitration
Global Control (DMACON)
Channel Control
Channel Priority Arbitration
Controller Registers
GLOBAL SUMMARY
Name DMACON 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 SIDL 28/20/12/4 SUSPEND 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
TABLE 5-2:
Virtual Address BF88_3000
BF88_3004 BF88_3008 BF88_300C BF88_3010
DMACONCLR DMACONSET DMACONINV DMASTAT
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DMACON, read yields undefined value Write sets selected bits DMACON, read yields undefined value Write inverts selected bits DMACON, read yields undefined value RDWR
DMACH<1:0>
BF88_3020
DMAADDR
31:24 23:16 15:8
DMAADDR<31:24> DMAADDR<23:16> DMAADDR<15:8> DMAADDR<7:0>
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TABLE 5-3:
Virtual Address BF88_3030
SUMMARY
Name 31/23/15/7 31:24 23:16 15:8 CRCEN 30/22/14/6 CRCAPP 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 PLEN<4:0> CRCCH<1:0> 25/17/9/1 24/16/8/0
DCRCCON
BF88_3034 DCRCCONCLR BF88_3038 DCRCCONSET BF88_303C DCRCCONINV BF88_3040 DCRCDATA
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DCRCCON, read yields undefined value Write sets selected bits DCRCCON, read yields undefined value Write inverts selected bits DCRCCON, read yields undefined value
DCRCDATA<15:8> DCRCDATA<7:0> Write clears selected bits DCRCDATA, read yields undefined value Write sets selected bits DCRCDATA, read yields undefined value Write inverts selected bits DCRCDATA, read yields undefined value
BF88_3044 DCRCDATACLR BF88_3048 DCRCDATASET BF88_304C DCRCDATAINV BF88_3050 DCRCXOR
31:0 31:0 31:0 31:24 23:16 15:8
DCRCXOR<15:8> DCRCXOR<7:0> Write clears selected bits DCRCXOR, read yields undefined value Write sets selected bits DCRCXOR, read yields undefined value Write inverts selected bits DCRCXOR, read yields undefined value
BF88_3054 DCRCXORCLR BF88_3058 DCRCXORSET BF88_305C DCRCXORINV
31:0 31:0 31:0
TABLE 5-4:
Virtual Address BF88_3060
CHANNEL SUMMARY
Name DCH0CON 31:24 23:16 15:8 31/23/15/7 CHEN 30/22/14/6 CHAED 29/21/13/5 CHCHN 28/20/12/4 CHAEN 27/19/11/3 CHXM 26/18/10/2 CHEDET 25/17/9/1 24/16/8/0 CHCHNS
CHPRI<1:0>
BF88_3064 BF88_3068 BF88_306C BF88_3070
DCH0CONCLR DCH0CONSET DCH0CONINV DCH0ECON
31:0 31:0 31:0 31:24 23:16 15:8 CFORCE
Write clears selected bits DCH0CON, read yields undefined value Write sets selected bits DCH0CON, read yields undefined value Write inverts selected bits DCH0CON, read yields undefined value CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN Write clears selected bits DCH0ECON, read yields undefined value Write sets selected bits DCH0ECON, read yields undefined value Write inverts selected bits DCH0ECON, read yields undefined value CHSDIE CHSDIF CHSHIE CHSHIF CHDDIE CHDDIF CHDHIE CHDHIF CHBCIE CHBCIF CHCCIE CHCCIF CHTAIE CHTAIF CHERIE CHERIF
BF88_3074 DCH0ECONCLR BF88_3078 DCH0ECONSET BF88_307C DCH0ECONINV BF88_3080 DCH0INT
31:0 31:0 31:0 31:24 23:16 15:8
BF88_3084 BF88_3088 BF88_308C BF88_3090
DCH0INTCLR DCH0INTSET DCH0INTINV DCH0SSA
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DCH0INT, read yields undefined value Write sets selected bits DCH0INT, read yields undefined value Write inverts selected bits DCH0INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits DCH0SSA, read yields undefined value Write sets selected bits DCH0SSA, read yields undefined value Write inverts selected bits DCH0SSA, read yields undefined value
BF88_3094 BF88_3098 BF88_309C Note
DCH0SSACLR DCH0SSASET DCH0SSAINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
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TABLE 5-4:
Virtual Address BF88_30A0
CHANNEL SUMMARY (CONTINUED)
Name DCH0DSA 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits DCH0DSA, read yields undefined value Write sets selected bits DCH0DSA, read yields undefined value Write inverts selected bits DCH0DSA, read yields undefined value
BF88_30A4 BF88_30A8 BF88_30AC BF88_30B0
DCH0DSACLR DCH0DSASET DCH0DSAINV DCH0SSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHSSIZ<7:0> Write clears selected bits DCH0SSIZ, read yields undefined value Write sets selected bits DCH0SSIZ, read yields undefined value Write inverts selected bits DCH0SSIZ, read yields undefined value
BF88_30B4 DCH0SSIZCLR BF88_30B8 BF88_30BC BF88_30C0 DCH0SSIZSET DCH0SSIZINV DCH0DSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits DCH0DSIZ, read yields undefined value Write sets selected bits DCH0DSIZ, read yields undefined value Write inverts selected bits DCH0DSIZ, read yields undefined value
BF88_30C4 DCH0DSIZCLR BF88_30C8 DCH0DSIZSET BF88_30CC BF88_30D0 DCH0DSIZINV DCH0SPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHSPTR<7:0>
BF88_30E0
DCH0DPTR
31:24 23:16 15:8
CHDPTR<15:8>(2) CHDPTR<7:0>
BF88_30F0
DCH0CSIZ
31:24 23:16 15:8
CHCSIZ<7:0> Write clears selected bits DCH0CSIZ, read yields undefined value Write sets selected bits DCH0CSIZ, read yields undefined value Write inverts selected bits DCH0CSIZ, read yields undefined value
BF88_30F4 DCH0CSIZCLR BF88_30F8 DCH0CSIZSET BF88_30FC BF88_3100 DCH0CSIZINV DCH0CPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHCPTR<7:0>
BF88_3110
DCH0DAT
31:24 23:16 15:8
CHPDAT<7:0> Write clears selected bits DCH0DAT, read yields undefined value Write sets selected bits DCH0DAT, read yields undefined value Write inverts selected bits DCH0DAT, read yields undefined value
BF88_3114 BF88_3118 BF88_311C Note
DCH0DATCLR DCH0DATSET DCH0DATINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
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TABLE 5-5:
Virtual Address BF88_1070 BF88_1040 BF88_1120 Note
CHANNEL INTERRUPT REGISTER SUMMARY(1)
Name IEC1 IFS1 IPC9 23:16 23:16 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 DMA3IE DMA3IF DMA0IP<2:0> 26/18/10/2 DMA2IE DMA2IF 25/17/9/1 DMA1IE DMA1IF 24/16/8/0 DMA0IE DMA0IF
DMA0IS<1:0>
This summary table contains partial register definitions that only pertain peripheral. Refer PIC32MX Family Reference Manual (DS61132) detailed description these registers.
TABLE 5-6:
Virtual Address BF88_3120
CHANNEL SUMMARY
Name DCH1CON 31:24 23:16 15:8 31/23/15/7 CHEN 30/22/14/6 CHAED 29/21/13/5 CHCHN 28/20/12/4 CHAEN 27/19/11/3 CHXM 26/18/10/2 CHEDET 25/17/9/1 24/16/8/0 CHCHNS
CHPRI<1:0>
BF88_3124 BF88_3128 BF88_312C BF88_3130
DCH1CONCLR DCH1CONSET DCH1CONINV DCH1ECON
31:0 31:0 31:0 31:24 23:16 15:8 CFORCE
Write clears selected bits DCH1CON, read yields undefined value Write sets selected bits DCH1CON, read yields undefined value Write inverts selected bits DCH1CON, read yields undefined value CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN
BF88_3134 DCH1ECONCLR BF88_3138 DCH1ECONSET BF88_313C DCH1ECONINV BF88_3140 DCH1INT
31:0 31:0 31:0 31:24 23:16 15:8 CHSDIE CHSDIF
Write clears selected bits DCH1ECON, read yields undefined value Write sets selected bits DCH1ECON, read yields undefined value Write inverts selected bits DCH1ECON, read yields undefined value CHSHIE CHSHIF CHDDIE CHDDIF CHDHIE CHDHIF CHBCIE CHBCIF CHCCIE CHCCIF CHTAIE CHTAIF CHERIE CHERIF
BF88_3144 BF88_3148 BF88_314C BF88_3150
DCH1INTCLR DCH1INTSET DCH1INTINV DCH1SSA
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DCH1INT, read yields undefined value Write sets selected bits DCH1INT, read yields undefined value Write inverts selected bits DCH1INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits DCH1SSA, read yields undefined value Write sets selected bits DCH1SSA, read yields undefined value Write inverts selected bits DCH1SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits DCH1DSA, read yields undefined value Write sets selected bits DCH1DSA, read yields undefined value Write inverts selected bits DCH1DSA, read yields undefined value
BF88_3154 BF88_3158 BF88_315C BF88_3160
DCH1SSACLR DCH1SSASET DCH1SSAINV DCH1DSA
31:0 31:0 31:0 31:24 23:16 15:8
BF88_3164 BF88_3168 BF88_316C BF88_3170
DCH1DSACLR DCH1DSASET DCH1DSAINV DCH1SSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHSSIZ<7:0> Write clears selected bits DCH1SSIZ, read yields undefined value Write sets selected bits DCH1SSIZ, read yields undefined value Write inverts selected bits DCH1SSIZ, read yields undefined value
BF88_3174 BF88_3178 BF88_317C Note
DCH1SSIZCLR DCH1SSIZSET DCH1SSIZINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
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TABLE 5-6:
Virtual Address BF88_3180
CHANNEL SUMMARY (CONTINUED)
Name DCH1DSIZ 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits DCH1DSIZ, read yields undefined value Write sets selected bits DCH1DSIZ, read yields undefined value Write inverts selected bits DCH1DSIZ, read yields undefined value
BF88_3184 BF88_3188 BF88_318C BF88_3190
DCH1DSIZCLR DCH1DSIZSET DCH1DSIZINV DCH1SPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHSPTR<7:0>
BF88_31A0
DCH1DPTR
31:24 23:16 15:8
CHDPTR<15:8>(2) CHDPTR<7:0>
BF88_31B0
DCH1CSIZ
31:24 23:16 15:8
CHCSIZ<7:0> Write clears selected bits DCH1CSIZ, read yields undefined value Write sets selected bits DCH1CSIZ, read yields undefined value Write inverts selected bits DCH1CSIZ, read yields undefined value
BF88_31B4 DCH1CSIZCLR BF88_31B8 DCH1CSIZSET BF88_31BC BF88_31C0 DCH1CSIZINV DCH1CPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHCPTR<7:0>
BF88_31D0
DCH1DAT
31:24 23:16 15:8
CHPDAT<7:0> Write clears selected bits DCH1DAT, read yields undefined value Write sets selected bits DCH1DAT, read yields undefined value Write inverts selected bits DCH1DAT, read yields undefined value
BF88_31D4 BF88_31D8 BF88_31DC Note
DCH1DATCLR DCH1DATSET DCH1DATINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
TABLE 5-7:
Virtual Address BF88_1070 BF88_1040 BF88_1120 Note
CHANNEL INTERRUPT REGISTER SUMMARY(1)
Name IEC1 IFS1 IPC9 23:16 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 DMA3IE DMA3IF DMA1IP<2:0> 26/18/10/2 DMA2IE DMA2IF 25/17/9/1 DMA1IE DMA1IF 24/16/8/0 DMA0IE DMA0IF
DMA1IS<1:0>
This summary table contains partial register definitions that only pertain peripheral. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description these registers.
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TABLE 5-8:
Virtual Address(1) BF88_31E0
CHANNEL SUMMARY
Name DCH2CON 31:24 23:16 15:8 31/23/15/7 CHEN 30/22/14/6 CHAED 29/21/13/5 CHCHN 28/20/12/4 CHAEN 27/19/11/3 CHXM 26/18/10/2 CHEDET 25/17/9/1 24/16/8/0 CHCHNS
CHPRI<1:0>
BF88_31E4 BF88_31E8 BF88_31EC BF88_31F0
DCH2CONCLR DCH2CONSET DCH2CONINV DCH2ECON
31:0 31:0 31:0 31:24 23:16 15:8 CFORCE
Write clears selected bits DCH2CON, read yields undefined value Write sets selected bits DCH2CON, read yields undefined value Write inverts selected bits DCH2CON, read yields undefined value CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN Write clears selected bits DCH2ECON, read yields undefined value Write sets selected bits DCH2ECON, read yields undefined value Write inverts selected bits DCH2ECON, read yields undefined value CHSDIE CHSDIF CHSHIE CHSHIF CHDDIE CHDDIF CHDHIE CHDHIF CHBCIE CHBCIF CHCCIE CHCCIF CHTAIE CHTAIF CHERIE CHERIF
BF88_31F4 BF88_31F8 BF88_31FC BF88_3200
DCH2ECONCLR DCH2ECONSET DCH2ECONINV DCH2INT
31:0 31:0 31:0 31:24 23:16 15:8
BF88_3204 BF88_3208 BF88_320C BF88_3210
DCH2INTCLR DCH2INTSET DCH2INTINV DCH2SSA
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DCH2INT, read yields undefined value Write sets selected bits DCH2INT, read yields undefined value Write inverts selected bits DCH2INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits DCH2SSA, read yields undefined value Write sets selected bits DCH2SSA, read yields undefined value Write inverts selected bits DCH2SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits DCH2DSA, read yields undefined value Write sets selected bits DCH2DSA, read yields undefined value Write inverts selected bits DCH2DSA, read yields undefined value
BF88_3214 BF88_3218 BF88_321C BF88_3220
DCH2SSACLR DCH2SSASET DCH2SSAINV DCH2DSA
31:0 31:0 31:0 31:24 23:16 15:8
BF88_3224 BF88_3228 BF88_322C BF88_3230
DCH2DSACLR DCH2DSASET DCH2DSAINV DCH2SSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHSSIZ<7:0> Write clears selected bits DCH2SSIZ, read yields undefined value Write sets selected bits DCH2SSIZ, read yields undefined value Write inverts selected bits DCH2SSIZ, read yields undefined value
BF88_3234 BF88_3238 BF88_323C BF88_3240
DCH2SSIZCLR DCH2SSIZSET DCH2SSIZINV DCH2DSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits DCH2DSIZ, read yields undefined value Write sets selected bits DCH2DSIZ, read yields undefined value Write inverts selected bits DCH2DSIZ, read yields undefined value
BF88_3244 BF88_3248 BF88_324C Note
DCH2DSIZCLR DCH2DSIZSET DCH2DSIZINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
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TABLE 5-8:
Virtual Address(1) BF88_3250
CHANNEL SUMMARY (CONTINUED)
Name DCH2SPTR 31:24 23:16 15:8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
CHSPTR<7:0>
BF88_3260
DCH2DPTR
31:24 23:16 15:8
CHDPTR<15:8>(2) CHDPTR<7:0>
BF88_3270
DCH2CSIZ
31:24 23:16 15:8
CHCSIZ<7:0> Write clears selected bits DCH2CSIZ, read yields undefined value Write sets selected bits DCH2CSIZ, read yields undefined value Write inverts selected bits DCH2CSIZ, read yields undefined value
BF88_3274 BF88_3278 BF88_327C BF88_3280
DCH2CSIZCLR DCH2CSIZSET DCH2CSIZINV DCH2CPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHCPTR<7:0>
BF88_3290
DCH2DAT
31:24 23:16 15:8
CHPDAT<7:0> Write clears selected bits DCH2DAT, read yields undefined value Write sets selected bits DCH2DAT, read yields undefined value Write inverts selected bits DCH2DAT, read yields undefined value
BF88_3294 BF88_3298 BF88_329C Note
DCH2DATCLR DCH2DATSET DCH2DATINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
TABLE 5-9:
Virtual Address BF88_1070 BF88_1040 BF88_1120 Note
CHANNEL INTERRUPT REGISTER SUMMARY(1)
Name IEC1 IFS1 IPC9 23:16 23:16 23:16 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 DMA3IE DMA3IF DMA2IP<2:0> 26/18/10/2 DMA2IE DMA2IF 25/17/9/1 DMA1IE DMA1IF 24/16/8/0 DMA0IE DMA0IF
DMA2IS<1:0>
This summary table contains partial register definitions that only pertain peripheral. Refer PIC32MX Family Reference Manual (DS61132) detailed description these registers.
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TABLE 5-10:
Virtual Address(1) BF88_32A0
CHANNEL SUMMARY
Name 31/23/15/7 31:24 23:16 15:8 CHEN 30/22/14/6 CHAED 29/21/13/5 CHCHN 28/20/12/4 CHAEN 27/19/11/3 CHXM 26/18/10/2 CHEDET 25/17/9/1 24/16/8/0 CHCHNS
DCH3CON
CHPRI<1:0>
BF88_32A4 DCH3CONCLR BF88_32A8 BF88_32AC BF88_32B0 DCH3CONSET DCH3CONINV DCH3ECON
31:0 31:0 31:0 31:24 23:16 15:8 CFORCE
Write clears selected bits DCH3CON, read yields undefined value Write sets selected bits DCH3CON, read yields undefined value Write inverts selected bits DCH3CON, read yields undefined value CHAIRQ<7:0> CHSIRQ<7:0> CABORT PATEN SIRQEN AIRQEN Write clears selected bits DCH3ECON, read yields undefined value Write sets selected bits DCH3ECON, read yields undefined value Write inverts selected bits DCH3ECON, read yields undefined value CHSDIE CHSDIF CHSHIE CHSHIF CHDDIE CHDDIF CHDHIE CHDHIF CHBCIE CHBCIF CHCCIE CHCCIF CHTAIE CHTAIF CHERIE CHERIF
BF88_32B4 DCH3ECONCLR BF88_32B8 DCH3ECONSET BF88_32BC DCH3ECONINV BF88_32C0 DCH3INT
31:0 31:0 31:0 31:24 23:16 15:8
BF88_32C4 BF88_32C8 BF88_32CC BF88_32D0
DCH3INTCLR DCH3INTSET DCH3INTINV DCH3SSA
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits DCH3INT, read yields undefined value Write sets selected bits DCH3INT, read yields undefined value Write inverts selected bits DCH3INT, read yields undefined value CHSSA<31:24> CHSSA<23:16> CHSSA<15:8> CHSSA<7:0> Write clears selected bits DCH3SSA, read yields undefined value Write sets selected bits DCH3SSA, read yields undefined value Write inverts selected bits DCH3SSA, read yields undefined value CHDSA<31:24> CHDSA<23:16> CHDSA<15:8> CHDSA<7:0> Write clears selected bits DCH3DSA, read yields undefined value Write sets selected bits DCH3DSA, read yields undefined value Write inverts selected bits DCH3DSA, read yields undefined value
BF88_32D4 BF88_32D8 BF88_32DC BF88_32E0
DCH3SSACLR DCH3SSASET DCH3SSAINV DCH3DSA
31:0 31:0 31:0 31:24 23:16 15:8
BF88_32E4 BF88_32E8 BF88_32EC BF88_32F0
DCH3DSACLR DCH3DSASET DCH3DSAINV DCH3SSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHSSIZ<7:0> Write clears selected bits DCH3SSIZ, read yields undefined value Write sets selected bits DCH3SSIZ, read yields undefined value Write inverts selected bits DCH3SSIZ, read yields undefined value
BF88_32F4 DCH3SSIZCLR BF88_32F8 BF88_32FC BF88_3300 DCH3SSIZSET DCH3SSIZINV DCH3DSIZ
31:0 31:0 31:0 31:24 23:16 15:8
CHDSIZ<15:8>(2) CHDSIZ<7:0> Write clears selected bits DCH3DSIZ, read yields undefined value Write sets selected bits DCH3DSIZ, read yields undefined value Write inverts selected bits DCH3DSIZ, read yields undefined value
BF88_3304 BF88_3308 BF88_330C BF88_3310
DCH3DSIZCLR DCH3DSIZSET DCH3DSIZINV DCH3SPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHSPTR<7:0>
Note
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
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TABLE 5-10:
Virtual Address(1) BF88_3320
CHANNEL SUMMARY (CONTINUED)
Name 31/23/15/7 31:24 23:16 15:8 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
DCH3DPTR
CHDPTR<15:8>(2) CHDPTR<7:0>
BF88_3330
DCH3CSIZ
31:24 23:16 15:8
CHCSIZ<7:0> Write clears selected bits DCH3CSIZ, read yields undefined value Write sets selected bits DCH3CSIZ, read yields undefined value Write inverts selected bits DCH3CSIZ, read yields undefined value
BF88_3334 BF88_3338 BF88_333C BF88_3340
DCH3CSIZCLR DCH3CSIZSET DCH3CSIZINV DCH3CPTR
31:0 31:0 31:0 31:24 23:16 15:8
CHCPTR<7:0>
BF88_3350
DCH3DAT
31:24 23:16 15:8
CHPDAT<7:0> Write clears selected bits DCH3DAT, read yields undefined value Write sets selected bits DCH3DAT, read yields undefined value Write inverts selected bits DCH3DAT, read yields undefined value
BF88_3354 BF88_3358 BF88_335C Note
DCH3DATCLR DCH3DATSET DCH3DATINV
31:0 31:0 31:0
starting address registers channel 0xbf883060 0xc0*n. These bits relevant Extended Addressing mode only.
TABLE 5-11:
Virtual Address BF88_1070 BF88_1040 BF88_1120 Note
CHANNEL INTERRUPT REGISTER SUMMARY
Name IEC1 IFS1 IPC9 23:16 23:16 31:24 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 DMA3IE DMA3IF DMA3IP<2:0> 26/18/10/2 DMA2IE DMA2IF 25/17/9/1 DMA1IE DMA1IF 24/16/8/0 DMA0IE DMA0IF
DMA3IS<1:0>
This summary table contains partial register definitions that only pertain peripheral. Refer PIC32MX Family Reference Manual (DS61132) detailed description these registers.
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REGISTER 5-1:
R/W-0 Legend: Readable Unimplemented 31-16 Writable Value POR: (`0', `1', Unknown) R/W-0 R/W-0 SIDL R/W-0 SUSPEND
DMACON: CONTROLLER CONTROL REGISTER
Unimplemented: Read module enabled module disabled FRZ: Freeze bit(1) frozen during Debug mode continues during Debug mode Note: writable Debug Exception mode only, forced Normal mode. SIDL: Stop Idle Mode transfers frozen during Sleep transfers continue during Sleep SUSPEND: Suspend transfers suspended allow uninterrupted access data operates normally Unimplemented: Read
11-0
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REGISTER 5-2:
Legend: Readable Unimplemented 31-4 Writable Value POR: (`0', `1', Unknown) RDWR
DMASTAT: STATUS REGISTER(1)
DMACH<1:0>
Unimplemented: Read RDWR: Read/Write Status Last access read Last access write Unimplemented: Read DMACH<1:0>: Channel bits This register contains value most recent active channel.
Note
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REGISTER 5-3:
Legend: Readable Unimplemented 31-0 Note Writable Value POR: (`0', `1', Unknown)
DMAADDR: ADDRESS REGISTER(1)
DMAADDR<31:24>
DMAADDR<23:16>
DMAADDR<15:8>
DMAADDR<7:0>
DMAADDR<31:0>: Module Address bits This register contains address most recent access.
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REGISTER 5-4:
R/W-0 CRCEN Legend: Readable Unimplemented 31-13 12-8 Writable Value POR: (`0', `1', Unknown) R/W-0 CRCAPP R/W-0 R/W-0 R/W-0 R/W-0 PLEN<4:0> R/W-0 R/W-0
DCRCCON: CONTROL REGISTER
R/W-0
CRCCH<1:0>
Unimplemented: Read PLEN<4:0>: Polynomial Length bits Denotes length polynomial CRCEN: Enable module enabled channel transfers routed through module module disabled channel transfers proceed normally CRCAPP: Append Mode Data read will passed CRC, included calculation, written destination register. When block transfer completes, calculated will written location given DCHxDSA Channel behaves normally, with being calculated data transferred from source destination Unimplemented: Read CRCCH<1:0>: Channel Select bits assigned Channel assigned Channel assigned Channel assigned Channel
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REGISTER 5-5:
R/W-0 R/W-0 Legend: Readable Unimplemented 31-16 15-0 Writable Value POR: (`0', `1', Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCDATA: DATA REGISTER
R/W-0 R/W-0
DCRCDATA<15:8>
DCRCDATA<7:0>
Unimplemented: Read DCRCDATA<15:0>: Data Register bits Writing this register will seed generator. Reading from this register will return current value CRC. Bits PLEN will return read.
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REGISTER 5-6:
R/W-0 R/W-0 Legend: Readable Unimplemented 31-16 15-0 Writable Value POR: (`0', `1', Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCXOR: ENABLE REGISTER(1)
R/W-0 R/W-0
DCRCXOR<15:8>
DCRCXOR<7:0>
Unimplemented: Read DCRCXOR<15:0>: Register bits Enable input Shift register Disable input Shift register; data shifted directly from previous stage register DCRCXOR register will always set.
Note
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REGISTER 5-7:
R/W-0 CHEN Legend: Readable Unimplemented 31-9 Writable Value POR: (`0', `1', Unknown) R/W-0 CHAED R/W-0 CHCHN R/W-0 CHAEN R/W-0 CHXM CHEDET R/W-0
DCHXCON: CHANNEL CONTROL REGISTER
R/W-0 CHCHNS R/W-0
CHPRI<1:0>
Unimplemented: Read CHCHNS: Chain Channel Selection Chain channel lower natural priority (CH1 will enabled transfer complete) Chain channel higher natural priority (CH1 will enabled transfer complete) Note: chain selection takes effect when chaining enabled, i.e., CHCHN CHEN: Channel Enable Channel enabled Channel disabled CHAED: Channel Allow Events Disabled Channel start/abort events will registered, even channel disabled Channel start/abort events will ignored channel disabled CHCHN: Channel Chain Enable Allow channel chained channel higher natural priority chain channel higher natural priority CHAEN: Channel Automatic Enable Channel continuously enabled, automatically disabled after block transfer complete Channel disabled block transfer complete CHXM: Channel Extended Addressing Mode Enable Extended Addressing mode enabled Extended Addressing mode disabled CHEDET: Channel Event Detected event been detected events have been detected CHPRI<1:0>: Channel Priority bits Channel priority (highest) Channel priority Channel priority Channel priority
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REGISTER 5-8:
R/W-1 R/W-1 CFORCE Legend: Readable Unimplemented 31-24 23-16 Writable Value POR: (`0', `1', Unknown) CABORT R/W-0 PATEN R/W-0 SIRQEN R/W-0 AIRQEN R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
DCHXECON: CHANNEL EVENT CONTROL REGISTER
R/W-1 R/W-1
CHAIRQ<7:0>
CHSIRQ<7:0>
Unimplemented: Read CHAIRQ<7:0>: that will abort Channel Transfer bits 11111111 Interrupt will abort transfers progress CHAIF flag 00000001 Interrupt will abort transfers progress CHAIF flag 00000000 Interrupt will abort transfers progress CHAIF flag
15-8
CHSIRQ<7:0>: that will Start Channel Transfer bits 11111111 Interrupt will initiate transfer 00000001 Interrupt will initiate transfer 00000000 Interrupt will initiate transfer
CFORCE: Forced Transfer transfer forced begin when this written This always reads CABORT: Abort Transfer transfer aborted when this written This always reads PATEN: Channel Pattern Match Abort Enable Abort transfer clear CHEN pattern match Pattern match disabled SIRQEN: Channel Start Enable Start channel cell transfer interrupt matching CHSIRQ occurs Interrupt number CHSIRQ ignored does start transfer
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REGISTER 5-8:
DCHXECON: CHANNEL EVENT CONTROL REGISTER (CONTINUED)
AIRQEN: Channel Abort Enable Channel transfer aborted interrupt matching CHAIRQ occurs Interrupt number CHAIRQ ignored does terminate transfer Unimplemented: Read
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REGISTER 5-9:
R/W-0 CHSDIE R/W-0 CHSDIF Legend: Readable Unimplemented 31-24 Writable Value POR: (`0', `1', Unknown) R/W-0 CHSHIF R/W-0 CHDDIF R/W-0 CHDHIF R/W-0 CHBCIF R/W-0 CHCCIF R/W-0 CHTAIF R/W-0 CHSHIE R/W-0 CHDDIE R/W-0 CHDHIE R/W-0 CHBCIE R/W-0 CHCCIE R/W-0 CHTAIE
DCHXINT: CHANNEL INTERRUPT CONTROL REGISTER
R/W-0 CHERIE R/W-0 CHERIF
Unimplemented: Read CHSDIE: Channel Source Done Interrupt Enable Interrupt enabled Interrupt disabled CHSHIE: Channel Source Half Empty Interrupt Enable Interrupt enabled Interrupt disabled CHDDIE: Channel Destination Done Interrupt Enable Interrupt enabled Interrupt disabled CHDHIE: Channel Destination Half Full Interrupt Enable Interrupt enabled Interrupt disabled CHBCIE: Channel Block Transfer Complete Interrupt Enable Interrupt enabled Interrupt disabled CHCCIE: Channel Cell Transfer Complete Interrupt Enable Interrupt enabled Interrupt disabled CHTAIE: Channel Transfer Abort Interrupt Enable Interrupt enabled Interrupt disabled CHERIE: Channel Address Error Interrupt Enable Interrupt enabled Interrupt disabled Unimplemented: Read
15-8
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REGISTER 5-9:
DCHXINT: CHANNEL INTERRUPT CONTROL REGISTER (CONTINUED)
CHSDIF: Channel Source Done Interrupt Flag Channel Source Pointer reached source (CHSPTR CHSSIZ) interrupt pending CHSHIF: Channel Source Half Empty Interrupt Flag Channel Source Pointer reached midpoint source (CHSPTR CHSSIZ/2) interrupt pending CHDDIF: Channel Destination Done Interrupt Flag Channel Destination Pointer reached destination (CHDPTR CHDSIZ) interrupt pending CHDHIF: Channel Destination Half Full Interrupt Flag Channel Destination Pointer reached midpoint destination (CHDPTR CHDSIZ/2) interrupt pending CHBCIF: Channel Block Transfer Complete Interrupt Flag block transfer been completed (the larger CHSSIZ/CHDSIZ bytes been transferred) pattern match event occurs interrupt pending CHCCIF: Channel Cell Transfer Complete Interrupt Flag cell transfer been completed (CHCSIZ bytes have been transferred) interrupt pending CHTAIF: Channel Transfer Abort Interrupt Flag interrupt matching CHAIRQ been detected transfer been aborted interrupt pending CHERIF: Channel Address Error Interrupt Flag channel address error been detected Either source destination address invalid. interrupt pending
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REGISTER 5-10:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXSSA: CHANNEL SOURCE START ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHSSA<31:24>
CHSSA<23:16>
CHSSA<15:8>
CHSSA<7:0>
CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must physical address source.
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REGISTER 5-11:
R/W-x R/W-x R/W-x R/W-x Legend: Readable Unimplemented 31-0 Writable Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXDSA: CHANNEL DESTINATION START ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHDSA<31:24>
CHDSA<23:16>
CHDSA<15:8>
CHDSA<7:0>
CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must physical address destination.
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REGISTER 5-12:
R/W-x Legend: Readable Unimplemented 31-8 Writable Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXSSIZ: CHANNEL SOURCE SIZE REGISTER
R/W-x
CHSSIZ<7:0>
Unimplemented: Read CHSSIZ<7:0>: Channel Source Size bits CHXM (DCHxCON<3>) (Normal Addressing mode): 255-byte source size 2-byte source size 1-byte source size 256-byte source size CHXM (DCHxCON<3>) (Extended Addressing mode): These bits make Most Significant bits transfer size.
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REGISTER 5-13:
R/W-x Legend: Readable Unimplemented 31-16 15-0 Writable Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXDSIZ: CHANNEL DESTINATION SIZE REGISTER
R/W-x
CHDSIZ<15:8>
CHDSIZ<7:0>
Unimplemented: Read CHDSIZ<15:0>: Channel Destination Size bits CHXM (DCHxCON<3>) (Normal Addressing mode): CHDSIZ<15:8> Unused, read `0', write effect. CHDSIZ<7:0> Read/Write Normal mode transfer size: 255-byte destination size 2-byte destination size 1-byte destination size 256-byte destination size CHXM (DCHxCON<3>) (Extended Addressing mode): CHDSIZ<15:0> Read Extended mode transfer size: 65535 65535-byte destination size 2-byte destination size 1-byte destination size 65536-byte destination size. CHDSIZ<15:8> write effect. CHDSIZ<7:0> write sets Extended mode transfer size.
2007 Microchip Technology Inc.
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REGISTER 5-14:
Legend: Readable Unimplemented 31-8 Writable Value POR: (`0', `1', Unknown)
DCHXSPTR: CHANNEL SOURCE POINTER REGISTER
CHSPTR<7:0>
Unimplemented: Read CHSPTR<7:0>: Channel Source Pointer bits CHXM (DCHxCON<3>) (Normal Addressing mode): Points 255th byte source Points byte source Points byte source CHXM (DCHxCON<3>) (Extended Addressing mode): These bits comprise Most Significant bits pointer. Note: This reset pattern detect, when Pattern Detect mode.
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REGISTER 5-15:
Legend: Readable Unimplemented 31-16 15-0 Writable Value POR: (`0', `1', Unknown)
DCHXDPTR: CHANNEL DESTINATION POINTER REGISTER
CHDPTR<15:8>
CHDPTR<7:0>
Unimplemented: Read CHDPTR<15:0>: Channel Destination Pointer bits CHXM (DCHxCON<3>) (Normal Addressing mode): CHDPTR<15:8> Unused, read `0'. CHDPTR<7:0> Normal Mode Destination Pointer: Points 255th byte destination Points byte destination Points byte destination CHXM (DCHxCON<3>) (Extended Addressing mode): CHDPTR<15:0> Extended Mode Destination Pointer: 65535 Points byte 65535 (0xFFFF) source/destination Points byte source/destination Points byte source/destination Points byte source/destination
2007 Microchip Technology Inc.
DS61143A-page
PIC32MX FAMILY
REGISTER 5-16:
R/W-x Legend: Readable Unimplemented 31-8 Writable Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXCSIZ: CHANNEL CELL-SIZE REGISTER
R/W-x
CHCSIZ<7:0>
Unimplemented: Read CHCSIZ<7:0>: Channel Cell Size bits CHXM (DCHxCON<3>) (Normal Addressing mode): bytes transferred event bytes transferred event byte transferred event bytes transferred event CHXM (DCHxCON<3>) (Extended Addressing mode): These bits used Extended Addressing mode.
DS61143A-page
2007 Microchip Technology Inc.
PIC32MX FAMILY
REGISTER 5-17:
Legend: Readable Unimplemented 31-8 Writable Value POR: (`0', `1', Unknown)
DCHXCPTR: CHANNEL CELL POINTER REGISTER
CHCPTR<7:0>
Unimplemented: Read CHCPTR<7:0>: Channel Cell Progress Pointer bits CHXM (DCHxCON<3>) (Normal Addressing mode): Bytes have been transferred since last event Bytes have been transferred since last event Bytes have been transferred since last event CHXM (DCHxCON<3>) (Extended Addressing mode): These bits used Extended Addressing mode. Note: This reset pattern detect, when Pattern Detect mode
2007 Microchip Technology Inc.
DS61143A-page
PIC32MX FAMILY
REGISTER 5-18:
R/W-x Legend: Readable Unimplemented 31-8 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DCHXDAT: CHANNEL PATTERN DATA REGISTER
R/W-x
CHPDAT<7:0>
Unimplemented: Read CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data matched must stored this register allow terminate match. other modes: Unused.
DS61143A-page
2007 Microchip Technology Inc.
PIC32MX FAMILY
Controller Operation
channel will transfer data from source destination without intervention. controller configuration resources: Controller corresponding channel have enabled using (DMACON<15>) CHEN (DCHxCON<7>) bits. source destination transfer programmable using DCHxSSA DCHxDSA registers respectively. source destination further independently configurable using DCHxSSIZ DCHxDSIZ registers. transfer initiated ways: Software initiate transfer setting channel CFORCE (DCHxECON<7>) bit. interrupt event occurs that matches CHSIRQ (DCHxECON<15:8>) interrupt SIRQEN (DCHxECON<4>). user select interrupt device start transfer. each event requiring transfer, number bytes specified cell size (DCHxCSIZ) will transferred (one more transactions will occur). channel keeps track number bytes transferred from source destination, using Source Destination Pointers (DCHxSPTR DCHxDPTR). Source Destination Pointers readonly updated after every transaction. Interrupts generated when Source Destination pointer half source destination size (DCHxSSIZ/2 DCHxDSIZ/2), when source destination counter equals size source destination. These interrupts CHSHIF, CHDHIF CHSDIF, CHDDIF, respectively. Source Destination Pointers reset: device Reset. When turned (DMACON<15>) `0').
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