Data Sheet December 2007 FN6611.0 Standard Buck Regulator IS

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Data Sheet December 2007 FN6611.0 Standard Buck Regulator IS

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ISL8500
Data Sheet December 2007 FN6611.0
Standard Buck Regulator
ISL8500 high-performance, simple output controller that provides single, high frequency power solution variety point-of-load applications. ISL8500 integrates standard buck controller switching MOSFET. controller ISL8500 drives internal switching N-Channel power MOSFET requires external Schottky diode generate output voltage from 0.6V 19V. integrated power switch optimized excellent thermal performance output current. standard buck input voltage range supports fixed variable 5.5V range. regulator switches fixed frequency 500kHz utilizes simple voltage mode control with input voltage feed forward provide flexibility component selection minimize solution size. Protection features include overcurrent, undervoltage thermal overload protection integrated into ISL8500 power good signal output indicates loss regulation output. ISL8500 available small 4mmx3mm Dual Flat No-Lead (DFN) package.
Features
Standard Buck Controller with Integrated Switching Power MOSFET Integrated Boot Diode Input Voltage Range Fixed ±10% Variable 5.5V Output Voltage Adjustable from 0.6V with Continuous Output Current Tolerance Voltage Mode Control with Voltage Feed Forward Fixed 500kHz Switching Frequency Externally Adjustable Soft-Start Time Output Undervoltage Protection Enable Inputs PGOOD Output Overcurrent Protection Thermal Overload Protection
Ordering Information
PART NUMBER (Note) ISL8500IRZ PART TEMP. MARKING RANGE (°C) 500Z PACKAGE (Pb-free) PKG. DWG. L12.4x3 L12.4x3
Internal regulator
Applications
General Purpose WLAN Cards-PCMCIA, Cardbus32, MiniPCI Cards-Compact Flash Cards Hand-Held Instruments Panel Set-top
ISL8500IRZ-T* 500Z
*Please refer TB347 details reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate PLUS ANNEAL termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Pinout
ISL8500 DFN) VIEW
COMP
PHASE PHASE BOOT
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. Rights Reserved other trademarks mentioned property their respective owners.
ISL8500 Typical Application Schematic
10pF 100pF VOUT 3.16k 2.2nF 51.1k COMP
0.1F
10uF
5.5V
ISL8500
PHASE 0.1F
VOUT 2.5V 100F B340LB
BOOT
FIGURE RANGE FROM 5.5V
FN6611.0 December 2007
ISL8500 Functional Block Diagram
COMP BOOT SOFT-START CONTROL MONITOR (x2) GATE DRIVE 30µA THERMAL MONITOR +150°C MONITOR POWER-ON RESET MONITOR VOLTAGE MONITOR 0.6V REFERENCE FAULT MONITOR RAMP GENERATOR
PHASE (x2)
OSCILLATOR
EPAD
FN6611.0 December 2007
ISL8500
Absolute Maximum Ratings (Note
-0.3V BOOT -0.3V BOOT PHASE -0.03V VDD, COMP, -0.3V
Thermal Information
Thermal Resistance (°C/W) (°C/W) Package (Notes Ambient Temperature Range. .-40°C +85°C Junction Temperature Range. .-40°C +125°C Storage Temperature Range .-65°C +150°C Pb-free reflow profile .see link below
Recommended Operating Conditions
Supply Voltage Range 4.5V Load Current Range Ambient Temperature Range -40°C +85°
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTES: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379 details. "case temp" location center exposed metal package underside. Tech Brief TB379 details. Test Condition: 15V, forced above regulation point (0.6V), switching, power MOSFET gate charging current included. Excluding blanking time. Specifications -40°C +85°C established +25°C test with margin limits.
Electrical Specifications
Unless Otherwise Noted, Parameter Limits Established Over Recommended Operating Conditions Typical Specifications Measured Following Conditions: -40°C +85°C (Note 5.5V 25V, Unless Otherwise Noted. Typical Values +25°C. SYMBOL TEST CONDITIONS UNITS
PARAMETER SUPPLY VOLTAGE Voltage Range
connected
Operating Supply Current Shutdown Supply Current POWER-ON RESET Threshold
Note 15V,
Rising Edge Hysteresis
4.00
4.15
4.30
INTERNAL Output Voltage Range REFERENCE Reference Voltage STANDARD BUCK REGULATOR Line Regulation Leakage Current OSCILLATOR MODULATOR Nominal Switching Frequency Modulator Gain Peak-to-Peak Sawtooth Amplitude Ramp Offset Voltage Maximum Duty Cycle AMOD VRAMP VOFFSET DCmax COMP (AMOD 8/VIN) (VP-P VIN/8) 0.65 0.75 0.75 0.95 0.85 IOUT 0mA, 5.5V 0.6V -0.05 0.05 5.5V 25V, IREF 0.594 0.606 5.5V 25V, IVDD 30mA 5.00
FN6611.0 December 2007
ISL8500
Electrical Specifications
Unless Otherwise Noted, Parameter Limits Established Over Recommended Operating Conditions Typical Specifications Measured Following Conditions: -40°C +85°C (Note 5.5V 25V, Unless Otherwise Noted. Typical Values +25°C. (Continued) SYMBOL TEST CONDITIONS UNITS
PARAMETER ERROR AMPLIFIER Open-Loop Gain Gain Bandwidth Product Slew Rate ENABLE SECTION Threshold
GBWP COMP 10pF
V/µs
Rising Edge Hysteresis
Logic Input Current FAULT PROTECTION Thermal Shutdown Temperature THYS Trip Level Propagation Delay Threshold Blanking Time POWER GOOD Trip Level Referred Nominal VOUT Lower Level, Falling Edge, with typically 15mV hysteresis Upper Level, Rising Edge, with typically 15mV hysteresis Propagation Delay Voltage Leakage Current SOFT-START SECTION Soft-Start Threshold Enable Buck Soft-Start Threshold Enable Soft-Start Voltage High Soft-Start Charging Current Soft-Start Pull-down POWER MOSFET rDS(ON) IOUT 100mA, Resistance 3.0V ISINK 5.5V, 0.6V, 5.5V Note Rising Threshold Hysteresis Referred Nominal VOUT
2.56
3.94
0.05
3.45
FN6611.0 December 2007
ISL8500 Descriptions
(Pin COMP (Pin
standard buck regulator employs single voltage control loop. negative input voltage loop error amplifier. COMP output error amplifier. output voltage external resistor divider connected With properly selected divider, output voltage voltage between power rail (reduced converter losses) 0.6V reference. Connecting network across COMP provides loop compensation amplifier. addition, regulator power good undervoltage protection circuitry monitor regulator output voltage.
BOOT (Pin
Floating bootstrap supply power MOSFET gate driver. bootstrap capacitor provides necessary charge turn hold internal N-Channel MOSFET. Connect external capacitor from this PHASE.
PHASE (Pins
Switch node connections internal power MOSFET source, external output inductor external diode cathode.
(Pins
input supply regulator power stage source internal linear regulator that provides bias Place ceramic capacitor from GND, close decoupling (typical 10µF).
(Pin
Program soft-start duration. regulated 30µA pull-up current source charges capacitor connected from GND. output voltage converter follows ramping voltage pin.
(Pin
controller enable input. converter output held when pulled ground. When voltage this rises above 1.7V, chip enabled.
(Pin
converter power good output. Open drain logic output that pulled ground when output voltage outside regulation limits. Connect 100k resistor from this VDD. when buck regulator output voltage within respective nominal voltage, during soft-start interval. high impedance when output within regulation.
(Pin
Ground connect thermal relief package. exposed must connected soldered PCB. voltage levels measured with respect this pin.
(Pin
Internal linear regulator output provides bias internal control logic. ISL8500 powered directly from (±10%) supply this pin. When used supply input, this must externally connected VIN. must always decoupled with ceramic bypass capacitor (minimum 1µF) located close pin.
TABLE INPUT SUPPLY CONFIGURATION INPUT 5.5V CONFIGURATION Connect input supply only. will provide output from internal linear regulator. Connect input supply pins.
±10%
FN6611.0 December 2007
ISL8500 Typical Performance Curves
Unless otherwise noted, operating conditions are: +25°C, 12V, VDD, 10µH, COUT 100µF, 2x22µF, IOUT "The input supply regulator power stage source internal linear regulator that provides bias Place ceramic capacitor from GND, close decoupling (typical 10µF)." page
1.8VOUT EFFICIENCY OUTPUT LOAD OUTPUT LOAD 1.5VOUT 1.2VOUT 1.8VOUT 1.5VOUT
EFFICIENCY 3.3VOUT 1.2VOUT
2.5VOUT
2.5VOUT 3.3VOUT
5VOUT
FIGURE EFFICIENCY LOAD, 5VIN
FIGURE EFFICIENCY LOAD, 12VIN
EFFICIENCY
12VOUT 5VOUT POWER DISSIPATION
OUTPUT LOAD 5VIN 12VIN 25VIN
1.2VOUT 1.8VOUT
1.5VOUT
2.5VOUT
OUTPUT LOAD
FIGURE EFFICIENCY LOAD, 25VIN
FIGURE POWER DISSIPATION LOAD, 2.5VOUT
1.206 1.205 OUTPUT VOLTAGE OUTPUT VOLTAGE 1.204 1.203 1.202 1.201 1.200 1.199 1.198 OUTPUT LOAD 5VIN 12VIN 25VIN
1.510 1.509 1.508 1.507 1.506 1.505 1.504 1.503 1.502 OUTPUT LOAD 5VIN 12VIN 25VIN
FIGURE VOUT REGULATION LOAD, 1.2VOUT
FIGURE VOUT REGULATION LOAD, 1.5VOUT
FN6611.0 December 2007
ISL8500 Typical Performance Curves
Unless otherwise noted, operating conditions are: +25°C, 12V, VDD, 10µH, COUT 100µF, 2x22µF, IOUT "The input supply regulator power stage source internal linear regulator that provides bias Place ceramic capacitor from GND, close decoupling (typical 10µF)." page (Continued)
2.506 25VIN OUTPUT VOLTAGE 12VIN 2.505 2.504 2.503 2.502 2.501 2.500 2.499 OUTPUT LOAD 2.498 5VIN 12VIN 25VIN
1.814 1.813 OUTPUT VOLTAGE 1.812 1.811 1.810 1.809 1.808 1.807 1.806 5VIN
OUTPUT LOAD
FIGURE VOUT REGULATION LOAD, 1.8VOUT
FIGURE VOUT REGULATION LOAD, 2.5VOUT
3.330 3.328 OUTPUT VOLTAGE 3.326 3.324 3.322 3.320 3.318 3.316 3.314 OUTPUT LOAD 7VIN 12VIN 25VIN OUTPUT VOLTAGE
4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.91 12VIN OUTPUT LOAD 7VIN 25VIN
FIGURE VOUT REGULATION LOAD, 3.3VOUT
FIGURE VOUT REGULATION LOAD, 5VOUT
PHASE 10V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
0.5A/DIV
1A/DIV
FIGURE STEADY STATE OPERATION LOAD (5µs/DIV)
FIGURE STEADY STATE OPERATION FULL LOAD (1µs/DIV)
FN6611.0 December 2007
ISL8500 Typical Performance Curves
Unless otherwise noted, operating conditions are: +25°C, 12V, VDD, 10µH, COUT 100µF, 2x22µF, IOUT "The input supply regulator power stage source internal linear regulator that provides bias Place ceramic capacitor from GND, close decoupling (typical 10µF)." page (Continued)
5V/DIV
PHASE 10V/DIV
VOUT 2V/DIV
VOUT RIPPLE 100mV/DIV
0.5mA/DIV 1A/DIV
5V/DIV
5V/DIV
FIGURE LOAD TRANSIENT (200µs/DIV)
FIGURE SOFT-START LOAD (2ms/DIV)
5V/DIV 5V/DIV VOUT 2V/DIV VOUT 2V/DIV
1A/DIV
5V/DIV
2A/DIV
5V/DIV 5V/DIV
FIGURE SOFT-START FULL LOAD (2ms/DIV)
FIGURE SHUT DOWN CIRCUIT (100µs/DIV)
PHASE 10V/DIV PHASE 10V/DIV
VOUT 1V/DIV
VOUT 2V/DIV
2A/DIV 2A/DIV
5V/DIV
5V/DIV
FIGURE OUTPUT SHORT CIRCUIT (5µs/DIV)
FIGURE OUTPUT SHORT CIRCUIT RECOVERY (1ms/DIV)
FN6611.0 December 2007
ISL8500 Detailed Description
ISL8500 combines standard buck controller with integrated switching MOSFET. buck controller drives internal N-Channel MOSFET requires external diode deliver load current Schottky diode recommended improved efficiency performance over standard diode. standard buck regulator operate from either unregulated source, such battery, with voltage ranging from +5.5V +25V, from regulated system rail +5V. When operating from +5.5V greater, controller biased from internal voltage regulator. converter output regulated down 0.6V from either input source. These features make ISL8500 ideally suited FPGA wireless chipset power applications. control loop uses single output voltage loop with input voltage feed forward, which simplifies feedback loop compensation rejects input voltage variation. External feedback loop compensation allows flexibility output filter component selection. regulator switches fixed 500kHz. buck regulator equipped with lossless current limit scheme. current limit buck regulator achieved monitoring drain-to-source voltage drop internal switching power MOSFET. current limit threshold internally 3.5A. part also features undervoltage protection latching switching MOSFET driver OFF-state during overcurrent, when output voltage lower than regulated output. This helps minimize power dissipation during short-circuit condition. only switching power MOSFET integration, there overvoltage protection feature this part.
Power-On Reset Undervoltage Lockout
portion ISL8500 automatically initializes upon receipt input power. power-on reset (POR) function continually monitors voltage. While below thresholds, controller inhibits switching internal power MOSFET. Once exceeded, controller initializes internal soft-start circuitry. either input supply drops below their falling threshold during soft-start operation, buck regulator latches off.
Enable Disable
internal power devices held high-impedance state, which ensures they remain while shutdown mode. Typically, enable input specific output toggled high after input supply that regulator active internal exceeded it's threshold. enables buck controller portion ISL8500. When voltage exceeds rising threshold, controller initiates soft-start function regulator. voltage drops below falling threshold, buck regulator shuts down. Pulling simultaneously output into shutdown mode supply current drops 100µA typical.
Soft-Start
Once input supply latch enable threshold met, soft-start function initialized. soft-start circuitry begins sourcing 30µA, from internal current source, which charges external soft-start capacitor. voltage begins ramping linearly from ground until voltage across soft-start capacitor reaches 3.0V. This linear ramp applied non-inverting input internal error amplifier overrides nominal 0.6V reference. output voltage reaches regulation value when soft-start capacitor voltage reaches 1.6V. Connect capacitor from ground. This capacitor (along with internal 30µA current source) sets soft-start interval converter, TSS.
(EQ.
Internal Bias Supply (VDD)
Voltage applied with respect regulated internal regulator. output LDO, VDD, bias voltage used internal control protection circuitry. requires ceramic capacitor connected GND. capacitor serves stabilize decouple load transients. input voltage range ISL8500 specified +5.5V +25V ±10%. case unregulated supply case, power supply connected only. Once enabled, linear regulator will turn-on rise VDD. supply case, pins must tied together bypass LDO. external decoupling capacitor still required this mode.
Upon disable, voltage will discharge zero voltage.
Power Good
open-drain output window comparator that continuously monitors buck regulator output voltage. actively held when during buck regulator soft-start period. After soft-start period terminates, becomes high impedance long output voltage within ±12% nominal regulation voltage When VOUT drops below rises above nominal regulation voltage, ISL8500 pulls low. fault condition forces until fault condition cleared attempts soft-start. logic level output voltages, connect external pull-up resistor between VDD. 100k resistor works well most applications.
Operation Initialization
power-on reset circuitry enable inputs prevent false start-up regulator output. Once input criteria met, controller soft-starts output voltage programmed level.
FN6611.0 December 2007
ISL8500
Output Voltage Selection
regulator output voltages programmed using external resistor dividers that scale voltage feedback relative internal reference voltage. scaled voltage back inverting input error amplifier; refer Figure output voltage programming resistor, will depend value chosen feedback resistor, desired output voltage, VOUT, regulator; Equation value feedback resistor typically between 10k.
0.6V 0.6V (EQ.
cycles, overcurrent fault counter overflows, indicating overcurrent fault condition exists. regulator shut down power good goes low. overcurrent condition clears prior counter reaching four consecutive cycles, internal flag counter reset. protection circuitry attempts recover from overcurrent condition after waiting soft-start cycles. internal overcurrent flag counter reset. normal soft-start cycle attempted normal operation continues fault condition cleared. overcurrent fault counter overflows during soft-start, converter shuts down this hiccup mode operation repeats. There 100ns blanking time noise immunity. recommended operate duty cycle higher than blanking time insure proper overcurrent protection.
output voltage desired 0.6V, then left unpopulated.
VOUT
Undervoltage Protection
voltage detected buck regulator falls below internal reference voltage, undervoltage fault condition flag set. regulator shutdown. controller enters recovery mode similar overcurrent hiccup mode. action taken soft-start cycles internal undervoltage counter fault condition flag reset. normal soft-start cycle attempted normal operation continues fault condition cleared. undervoltage counter overflows during soft-start, converter shut down this hiccup mode operation repeats.
0.6V REFERENCE
FIGURE EXTERNAL RESISTOR DIVIDER
buck output programmed high 19V. Proper heatsinking must provided insure that junction temperature does exceed +125°C. When output greater than 2.7V, recommended pre-load least 10mA make sure that input rise time faster than VOUT1 rise time. This allows BOOT capacitor adequate time charge proper operation.
Thermal Overload Protection
Thermal overload protection limits total power dissipation ISL8500. There sensor chip monitor junction temperature internal switching power N-Channel MOSFET. When junction temperature (TJ) sensor exceeds +150°C, thermal sensor sends signal fault monitor. fault monitor commands buck regulator shut down. buck regulator soft-starts turn again after IC's junction temperature cools +20°C. buck regulator experiences hiccup mode operation during continuous thermal overload conditions. continuous operation, exceed +125°C junction temperature rating.
Protection Features
ISL8500 limits current power devices limit on-chip power dissipation. Overcurrent limits regulator protect internal power device from excessive thermal damage. Undervoltage protection circuitry buck regulator provides second layer protection internal power device under high current condition.
Buck Regulator Overcurrent Protection
During on-time, current through internal switching MOSFET sampled scaled through internal pilot device. sampled current compared nominal 3.5A overcurrent limit. sampled current exceeds overcurrent limit reference level, internal overcurrent fault counter internal flag set. internal power MOSFET immediately turned will turned again until next switching cycle. protection circuitry continues monitor current turns internal MOSFET described. overcurrent condition persists eight sequential clock
Application Guidelines
Operating Frequency
ISL8500 operates fixed switching frequency 500kHz.
Buck Regulator Output Capacitor Selection
output capacitor required filter inductor current supply load transient current. filtering requirements function switching frequency ripple current. load transient requirements function slew rate (di/dt) magnitude
FN6611.0 December 2007
ISL8500
transient load current. These requirements generally with capacitors careful layout. Embedded processor systems capable producing transient load rates above 1A/ns. High frequency capacitors initially supply transient slow current load rate seen bulk capacitors. bulk filter capacitor values generally determined (Effective Series Resistance) voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications bulk capacitors. bulk capacitor's will determine output ripple voltage initial voltage drop after high slew-rate transient. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, Equivalent Series Inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable component. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. response time transient different application load removal load. Equation gives approximate response time interval application removal transient load:
tRISE ITRAN VOUT tFALL ITRAN VOUT (EQ.
where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. worst case response time either application removal load. sure check Equation minimum maximum output levels worst case response time.
Rectifier Selection
Current circulates from ground junction MOSFET inductor when high-side switch off. consequence, polarity switching node negative with respect ground. This voltage approximately -0.5V Schottky diode drop) during off-time. rectifier's rated reverse breakdown voltage must least equal maximum input voltage, preferably with derating factor. power dissipation shown Equation
(EQ.
where voltage Schottky diode 0.5V 0.7V
Input Capacitor Selection
input bypass capacitors control voltage overshoot across MOSFETs. small ceramic capacitors high frequency decoupling bulk capacitors supply current needed each time switching MOSFET turns Place small ceramic capacitors physically close MOSFET pins (switching MOSFET drain) Schottky diode anode. important parameters bulk input capacitance voltage rating current rating. reliable operation, select bulk capacitors with voltage current ratings above maximum input voltage largest current required circuit. Their voltage rating should least 1.25 times greater than maximum input voltage, while voltage rating times conservative guideline. most cases, current rating requirement input capacitor buck regulator approximately load current. maximum current required regulator closely approximated through Equation
Output Inductor Selection
output inductor selected meet output voltage ripple requirements minimize converter's response time load transient. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated Equation
VOUT VOUT VOUT (EQ.
Increasing value inductance reduces ripple current voltage. However, large inductance values reduce converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, ISL8500 will provide either duty cycle response load transient. response time time required slew inductor current from initial current value transient current level. During this interval, difference between inductor current transient current level must supplied output capacitor. Minimizing response time minimize output capacitance required.
(EQ.
through hole design, several electrolytic capacitors needed. surface mount designs, solid tantalum capacitors used, caution must exercised with
FN6611.0 December 2007
ISL8500
regard capacitor surge current rating. These capacitors must capable handling surge-current power-up. Some capacitor series available from reputable manufacturers surge current tested.
DRIVER PHASE VDDQ COMPARATOR
zeros gain components Figure following guidelines locating poles zeros compensation network: Pick Gain (R2/R1) desired converter bandwidth. Place Zero Below Filter's Double Pole (~75% FLC). Place Zero Filter's Double Pole. Place Pole Zero. Place Pole Half Switching Frequency. Check Gain against Error Amplifier's Open-Loop Gain. Estimate Phase Margin Repeat Necessary.
VOSC
VE/A ERROR REFERENCE
(PARASITIC)
Compensation Break Frequency Equations
DETAILED COMPENSATION COMPONENTS COMP ISL8500 REFERENCE VOUT
(EQ.
FIGURE VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN OUTPUT VOLTAGE SELECTION
Feedback Compensation
Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage (VOUT) regulated Reference voltage level. error amplifier output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated (PWM) wave with amplitude PHASE node. wave smoothed output filter CO). modulator transfer function small-signal transfer function VOUT/VE/A This function dominated Gain output filter CO), with double pole break frequency zero FESR Gain modulator simply input voltage (VIN) divided peak-to-peak oscillator voltage VOSC
Figure shows asymptotic plot DC/DC converter's gain frequency. actual Modulator Gain high gain peak high factor output filter shown Figure Using previously mentioned guidelines should give Compensation Gain similar curve plotted. open loop error amplifier gain bounds compensation gain. Check compensation gain with capabilities error amplifier. Closed Loop Gain constructed graph Figure adding Modulator Gain Compensation Gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain.
GAIN (dB) FESR 100k MODULATOR GAIN 20LOG (R2/R1) OPEN LOOP ERROR GAIN
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
Modulator Break Frequency Equations
(EQ.
FREQUENCY (Hz)
compensation network consists error amplifier (internal ISL8500) impedance networks ZFB. goal compensation network provide closed loop transfer function with highest crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB 180°. Equation relates compensation network's poles,
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
compensation gain uses external impedance networks provide stable, high bandwidth (BW) overall loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than 45°. Include worst case component variations when determining phase margin.
FN6611.0 December 2007
ISL8500
more detailed explanation voltage mode control buck regulator found TB417, entitled "Designing Stable Compensation Networks Single Phase Voltage Mode Buck Regulators."
ISL8500 CBP1 PHASE COMP COUT1 LOAD
FN6611.0 December 2007
Layout Considerations
Layout very important high frequency switching converter design. With power devices switching efficiently between 100kHz 600kHz, resulting current transitions from device another cause voltage spikes across interconnecting impedances parasitic circuit elements. These voltage spikes degrade efficiency, radiate noise into circuit, lead device overvoltage stress. Careful component layout printed circuit board design minimizes these voltage spikes. example, consider turn-off transition upper MOSFET. Prior turn-off, MOSFET carrying full load current. During turn-off, current stops flowing MOSFET picked Schottky diode. parasitic inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide traces minimizes magnitude voltage spikes. There sets critical components ISL8500 switching converter. switching components most critical because they switch large amounts energy, therefore tend generate large amounts noise. Next small signal components, which connect sensitive nodes supply critical bypass current signal coupling. multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT could each represent numerous physical capacitors. Dedicate solid layer, usually middle layer board, ground plane make critical component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. Keep metal runs from PHASE terminals output inductor short. power plane should support input power output power nodes. copper filled polygons bottom circuit layers phase nodes. remaining printed circuit layers small signal wiring. order dissipate heat generated internal MOSFET, ground pad, should connected internal ground plane through least four vias. This allows heat move away from also ties ground plane through impedance path. switching components should placed close ISL8500 first. Minimize length connections between input capacitors, CIN, power switches placing them nearby. Position both ceramic bulk input capacitors close upper MOSFET drain
VOUT1
ISLAND POWER PLANE LAYER ISLAND CIRCUIT AND/OR POWER PLANE LAYER CONNECTION GROUND PLANE
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
possible. Position output inductor output capacitors between upper Schottky diode load. critical small signal components include bypass capacitors, feedback components, compensation components. Place converter compensation components close COMP pins. feedback resistors should located close possible with vias tied straight ground plane required.
ISL8500 Dual Flat No-Lead Plastic Package (DFN)
L12.4x3
0.15 0.15
LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT JEDEC MO-229-VGED-4 ISSUE MILLIMETERS SYMBOL 0.80 NOMINAL 0.90 0.20 0.18 0.23 4.00 3.15 3.30 3.00 1.55 1.70 0.50 0.20 0.30 0.40 0.50 1.80 3.40 0.30 1.00 0.05 NOTES Rev. 2/05
INDEX AREA VIEW
0.10 0.08
SIDE VIEW SEATING PLANE (DATUM INDEX AREA (DATUM E2/2 (Nd-1)Xe REF. BOTTOM VIEW (A1) 0.10 D2/2
NOTES:
Dimensioning tolerancing conform ASME Y14.5-1994. number terminals. refers number terminals dimensions millimeters. Angles degrees. Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. configuration identifier optional, must located within zone indicated. identifier either mold mark feature. Dimensions exposed pads which provide improved electrical thermal performance. Nominal dimensions provided assist with Land Pattern Design efforts, Intersil Technical Brief TB389.
SECTION "C-C" TERMINAL EVEN TERMINAL/SIDE
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN6611.0 December 2007

Data Sheet December 2007 FN6611.0 Standard Buck Regulator IS

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