General Description AS1156/AS1154 Single/Dual Flow-Through LVDS (

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General Description AS1156/AS1154 Single/Dual Flow-Through LVDS (

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1156/AS1154
General Description
AS1156/AS1154 Single/Dual Flow-Through LVDS (Low-Voltage Differential Signaling) Line Driver which accepts converts LVTTL/LVCMOS input levels into LVDS output signals. device perfect low-power low-noise applications requiring high signaling rates reduced emissions. device guaranteed transmit data speeds 800Mbps (400MHz) over controlled impedance media approximately 100. Supported transmission media traces, backplanes, cables. AS1156 single LVDS transmitter, AS1154 dual LVDS transmitter. Outputs conform ANSI TIA/EIA-644 LVDS standards. Flow-through pinout simplifies board layout reduces crosstalk separating LVTTL/LVCMOS inputs LVDS outputs. AS1156/AS1154 operates from single +3.3V supply specified operation from +85°C.
Features
Flow-Through Pinout Guaranteed 800Mbps Data Rate 250ps Pulse Skew (Max) Conforms ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: +85°C 8-Pin SOIC Package
Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors Microcontrollers, Power Monitoring, Portable/Battery-Powered Equipment.
Figure Block Diagram
AS1156
AS1154
OUT1-
OUT1-
OUT1+
OUT1+
OUT2+
OUT2-
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AS1156/AS1154 Data Sheet
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Assignments
Pinout Packaging
Assignments
Figure AS1156/AS1154 Assignments (Top View)
OUT1OUT1+
OUT1OUT1+ OUT2+ OUT2-
AS1156
AS1154
Descriptions
Table AS1156/AS1154 Descriptions Number AS1154 AS1156 Name OUT2OUT2+ OUT1+ OUT1N/C Description Power Supply Input. Bypass with 0.1µF 0.001µF ceramic capacitors. LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Driver Input Ground Inverting LVDS Driver Output Noninverting LVDS Driver Output Noninverting LVDS Driver Output Inverting LVDS Driver Output connected
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Descriptions
Absolute Maximum Ratings
Stresses beyond those listed Table cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings Parameter INx, OUTx+, OUTx- Short Circuit Duration (OUTx+, OUTx-) Continuous Power Dissipation +70°C) Storage Temperature Range Maximum Junction Temperature Operating Temperature Range Limits -0.3 +5.0 -0.3 (VCC 0.3) -0.3 Continuous +150 +150
Units
Notes
Derate 9.4mW/°C Above +70°C
Package Body Temperature
reflow peak soldering temperature (body temperature) specified compliance with IPC/JEDEC J-STD020C "Moisture/ Reflow Sensitivity Classification Non-Hermetic Solid State Surface Mount Devices". Human Body Model, INx, OUTx+, OUTx-
Protection
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Electrical Characteristics
Electrical Characteristics
Electrical Characteristics
(VCC +3.0 +3.6V, +85°C Typical values +3.3V, +25°C, Unless Otherwise Noted.) Table Electrical Characteristics Parameter LVDS Output (OUtx+, OUTx-) Differential Output Voltage
Change Magnitude Between Complementary Output States
Symbol
Conditions
Unit
Figure page Figure page Figure page Figure page
1.375
Offset Voltage
Change Magnitude Between Complementary Output States
1.125
1.25
IOSD IOFF
Output High Voltage Output Voltage Differential Output Short-Circuit Current Output Short-Circuit Current Power-Off Output Current Inputs (INx) High-Level Input Voltage Low-Level Input Voltage Input Current Supply Current No-Load Supply Current
0.90
OUTx+ OUTx- open, OUTx+ 3.6V OUTx- 3.6V,
-3.7
channels 100, channels, AS1156 100, channels, AS1154
Loaded Supply Current
ICCL
Notes: Currents into device positive, current device negative. voltages referenced ground except VOD. Guaranteed correlation data.
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Switching Characteristics
Switching Characteristics
(VCC +3.0 +3.6V, ±1%, 2.5pF (differential), +85°C Typical values +3.3V, Unless Otherwise Noted.)
Table Switching Characteristics Parameter Differential Propagation Delay, High-to-Low Differential Propagation Delay, Low-to-High Differential Pulse Skew Differential Channel-to-Channel Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Maximum Operating Frequency Notes: Parameters guaranteed design characterization. includes probe capacitance. Signal generator conditions dynamic tests: 2.4V, 100MHz, duty cycle, 1ns, 100%). tSKD1 magnitude difference differential propagation delay. tSKD1 |tPHLD tPLHD|. tSKD2 magnitude difference tPHLD tPLHD channel tPHLD tPLHD another channel same device. tSKD3 magnitude difference differential propagation delays between devices same within each other. tSKD4 magnitude difference differential propagation delays between devices operating over rated supply temperature ranges. fMAX signal generator conditions: 2.4V, duty cycle, 1ns, 100%). Transmitter output criteria: duty cycle 55%, 250mV. optimum performance matched circuits should used. Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Conditions Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page 1.268 1.267 Unit
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Switching Characteristics
Typical Operating Characteristics
+3.3V, CLOAD 2.5pF (differential), Freq 20MHz, Tamb unless otherwise noted Figure Transition Time
Figure Transition Time Temperature
tTHL
tTHL
Transition Time (ps)
Transition Time (ps)
tTLH
tTLH
Supply Voltage(V)
Ambient Temperature(°C)
Figure Differential Pulse Skew
Figure Pulse Skew Temperature
Differential Pulse Skew (ps)
Pulse Skew (ps)
Supply Voltage(V)
Ambient Temperature(°C)
Figure Differential Propagation Delay VCC;
1.05
Figure Differential Propagation Delay Temp.
1.14
1.12 1.03
tPHLD
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
1.08 1.06 1.04 1.02 0.98
tPHLD tPLHD
1.01
0.99
0.97
tPLHD
0.95
Supply Voltage(V)
Ambient Temperature(°C)
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Switching Characteristics
Figure Differential Output Voltage
Figure Differential Output Voltage Frequency
Supply Voltage
Differential Output Voltage (mV)
Differential Output Voltage (mV)
Frequency (MHz)
Figure Offset Voltage
1.24
Figure Offset Voltage Frequency
1.35
Offset Voltage
1.23
Offset Voltage
1.25
1.22
1.21
1.15
Supply Voltage
Frequency (MHz)
Figure Output Voltage VCC;
1.45
VOUT+
Figure Output Voltage Load Resistance;
1.45
Output Voltage
Output Voltage
1.35
1.35
VOUT+
1.25
1.25
1.15
VOUT-
1.15
VOUT-
1.05
1.05
0.95
0.95
Supply Voltage
Load Resistance
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Switching Characteristics
Figure
Figure Temperature;
10.6
Supply Current (mA)
10.2
Supply Current (mA)
Freq 100MHz
Freq 20MHz
Supply Voltage
Ambient Temperature(°C)
Figure Short Circuit Current
Figure Frequency
Output Short Circuit Current (mA)
3.85
Supply Current (mA)
Channel
Channels
3.75
3.65
Supply Voltage(V)
Frequency (MHz)
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AS1156/AS1154 Data Sheet
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LVDS Interface
Detailed Description
LVDS Interface
LVDS interface standard signaling method intended point-to-point communication over controlled-impedance medium defined ANSI/TIA/EIA-644 IEEE 1596.3 standards. LVDS standard uses lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing emissions system susceptibility noise. AS1156/AS1154 800Mbps single/dual differential LVDS driver that designed high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels translates them LVDS output signals. AS1156/AS1154 generates 2.5mA 4.5mA output current using current-steering configuration. This current steering approach induces less ground bounce shoot-through current, enhancing noise margin system speed performance. driver outputs short-circuit current limited, enter high-impedance state when device powered disabled. current-steering architecture AS1156/AS1154 requires resistive load terminate signal complete transmission loop. Because device switches current voltage, actual output voltage swing determined value termination resistor input LVDS receiver (AS1157, AS1158). Logic states determined direction current flow through termination resistor. With typical 3.7mA output current, AS1156/AS1154 produces output voltage 370mV when driving load.
Termination
Because AS1156/AS1154 current-steering device, output voltage will generated without termination resistor. termination resistors should match differential impedance transmission line. Output voltage levels depend upon value termination resistor. AS1156/AS1154 optimized point-to-point interface with termination resistors receiver inputs. Termination resistance values range between and132, depending characteristic impedance transmission medium.
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Power-Supply Bypassing
Applications
Table Function Table Input 0.8V VINx 2.0V OUTx+ Undetermined Output OUTxH Undetermined
Figure Typical Application Circuit
+3.3V
+3.3V
0.001µF
0.1µF
0.001µF
0.1µF
LVDS Signals LVTTL/LVCMOS Data Inputs LVTTL/LVCMOS Data Outputs
AS1156
AS1158 Single LVDS Receiver
Shielded Twisted Cable Microstrip Board Traces
Power-Supply Bypassing
bypass VCC, high-frequency surface-mount ceramic 0.1µF 0.001µF capacitors parallel close device possible, with smaller valued capacitor closest VCC.
Differential Traces
Input trace characteristics adversely affect performance AS1156/AS1154.
controlled-impedance board traces match cable characteristic impedance. termination resistor also matched this characteristic impedance. Eliminate reflections ensure that noise couples common mode running differential traces near each other. Reduce skew using matched trace lengths. Tight skew control required minimize emissions proper data recovery devices. Route each channel's differential signals very close each other optimal cancellation their respective external magnetic fields. constant distance between differential traces avoid irregularities differential impedance. Avoid turns (use turns). Minimize number vias further prevent impedance irregularities.
Cables Connectors
Supported transmission media include printed circuit board traces, backplanes, cables.
cables connectors with matched differential impedance (typically 100) minimize impedance mismatches. Balanced cables such twisted pair offer superior signal quality tend generate less magnetic field canceling effects. Balanced cables pick noise common mode, which rejected LVDS receiver. Avoid unbalanced cables such ribbon cable simple coaxial cable.
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Board Layout
device should placed close interface connector possible minimize LVDS trace length.
Keep LVDS other digital signals separated from each other reduce crosstalk. four-layer board that provides separate power, ground, LVDS signals, input signals. Isolate input LVDS signals from each other output LVCMOS/LVTTL signals from each other prevent coupling. Separate input LVDS signals from output signals planes with power ground planes best results.
Figure Driver Propagation Delay Transition Time Waveforms
1.5V tPLHD OUTx0 Differential OUTx+
1.5V
tPHLD
VDIFF (VOUTx+) (VOUTx-)
tTLH
tTHL
Figure Driver Propagation Delay Transition Time Test Circuit
OUTx+
Generator
OUTx-
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Figure Driver Test Circuit
OUTx+
RL/2 RL/2
OUTx-
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Board Layout
Package Drawings Markings
AS1156/AS1154 available 8-pin SOIC package. Figure 8-pin SOIC Package
Notes: Lead coplanarity should 0.10mm (.004") max. Package surface finishing: Top, matte (charmilles #18-30) sides, matte (charmilles +18-30) Bottom, smooth matte (charmilles +18-30) dimensions excluding mold flashes flash from package body shall exceed 0.25mm (.010") side. Details mark optional must located within area indicated.
Symbol
1.52 1.72 0.10 0.25 1.37 1.57 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27BSC 5.80 6.20 0.25 0.50 0.41 1.27 0.53REF
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Board Layout
Ordering Information
Part Number AS1156-BSOU AS1156-BSOT AS1154-BSOU AS1154-BSOT Description Single Channel LVDS Line Driver Single Channel LVDS Line Driver Dual Channel LVDS Line Driver Dual Channel LVDS Line Driver Delivery Form Tubes Tape Reel Tubes Tape Reel Package SOIC-8 SOIC-8 SOIC-8 SOIC-8
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Board Layout
Copyrights
Copyright 1997-2006, austriamicrosystems Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. products companies mentioned trademarks registered trademarks their respective companies.
Disclaimer
Devices sold austriamicrosystems covered warranty patent indemnification provisions appearing Term Sale. austriamicrosystems makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. austriamicrosystems reserves right change specifications prices time without notice. Therefore, prior designing this product into system, necessary check with austriamicrosystems current information. This product intended normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support lifesustaining equipment specifically recommended without additional processing austriamicrosystems each application. shipments less than parts manufacturing flow might show deviations from standard production flow, such test flow test location. information furnished here austriamicrosystems believed correct accurate. However, austriamicrosystems shall liable recipient third party damages, including limited personal injury, property damage, loss profits, loss use, interruption business indirect, special, incidental consequential damages, kind, connection with arising furnishing, performance technical data herein. obligation liability recipient third party shall arise flow austriamicrosystems rendering technical other services.
Contact Information
Headquarters austriamicrosystems A-8141 Schloss Premstaetten, Austria Tel: 3136 Fax: 3136
Sales Offices, Distributors Representatives, please visit:
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General Description AS1156/AS1154 Single/Dual Flow-Through LVDS (

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