TMP88PH40MG Revision History Date 2007/7/10 Revision First R
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TLCS-870/X Series
TMP88PH40MG
Revision History
Date 2007/7/10 Revision First Release
Table Contents
TMP88PH40MG
Features Assignment Block Diagram Names Functions
Functional Description
Functions Core
Memory Address Map. Program Memory (ROM) Data Memory (RAM) System Clock Control Circuit
Clock Generator Timing Generator Standby Control Circuit Controlling Operation Modes External Reset Input Adress Trap Reset Watchdog Timer Reset System Clock Reset
2.1.1 2.1.2 2.1.3 2.1.4
2.1.5
2.1.4.1 2.1.4.2 2.1.4.3 2.1.4.4 2.1.5.1 2.1.5.2 2.1.5.3 2.1.5.4
Reset Circuit
Interrupt Control Circuit
Interrupt latches (IL38 IL2) Interrupt enable register (EIR) Interrupt Sequence
Interrupt acceptance processing packaged follows. Saving/restoring general-purpose registers
Using Automatic register bank switcing Using register bank switching Using PUSH instructions Using data transfer instructions
3.2.1 3.2.2
Interrupt master enable flag (IMF) Individual interrupt enable flags (EF38 EF3)
3.3.1 3.3.2
3.3.3 3.4.1 3.4.2
3.3.2.1 3.3.2.2 3.3.2.3 3.3.2.4
Software Interrupt (INTSW) External Interrupts
Address error detection Debugging
Interrupt return
Special Function Register
Input/Output Ports
Port (Only P10) Port (P37 P30) Port (P45 P40) Port (P63 P60)
Watchdog Timer (WDT)
Watchdog Timer Configuration Watchdog Timer Control
Malfunction Detection Methods Using Watchdog Timer Watchdog Timer Enable Watchdog Timer Disable Watchdog Timer Interrupt (INTWDT). Watchdog Timer Reset
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5
Time Base Timer (TBT)
Time Base Timer Table
16-Bit TimerCounter (TC1)
Configuration TimerCounter Control Function.
8.3.1 Timer mode. Figure Figure Figure Figure Figure
8-Bit TimerCounter (TC3)
Configuration TimerCounter Control Function.
9.3.1 Timer mode. Figure Figure
8-Bit TimerCounter (TC4)
10.1 10.2 10.3 Configuration TimerCounter Control Function
10.3.1 Timer Mode. Table 10-1 Table 10-1
Motor Control Circuit (PMD: Programmable motor driver)
11.1 11.2 11.3 Outline Motor Control Configuration Motor Control Circuit Position Detection Unit
Configuration position detection unit. Position Detection Circuit Register Functions. Outline Processing Position Detection Unit
11.4 11.5
11.3.1 11.3.2 11.3.3 11.4.1
Timer Unit
Configuration Timer Unit
Timer Circuit Register Functions Outline Processing Timer Unit
11.4.1.1 11.4.1.2
Three-phase Output Unit
Configuration three-phase output unit. Register Functions Waveform Synthesis Circuit. Port output with UOC/VOC/WOC bits UPWM/VPWM/WPWM bits. Protective Circuit. Functions Protective Circuit Registers
Pulse width modulation circuit (PWM waveform generating unit) Commutation control circuit
11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.6.1
11.5.1.1 11.5.1.2
11.6
Electrical Angle Timer Waveform Arithmetic Circuit
Electrical Angle Timer Waveform Arithmetic Circuit
Functions Electrical Angle Timer Waveform Arithmetic Circuit Registers List Related Control Registers
11.6.1.1 11.6.1.2
Asynchronous Serial interface (UART)
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuration Control Transfer Data Format Transfer Rate. Data Sampling Method STOP Length Parity Transmit/Receive Operation
Data Transmit Operation Data Receive Operation
12.8.1 12.8.2
Status Flag
Parity Error. Framing Error. Overrun Error Receive Data Buffer Full. Transmit Data Buffer Empty Transmit Flag
12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6
Synchronous Serial Interface (SIO)
13.1 13.2 13.3 Configuration Control Serial clock
Clock source
13.3.1
13.3.2
13.3.1.1 13.3.1.2 13.3.2.1 13.3.2.2
Shift edge.
Leading edge Trailing edge
Internal clock External clock
13.4 13.5 13.6
Number bits transfer Number words transfer Transfer Mode
4-bit 8-bit transfer modes 4-bit 8-bit receive modes 8-bit transfer receive mode
13.6.1 13.6.2 13.6.3
10-bit Converter (ADC)
14.1 14.2 14.3 Configuration Register configuration Function.
Software Start Mode Repeat Mode Register Setting
14.4 14.5
14.3.1 14.3.2 14.3.3
Analog Input Voltage Conversion Result Precautions about Converter
Analog input voltage range Analog input shared pins Noise Countermeasure
14.5.1 14.5.2 14.5.3
operation
15.1 Operating mode.
mode.
Program Memory Data Memory Input/Output Circuiry 15.1.1.1 15.1.1.2 15.1.1.3 15.1.2.1 15.1.2.2
15.1.1
15.1.2
PROM mode
Programming Flowchart (High-speed program writing) Program Writing using General-purpose PROM Programmer
Input/Output Circuitry
16.1 16.2 Control pins Input/output ports.
Electrical Characteristics
17.1 17.2 17.3 17.4 17.5 17.6 17.7 Absolute Maximum Ratings Operating Conditions Characteristics. Conversion Characteristics Characteristics Characteristics, Characteristics (PROM mode).
Read operation PROM mode. Program operation (High-speed)
17.6.1 17.6.2
Recommended Oscillation Conditions.
17.8
Handling Precaution
Package Dimensions
This technical document that describes operating functions electrical specifications 8-bit microcontroller series TLCS-870/X (LSI).
TMP88PH40MG
Assignment
XOUT TEST
RESET
AVSS AVDD VAREF (AIN3/DBOUT1) AIN2 AIN1 AIN0 (INT0) (SO/TXD) (SI/RXD) (SCK) (PDU1) (PDV1) (PDW1)
(Z1) (Y1) (X1) (W1) (V1) (U1) (EMG1) (CL1)
Figure Assignment
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Block Diagram
TMP88PH40MG
Block Diagram
Figure Block Diagram
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TMP88PH40MG
Names Functions
TMP88PH40MG mode PROM mode. Table shows functions mode. PROM mode explained later separate chapter.
Table Names Functions(1/2)
Name
INT0
Number
Input/Output PORT10 External interrupt input
Functions
PORT37 over load protection input1 PORT36 emergency stop input1 PORT35 control output PORT34 control output PORT33 control output PORT32 control output PORT31 control output PORT30 control output PORT45 Serial Data Output UART data output PORT44 Serial Data Input UART data input PORT43 Serial Clock PORT42 control input PORT41 control input PORT40 control input PORT63 Analog Input3 debug output1 PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 Resonator connecting pins high-frequency clock
EMG1
PDU1 PDV1 PDW1 AIN3 DBOUT1 AIN2 AIN1 AIN0
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Names Functions
TMP88PH40MG
Table Names Functions(2/2)
Name XOUT
RESET
Number
Input/Output
Functions Resonator connecting pins high-frequency clock Reset signal Test out-going test Serial PROM mode control pin. Usually level. high level when Serial PROM mode starts. Analog Base Voltage Input Conversion Analog Power Supply Analog Power Supply 0(GND)
TEST
VAREF AVDD AVSS
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TMP88PH40MG
Functional Description
Functions Core
core consists mainly CPU, system clock control circuit, interrupt control circuit. This chapter describes core, program memory, data memory, reset circuit TMP88PH40MG.
2.1.1
Memory Address
memory TMP88PH40MG consists four blocks: ROM, RAM, (Special Function Registers), (Data Buffer Registers), which mapped into 1-Mbyte address space. general-purpose registers consist banks, which mapped into address space. Figure shows memory address TMP88PH40MG.
(128 bytes) bytes)
002BFH
00000H 0003FH 00040H 000BFH 000C0H
bytes bytes
bytes
Special Function Register General-purpose Register Bank registers banks) Random-Access Memory
01F80H
bytes
01FFFH 04000H
Data Buffer Register (peripheral hardware control register status register)
16128 bytes
Program Memory
Kbytes)
07EFFH
FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH
bytes bytes bytes
Interrupt Vector Table Vector Table Vector Call Instructions Interrupt Vector Table
SFR: Special Function Registers Input/output port Peripheral hardware control register Peripheral hardware status register RAM: Random Access Memory System control register Data memory Interrupt control register Stack Program status word General-purpose register bank ROM: Read-Only Memory Program memory Vector Table
DBR: Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register
Figure Memory address
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Functional Description
Functions Core TMP88PH40MG
2.1.2
Program Memory (ROM)
TMP88PH40MG contains 16Kbytes program memory (OTP) located addresses 04000H 07EFFH addresses FFF00H FFFFFH.
2.1.3
Data Memory (RAM)
TMP88PH40MG contains 512bytes +128bytes RAM. first 128bytes location (00040H 000BFH) internal shared with general-purpose register bank. content data memory indeterminate power-on, sure initialize initialize routine. Example :Clearing internal TMP88PH40MG (clear addresses except bank
SRAMCLR: 0048H 277H (HL+), SRAMCLR start address initialization data (00H) byte counts (-1)
Note:Because general-purpose registers exist RAM, never clear current bank address RAM. above example, cleared except bank
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TMP88PH40MG
2.1.4
System Clock Control Circuit
System Clock Control Circuit consists clock generator, timing generator, standby control circuit.
Timing generator control register Clock generator High-frequency clock oscillator circuit XOUT Timing generator Standby control circuit 00039H SYSCR2 System clocks System control register TBTCR 00036H
Figure System Clock Control Circuit
2.1.4.1 Clock Generator
Clock Generator generates fundamental clock which serves reference system clocks supplied core peripheral hardware units. high-frequency clock (frequency obtained easily connecting resonator XOUT pins. clock generated external oscillator also used. this case, enter external clock from leave XOUT open. TMP88PH40MG does support network that produces time constant.
High-frequency Clock XOUT XOUT
(Open)
Using crystal ceramic resonator
Using external oscillator
Figure Example Connecting Resonator
Adjusting oscillation frequency
Note: Although hardware functions provided that allow fundamental clock monitored directly from outside, oscillation frequency adjusted forwarding pulse fixed frequency (e.g., clock output) port monitoring program while interrupts watchdog timer disabled. systems that require adjusting oscillation frequency, adjustment program must created beforehand.
2.1.4.2
Timing Generator
Timing Generator generates various system clocks from fundamental clock that supplied core peripheral hardware units. Timing Generator following functions:
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Functional Description
Functions Core TMP88PH40MG
Generate source clock time base timer Generate source clock watchdog timer Generate internal source clock timer counter Configuration Timing Generator Timing Generator 3-stage prescaler, 21-stage dividers, machine cycle counter. When reset, prescaler dividers cleared
Machine cycle counter
DV1CK
Prescaler
Selector
Divider
Divider
10111213141516171819 2021
Standby control circuit Watchdog timer
Timer counter
Time base timer
Figure Configuration Timing Generator
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TMP88PH40MG
Divider Control Register
CGCR (0030H) DV1CK (Initial value: 000* *000)
DV1CK
Selects input clock first divider stage
fc/4 fc/8
Note high-frequency clock [Hz], Don't care Note CGCR Register bits show indeterminate value when read. Note sure write CGCR Register bits
Machine cycle Instruction execution internal hardware operations synchronized system clocks. minimum unit instruction execution referred "mgmachine cycle". TLCS870/X series types instructions, from 1-cycle instructions which executed machine cycle 15-cycle instructions that require maximum machine cycles. machine cycle consists four states S3), with each state comprised main system clock cycle.
1/fc Main system clock
States
Machine cycle (0.20 MHz)
Figure Machine Cycles
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Functional Description
Functions Core TMP88PH40MG
2.1.4.3
Standby Control Circuit
Standby Control Circuit starts/stops high-frequency clock oscillator circuit selects main system clock. System Control Registers (SYSCR2) used control operation modes this circuit. Figure shows operation mode transition diagram, followed description System Control Registers. Single clock mode Only high-frequency clock oscillator circuit used. Because main system clock generated from high-frequency clock, machine cycle time single clock mode 4/fc [s]. NORMAL mode this mode, core peripheral hardware units operated with high-frequency clock. TMP88PH40MG enters this NORMAL mode after reset. IDLE mode this mode, watchdog timer turned while peripheral hardware units operated with high-frequency clock. IDLE mode entered into using System Control Register device placed this mode back into NORMAL mode interrupt from peripheral hardware external interrupt. When (interrupt master enable flag) (interrupt enabled), device returns normal operation after interrupt been serviced. When (interrupt disabled), device restarts execution beginning with instruction next that placed IDLE mode.
Table
Single Clock Mode
Oscillator Circuit Core Peripheral Circuit Reset 4/fc Operate IDLE Stop Machine Cycle Time
Operation Mode
High Frequency
Frequency
RESET Single Clock NORMAL Oscillate
Reset Operate
RESET Reset deasserted Instruction IDLE mode Interrupt NORMAL mode
Figure Operation Mode Transition Diagram
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TMP88PH40MG
System Control Register
SYSCR2 (0039H) IDLE (Initial value: 1000 ****)
IDLE
Place device IDLE mode
Keep operating Stop (IDLE mode entered)
Note sure SYSCR2 Register bit7. When cleared device reset. Note WDT: Watchdog Timer, Don't care Note sure write SYSCR2 Register bit6 bit5. Note values SYSCR2 Register bits indeterminate when read.
2.1.4.4
Controlling Operation Modes
IDLE mode IDLE mode controlled System Control Register (SYSCR2) maskable interrupt. During IDLE mode, device retains following state. watchdog timer stop operating. peripheral hardware continues operating. data memory, register, program status word, port output latch hold state which they were immediately before entering IDLE mode. program counter holds instruction address instructions ahead that placed device IDLE mode.
Example :Placing device IDLE mode
(SYSCR2)
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Functional Description
Functions Core TMP88PH40MG
Place device IDLE mode instruction)
Stop
Reset input
Reset
Interrupt request
(Released interrupt)
(Released normally)
Interrupt handling
Execute instruction next that placed device IDLE mode
Figure IDLE Mode
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TMP88PH40MG
device released from IDLE mode normally interrupt selected with interrupt master enable flag (IMF). Released normally (when device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), restarts execution beginning with instruction next that placed IDLE mode. interrupt latch (IL) interrupt source used exit IDLE mode normally needs cleared using load instruction. Released interrupt (when device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), enters interrupt handling. After interrupt handling, device returns instruction next that placed IDLE mode. device also released from IDLE mode pulling RESET input low, which case device immediately reset normally reset RESET. After reset, device starts operating from NORMAL mode.
Note: watchdog timer interrupt occurs immediately before entering IDLE mode, device processes watchdog timer interrupt without entering IDLE mode.
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Main system clock
Functional Description
Functions Core
Interrupt request IDLE
Program counter (SYSCR2).
Instruction execution Operating
Watchdog timer
Entering IDLE mode (Example: Entered into instruction placed address
Main system clock
Interrupt request
Program counter Instruction address
Figure Entering Exiting IDLE Mode
Operating Interrupt accepted Operating
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Instruction execution
IDLE
Watchdog timer
IDLE
Released normally
Main system clock
Interrupt request
Program counter
Instruction execution
IDLE
Watchdog timer
IDLE
Released interrupt
TMP88PH40MG
Exiting IDLE mode
TMP88PH40MG
2.1.5
Reset Circuit
TMP88PH40MG four ways generate reset: external reset input, address trap reset, watchdog timer reset, system clock reset. Table shows internal hardware initialized reset operation. power-on time, internal cause reset circuits (watchdog timer reset, address trap reset, system clock reset) initialized. Table Internal Hardware Initialization Reset Operation
Internal Hardware Program Counter (PC) Stack Pointer (SP) General-purpose Registers Register Bank Selector (RBS) Jump Status Flag (JF) Zero Flag (ZF) Carry Flag (CF) Half Carry Flag (HF) Sign Flag (SF) Overflow Flag (VF) Interrupt Master Enable Flag (IMF) Interrupt Individual Enable Flag (EF) Interrupt Latch (IL) Interrupt Nesting Flag (INF) Initial Value (FFFFEH FFFFCH) initialized initialized Watchdog timer initialized initialized initialized Output latch input/output port initialized initialized Control register description each control register. initialized description each input/output port. Enable Prescaler divider timing generator Internal Hardware Initial Value
2.1.5.1
External Reset Input
RESET hysteresis input with pull-up resistor included. holding RESET least three machine cycles (12/fc [s]) more while power supply voltage within rated operating voltage range oscillator oscillating stably, device reset internal state initialized. When RESET input released back high, device freed from reset starts executing program beginning with vector address stored addresses FFFFCH FFFFEH.
RESET
Reset input
Figure Reset Circuit
2.1.5.2 Adress Trap Reset
should start looping reasons noise, etc. attempts fetch instructions from internal RAM,SFR area, device generats internal reset. addess trap permission/prohibition address trap reset control register (ATAS,ATKEY). address trap permited initially internal reset generated fetching from internal RAM,SFR area. address trap prohibited, instructions internal area executed. Page
Functional Description
Functions Core TMP88PH40MG
Address Trap Control Register
ATAS (1F94H) ATAS (initial value: **** ***0)
ATAS
Select address trap permission prohibition
Permit address trap Prohibit address trap available after setting control code ATKEY register)
Write only
Address Trap Control Code Register
ATKEY (1F95H) (initial value: **** ****)
ATKEY
Write control code prohibit address trap
D2H: Address trap prohibition code Others: Ineffective
Write only
Note: Read-modify-write instructions, such manipulation, cannot access ATAS ATKEY register because these register write only. Note development tools, address trap cannot prohibited internal RAM,SFR area with address trap control registers. When using development tools, even address trap permission/prohibition setting changed user's program, this change ineffective. execute instructions from area, development tools must accordingly. Note While instruction address immediately before address trap area executing, program counter incremented point next address address trap area; address trap therefore taken immediately.
Development tool setting prohibit address trap: Modify iram (mapping attribute) area (00040H 000BFH) memory window. 000C0H "address trap prohibition area" eram (mapping attribute) area. Load user program Execute address trap prohibition code user's program
2.1.5.3
Watchdog Timer Reset
Refer Section "Watchdog Timer."
2.1.5.4
System Clock Reset
When SYSCR2 Register cleared system clock turned off, causing become locked prevent this problem, upon detecting SYSCR2 Register detecting SYSCR2 Register device automatically generates internal reset signal system clock continue oscillating.
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TMP88PH40MG
Interrupt Control Circuit
TMP88PH40MG total interrupt sources excluding reset. Interrupts nested with priorities. internal interrupt sources pseudo nonmaskable while rest maskable. Interrupt sources provided with interrupt latches (IL), which hold interrupt requests, independent vectors. interrupt latch generation interrupt request which requests accept interrupts. Interrupts enabled disabled software using interrupt master enable flag (IMF) interrupt enable flag (EF). more than interrupts generated simultaneously, interrupts accepted order which dominated hardware. However, there prioritized interrupt factors among non-maskable interrupts.
Interrupt Latch IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 IL30 IL31 IL32 IL33 IL34 IL35 IL36 IL37 IL38 Vector Address FFFFC FFFF8 FFFF4 FFFF0 FFFEC FFFE8 FFFE4 FFFE0 FFFDC FFFD8 FFFD4 FFFD0 FFFCC FFFC8 FFFC4 FFFC0 FFFBC FFFB8 FFFB4 FFFB0 FFFAC FFFA8 FFFA4 FFFA0 FFF9C FFF98 FFF94 FFF90 FFF8C FFF88 FFF84 FFF80 FFF3C FFF38 FFF34 FFF30 FFF2C FFF28 FFF24
Interrupt Factors Internal/External Internal Internal External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal (Reset) INTSW (Software interrupt) INTWDT (Watchdog timer interrupt) INT0 (External interrupt Reserved Reserved INTTBT (TBT interrupt) Reserved INTEMG1 (ch1 Error detect interrupt) Reserved INTCLM1 (ch1 Overload protection interrupt) Reserved INTTMR31 (ch1 Timer interrupt) Reserved Reserved Reserved INTPDC1 (ch1 Posision detect interrupt) Reserved INTPWM1 (ch1 Waveform generater interrupt) Reserved INTEDT1 (ch1 Erectric angle Timer interrupt) Reserved INTTMR11 (ch1 Timer1 interrupt) Reserved INTTMR21 (ch1 Timer2 interrupt) Reserved INTTC1 (TC1 interrupt) Reserved Reserved Reserved Reserved Reserved INTRX (UART receive interrupt) INTTX (UART transmit interrupt) INTSIO (SIO interrupt) INTTC3 (TC3 interrupt) INTTC4 (TC4 interrupt) Reserved INTADC (A/D converter interrupt)
Enable Condition Nonmaskable Pseudo nonmaskable Pseudo nonmaskable INT0EN EF10 EF11 EF12 EF13 EF14 EF15 EF16 EF17 EF18 EF19 EF20 EF21 EF22 EF23 EF24 EF25 EF26 EF27 EF28 EF29 EF30 EF31 EF32 EF33 EF34 EF35= EF36 EF37 EF38
Priority High
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Interrupt Control Circuit
Interrupt latches (IL38 IL2) TMP88PH40MG
Note watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> "Reset request" after reset released). described section "Watchdog Timer" details.
Interrupt latches (IL38 IL2)
interrupt latch provided each interrupt source, except software interrupt executed undefined instruction interrupt. When interrupt request generated, latch "1", requested accept interrupt interrupt enabled. interrupt latch cleared immediately after accepting interrupt. interrupt latches initialized during reset. interrupt latches located address 003CH, 003DH, 002EH, 002FH 002BH area. Each latch cleared individually instruction. However, should cleared software. clearing interrupt latch, load instruction should used then should "1". read-modifywrite instructions such manipulation operation instructions used, interrupt request would cleared inadequately interrupt requested while such instructions executed. Since interrupt latches read, status interrupt requests monitored software. interrupt latches instruction.
Note: main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
Example :Clears interrupt latches
(ILL), 1110100000111111B (ILH), 1110100000111111B (ILE), 1110100000111111B (ILD), 1110100000111111B (ILC), 1110100000111111B IL15 IL16 IL23 IL24 IL31 IL32 toIL38
Example :Reads interrupt latches
(ILL) (ILE) (ILC) (ILH), (ILL) (ILD), (ILE) (ILC)
Example :Tests interrupt latches
TEST (ILL). SSET then jump
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TMP88PH40MG
Interrupt enable register (EIR)
interrupt enable register (EIR) enables disables acceptance interrupts, except pseudo nonmaskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt watchdog interrupt). Pseudo non-maskable interrupt accepted regardless contents EIR. consists interrupt master enable flag (IMF) individual interrupt enable flags (EF). These registers located address 003AH, 003BH, 002CH, 002DH 002AH area, they read written instructions (Including read-modify-write instructions such manipulation operation instructions).
3.2.1
Interrupt master enable flag (IMF)
interrupt enable register (IMF) enables disables acceptance whole maskable interrupt. While "0", maskable interrupts accepted regardless status each individual interrupt enable flag (EF). setting "1", interrupt becomes acceptable individuals enabled. When interrupt accepted, cleared after latest status stacked. Thus maskable interrupts which follow disabled temporarily. flag maskable interrupt return instruction [RETI] after executing interrupt service program routine, accept interrupt again. latest interrupt request generated already, available immediately after [RETI] instruction executed. pseudo non-maskable interrupt, non-maskable return instruction [RETN] adopted. this case, flag only when performs pseudo non-maskable interrupt service routine interrupt acceptable status (IMF=1). However, pseudo non-maskable interrupt service routine, maintains status (IMF="0"). located bit0 EIRL (Address: 003AH SFR), read written instruction. normally cleared [EI] [DI] instruction respectively. During reset, initialized "0".
3.2.2
Individual interrupt enable flags (EF38 EF3)
Each these flags enables disables acceptance maskable interrupt. Setting corresponding individual interrupt enable flag enables acceptance interrupt, setting disables acceptance. During reset, individual interrupt enable flags (EF38 EF3) initialized maskable interrupts accepted until they "1".
Note:In main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
Example :Enables interrupts individually sets
(EIRL), (EIRL), (EIRH), (EIRD), EF12 EF24
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Interrupt Control Circuit
Interrupt enable register (EIR) TMP88PH40MG
Interrupt Latches
(Initial value: ***0*0*0 *0**0000) ILH,ILL (003DH, 003CH) IL12 IL10
(003DH)
(003CH)
(Initial value: *****0*0 *0*0*0*0) ILD,ILE (002FH, 002EH) IL26 IL24 IL22 IL20 IL18 IL16
(002FH)
(002EH)
(Initial value: *0*00000) (002BH) IL38 IL36 IL35 IL34 IL33 IL32
(002BH)
Read IL38 Interrupt latches interrupt request Interrupt request interrupt service interrupt service level interrupt service more than level interrupt service more than level
Write Clears interrupt request (Note1) (Unable interrupt latch) Reserved Clear nesting counter Count-down step nesting counter (Note2) Reserved
Interrupt Nesting Flag
Note cannot alone cleard. Note Unable detect under-flow counter. Note nesting counter initially, performs count-up interrupt acceptance count-down executing interrupt return instruction. Note main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1". Note clear with read-modify-write instructions such operations.
Interrupt Enable Registers
(Initial value: ***0*0*0 *0**0**0) EIRH,EIRL (003BH, 003AH) EF12 EF10
EIRH (003BH)
EIRL (003AH)
(Initial value: *****0*0 *0*0*0*0) EIRD,EIRE (002DH, 002CH) EF26 EF24 EF22 EF20 EF18 EF16
EIRD (002DH)
EIRE (002CH)
(Initial value: *0*00000) EIRE (002AH) EF38 EF36 EF35 EF34 EF33 EF32
EIRE (002AH)
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TMP88PH40MG
EF38
Individual-interrupt enable flag (Specified each bit) Interrupt master enable flag
Disables acceptance each maskable interrupt. Enables acceptance each maskable interrupt. Disables acceptance maskable interrupts Enables acceptance maskable interrupts
Note interrupt enable flag (EF38 EF3) same time. Note main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
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Interrupt Control Circuit
Interrupt Sequence TMP88PH40MG
Interrupt Sequence
interrupt request, which raised interrupt latch, held, until interrupt accepted interrupt latch cleared resetting instruction. Interrupt acceptance sequence requires machine cycles (2.4 MHz) after completion current instruction. interrupt service task terminates upon execution interrupt return instruction [RETI] (for maskable interrupts) [RETN] (for non-maskable interrupts). Figure shows timing chart interrupt acceptance processing.
3.3.1
Interrupt acceptance processing packaged follows.
interrupt master enable flag (IMF) cleared order disable acceptance following interrupt. interrupt latch (IL) interrupt source accepted cleared "0". contents program counter (PC) program status word, including interrupt master enable flag (IMF), saved (Pushed) stack sequence PSWH, PSWL, PCE, PCH, PCL. Meanwhile, stack pointer (SP) decremented entry address (Interrupt vector) corresponding interrupt service program, loaded vector table, transferred program counter. Read control code from vector table, MSB(4bit) register bank selecter (RBS). Count interrupt nesting counter. instruction stored entry address interrupt service program executed.
Note:When contents saved stack, contents also saved.
Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) Execute instruction Execute instruction
Execute instruction
Interrupt acceptance
Execute RETI instruction
Note Return address, Entry address, Address which RETI instruction stored Note condition that interrupt enabled, takes 62/fc maximum interrupt latch first machine cycle cycle instruction) start interrupt acceptance processing since interrupt latch set.
Figure Timing Chart Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address INTTBT entry address interrupt service program
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TMP88PH40MG
Vector table address
Entry address
FFFE4H FFFE5H FFFE6H FFFE7H
control code Vector
12345H 12346H 12347H 12348H Interrupt service program
Figure Vector table address,Entry address
maskable interrupt accepted until even maskable interrupt higher than level current servicing interrupt requested. order utilize nested interrupt service, interrupt service program. this case, acceptable interrupt sources selectively enabled individual interrupt enable flags. don't read-modify-write instruction EIRL(0003AH) pseudo non-maskable interrupt service task. avoid overloaded nesting, clear individual interrupt enable flag whose interrupt currently serviced, before setting "1". non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise status cannot recovered non-maskable interrupt would simply nested.
3.3.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, program counter (PC) program status word (PSW, includes IMF) automatically saved stack, accumulator others not. These registers saved software necessary. When multiple interrupt services nested, also necessary avoid using same data memory area saving registers. following four methods used save/restore general-purpose registers.
3.3.2.1
Using Automatic register bank switcing
switching non-use register bank, restore general-purpose register hige speed. Usually bank register assigned main task bank register each interrupt service task. make data memory efficiency, common bank assigned non-multiple intrrupt factor. return back main-flow executing interrupt return instructions ([RETI]/[RETN]) from current interrupt register bank automatically. Thus, need restore program.
Example :Register bank switching
PINTxx: (interrupt processing) RETI VINTxx: PINTxx PINTxx vector address setting setting PINTxx Begin interrupt routine interrupt
3.3.2.2
Using register bank switching
switching non-use register bank, restore general-purpose register hige speed. Usually bank register assigned main task bank register each interrupt service task. Page
Interrupt Control Circuit
Interrupt Sequence TMP88PH40MG
Example :Register bank switching
PINTxx: RBS, Begin interrupt routine (interrupt processing) RETI VINTxx: PINTxx PINTxx vector address setting setting PINTxx interrupt restore interrupt return
3.3.2.3
Using PUSH instructions
only specific register saved interrupts same source nested, general-purpose registers saved/restored using PUSH/POP instructions.
Example :Save/store register using PUSH instructions
PINTxx: PUSH Save register (interrupt processing) RETI Restore register RETURN
Address (Example) PSWL PSWH acceptance interrupt PSWL PSWH execution PUSH instruction PSWL PSWH execution instruction execution RETI instruction
Figure Save/store register using PUSH instructions
3.3.2.4 Using data transfer instructions
save only specific register without nested interrupts, data transfer instructions available.
Example :Save/store register using data transfer instructions
PINTxx: (GSAVA), Save register (interrupt processing) RETI (GSAVA) Restore register Return
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TMP88PH40MG
Main task Bank
Interrupt acceptance
Main task
Interrupt service task
Bank
Interrupt acceptance
Switch bank instruction Switch bank automatically
Interrupt service task
Saving registers
Bank
Bank
Interrupt return
Restore bank automatically [RETI]/[RETN]
Restoring registers
Interrupt return
Saving/restoring register bank changeover
Saving/restoring general-purpose registers using PUSH/POP data transfer instruction
Figure Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return
Interrupt return instructions [RETI]/[RETN] perform follows.
[RETI] Maskable Interrupt Return contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag "1". interrupt nesting counter decremented, interrupt nesting flag changed. [RETN] Non-maskable Interrupt Return contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag only when non-maskable interrupt accepted interrupt enable status. However, interrupt master enable flag remains when clear interrupt service program. interrupt nesting counter decremented, interrupt nesting flag changed.
Interrupt requests sampled during final cycle instruction being executed. Thus, next interrupt accepted immediately after interrupt return instruction executed.
Note: When interrupt processing time longer than interrupt request generation time, interrupt service task performed main task.
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Interrupt Control Circuit
Software Interrupt (INTSW) TMP88PH40MG
Software Interrupt (INTSW)
Executing instruction generates software interrupt immediately starts interrupt processing (INTSW highest prioritized interrupt). However, processing non-maskable inerrupt already underway, executing instruction will generate software interrupt will result same operation instruction. instruction only detection address error debugging.
3.4.1
Address error detection
read some cause such noise attempts fetch instruction from non-existent memory address during single chip mode. Code instruction, software interrupt generated address error detected. address error detection range further expanded writing unused areas program memory. Address trap reset generated case that instruction fetched from RAM, areas.
3.4.2
Debugging
Debugging efficiency increased placing instruction software break point setting address.
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TMP88PH40MG
External Interrupts
TMP88PH40MG external interrupt inputs. These inputs equipped with digital noise reject circuits (Pulse inputs less than certain time eliminated noise). INT0/P10 configured either external interrupt input input/output port, configured input port during reset. Noise reject control INT0/P10 function selection performed external interrupt control register (EINTCR).
Source INT0
INT0
Sub-Pin
Enable Conditions INT0EN=1
Release Edge (level) Falling edge
Digital Noise Reject Pulses less than 2/fc eliminated noise. Pulses 6/fc more considered signals. CGCR<DV1CK>=0).
Note When EINTCR<INT0EN> "0", even falling edge detected INT0 input. Note When with more than function used output change occurs data input/output status, interrupt request signal generated pseudo manner. this case, necessary perform appropriate processing such disabling interrupt enable flag.
External Interrupt Control Register
EINTCR (0037H) INT0EN (Initial value: *0** ****)
INT0EN
P10/INT0 configuration
input/output port INT0 (Port should input mode)
Note High-frequency clock [Hz], Don't care Note When external interrupt control register (EINTCR) overwritten,the noise canceller operate normally. recommended that external interrupts disabled using interrupt enable register (EIR).
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Interrupt Control Circuit
External Interrupts TMP88PH40MG
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TMP88PH40MG
Special Function Register
TMP88PH40MG adopts memory mapped system, peripheral control transfers performed through special function register (SFR) data buffer register (DBR). mapped address 0000H 003FH, mapped address 1F80H 1FFFH. This chapter shows arrangement special function register (SFR) data buffer register (DBR) TMP88PH40MG.
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H TC3DRB TC3CR Reserved Reserved Reserved Reserved Reserved Reserved Reserved TC1DRBL TC1DRBH Reserved Reserved Reserved Reserved Reserved Reserved TC4CR TC4DR TC3DRA Read Reserved P1DR Reserved P3DR P4DR Reserved P6DR Reserved Reserved Reserved Reserved P1CR Reserved Reserved Reserved TC1CR TC1DRAL TC1DRAH Write
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Special Function Register
TMP88PH40MG
Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH
Read ADCCRA ADCCRB ADCDRL ADCDRH EIRC EIRE EIRD CGCR Reserved Reserved Reserved TBTCR EINTCR Reserved SYSCR2 EIRL EIRH PSWL PSWH
Write
WDTCR1 WDTCR2
Note access reserved areas program. Note Cannot accessed. Note Write-only registers interrupt latches cannot read-modify-write instructions (Bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.).
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TMP88PH40MG
Address 1F80H 1F81H 1F82H 1F83H 1F84H 1F85H 1F86H 1F87H 1F88H 1F89H 1F8AH 1F8BH 1F8CH 1F8DH 1F8EH 1F8FH 1F90H 1F91H 1F92H 1F93H 1F94H 1F95H 1F96H 1F97H 1F98H 1F99H 1F9AH 1F9BH 1F9CH 1F9DH 1F9EH 1F9FH 1FA0H 1FA1H 1FA2H 1FA3H 1FA4H 1FA5H 1FA6H 1FA7H 1FA8H 1FA9H 1FAAH 1FABH 1FACH 1FADH 1FAEH 1FAFH ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 MCAPL MCAPH CMP1L CMP1H CMP2L CMP2H CMP3L CMP3H MDCRA MDCRB PDCRC SDREG MTCRA MTCRB UARTSR RDBUF SIOSR SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 PDCRA PDCRB Read P3ODE P4ODE P3CR P4CR P6CR UARTCRA UARTCRB TDBUF ATAS ATKEY SIOCR1 SIOCR2 Write
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Special Function Register
TMP88PH40MG
Address 1FB0H 1FB1H 1FB2H 1FB3H 1FB4H 1FB5H 1FB6H 1FB7H 1FB8H 1FB9H 1FBAH 1FBBH 1FBCH 1FBDH 1FBEH 1FBFH 1FC0H 1FC1H 1FC2H 1FC3H 1FC4H 1FC5H 1FC6H 1FC7H 1FC8H 1FC9H 1FCAH 1FCBH 1FCCH 1FFFH
ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1
Read EMGCRA EMGCRB MDOUTL MDOUTH MDCNTL MDCNTH MDPRDL MDPRDH CMPUL CMPUH CMPVL CMPVH CMPWL CMPWH EDCRA EDCRB EDSETL EDSETH ELDEGL ELDEGH AMPL AMPH EDCAPL EDCAPH Reserved Reserved
Write
EMGREL
WFMDR
Note access reserved areas program. Note Cannot accessed. Note Write-only registers interrupt latches cannot read-modify-write instructions (Bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.).
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TMP88PH40MG
Input/Output Ports
TMP88PH40MG contains input/output ports comprised pins.
Primary Function Port Port Port Port 1-bit port 8-bit port 6-bit port 4-bit port External interrupt input Motor control input/output Serial interface input/output, motor control circuit input Analog input motor control circuit output Secondary Functions
output ports contain latch, output data therefore retained latch. none input ports have latch, desirable that input data retained externally until read out, read several times before being processed. Figure shows input/output timing. timing which external data read from input/output ports state read cycle instruction execution. Because this timing cannot recognized from outside, transient input data such chattering needs dealt with program. timing which data forwarded input/output ports state write cycle instruction execution.
Fetch cycle Instruction execution cycle Fetch cycle Read cycle
Input strobe
Data input Input timing
Fetch cycle Instruction execution cycle
Fetch cycle (x),
Write cycle
Output latch pulse
Data Output
Output timing
Note: read/write cycle positions vary depending instructions.
Figure Example Input/Output Timing
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Input/Output Ports
Port (Only P10) TMP88PH40MG
When operation performed read from input/output port except programmable input/output ports, whether input value content output latch read depends instruction executed, shown below. Instructions which read content output latch (src) SET/CLR/CPL (src).b SET/CLR/CPL (pp).g (src).b, (pp).b, (src). ADD/ADDC/SUB/SUBB/AND/OR/XOR ADD/ADDC/SUB/SUBB/AND/OR/XOR MXOR (src), Instructions which read input value instructions other than those listed above ADD/ADDC/SUB/SUBB/AND/OR/XOR (src),(HL) instructions, (HL) side thereof. (src), (src), (HL) instructions, (src) side thereof
Port (Only P10)
Port 8-bit input/output port shared with external interrupt input. This port switched between input output modes using port input/output control register (P1CR). When reset, P1CR register initialized with port input mode. Also, output latch (P1DR) initialized when reset.
P1CR Data input Data output Control input
Output latch
External input Control input values
Figure Port
port input/output register
P1DR (00001H) P1CR (0000BH)
INT0
(Initial value: **** ***0)
(Initial value: **** ***0)
P1CR
port input/output control (Specify bitwise)
Input mode Output mode
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TMP88PH40MG
Port (P37 P30)
Port 8-bit input/output port. This port switched between input output modes using port Input/ output Control Register (P3CR). When reset, P3CR Register initialized with port input mode. Also, Output Latch (P3DR) initialized when reset. port contains bitwise programmable open-drain control. Port Open-drain Control Register (P3ODE) used select open-drain tri-state mode port. When reset, P3ODE Register initialized with tri-state mode selected port.
P3CRi Data input Data output Control output Control input
Output latch
External input Control input values Note:
Figure Port
port input/output registers
P3DR (00003H) P3CR (01F89H)
EMG1
(Initial value: 0000 0000) (Initial value: 0000 0000)
P3CR
port input/output control (Specify bitwise)
Input mode Output mode
P3ODE (01F83H)
(Initial value: 0000 0000)
P3ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note read-modify-write instruction executed while register selecting open-drain mode, output latch data read out. other instruction executed, external states read out. Note circuit output, P3DR output latch Note When using port input/output port, disable EMG1 circuit.
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Input/Output Ports
Port (Only P10) TMP88PH40MG
Port (P45 P40)
Port 6-bit input/output port shared with serial interface input/output. This port switched between input output modes using port input/output control register (P4CR). When reset, P4CR register initialized with port input mode. Also, output latch (P4DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P4ODE) used select open-drain tri-state mode port. When reset, P4ODE register initialized with tristate mode selected port.
P4CRi Data input Data output Control output Control input
Output latch
External input Control input values Note:
Figure Port
port input/output registers
P4DR (00004H) P4CR (01F8AH) TXD1 RXD1
PDU1
PDV1
PDW1 (Initial value: **00 0000) (Initial value: **00 0000)
P4CR
port input/output control (Specify bitwise)
Input mode Output mode
P4ODE (01F84H)
(Initial value: **00 0000)
P4ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note read-modify-write instruction executed while register selecting open-drain mode, output latch data read out. other instruction executed, external states read out. Note Don't care
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TMP88PH40MG
Port (P63 P60)
Port 4-bit input/output port shared with converter analog input. This port switched between input output modes using port input/output control register (P6CR), port output latch (P6DR), ADCCRA<AINDS>. When reset, P6CR Register P6DR output latch initialized while ADCCRA<AINDS> that have their inputs fixed When using port input port, corresponding bits input mode (P6CR P6DR reason output latch because necessary prevent current from flowing into shared data input circuit. When using port output port, P6CR Register's corresponding bits When using port analog input, corresponding bits analog input (P6CR P6DR Then ADCCRA<AINDS> conversion will start. ports used analog input must have their output latches beforehand. actual input channels conversion selected using ADCCRA<SAIN>. Although bits port used analog input used input/output ports, execute output instructions these ports during conversion. This necessary maintain accuracy conversion. Also, apply rapidly changing signals ports adjacent analog input during conversion. input instruction executed while P6DR output latch cleared data read from said bits.
Analog input AINDS SAIN P6CRi P6CRi input Data input (P6) Data output (P6) Control output (P6) Note Note SAIN selects input channels.
Figure Port
port input/output registers
P6DR (00006H) P6CR (01F8CH) AIN3 DBOUT AIN2 AIN1 AIN0 (Initial value: **** 0000) (Initial value: **** 0000)
AINDS (when using port input/output control (Specify bitwise) P6DR Inputs fixed P6DR Input mode
AINDS (when using P6DR Analog input mode (Note2) P6DR Input mode
P6CR
Output mode
Output mode
Note pins used analog input cannot output mode (P6CR because they become shorted with external signals. Note When read instruction executed bits this port which analog input mode, data read Note DBOUT output, P6DR (P63) output latch Note Don't care Note When using this port input mode (including analog input), manipulating other read-modify-write instructions. When read instruction executed bits this port that input, contents pins read that read-modify-write instruction executed, their output latches rewritten, making pins unable
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Input/Output Ports
Port (Only P10) TMP88PH40MG
accept input. read-modify-write instruction first reads data from eight bits after modifying them (bit manipulation), writes data eight bits output latches.)
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TMP88PH40MG
Watchdog Timer (WDT)
watchdog timer fail-safe system detect rapidly malfunctions such endless loops spurious noises deadlock conditions, return system recovery routine. watchdog timer signal detecting malfunctions programmed only once "reset request" "pseudo nonmaskable interrupt request". Upon reset release, this signal initialized "reset request". When watchdog timer used detect malfunctions, used timer provide periodic interrupt.
Note: Care must taken system design since watchdog timer functions operated completely effect disturbing noise.
Watchdog Timer Configuration
Reset release
fc/2 ,fc/2 fc/221,fc/222 fc/219,fc/220 fc/217,fc/218
Selector
Binary counters Clock Clear Overflow output
Reset request INTWDT interrupt request
Interrupt request
Internal reset
WDTEN WDTT
Writing disable code
Writing clear code
WDTOUT
Controller
0034H WDTCR1
0035H WDTCR2
Watchdog timer control registers
Figure Watchdog Timer Configuration
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Watchdog Timer (WDT)
Watchdog Timer Control TMP88PH40MG
Watchdog Timer Control
watchdog timer controlled watchdog timer control registers (WDTCR1 WDTCR2). watchdog timer automatically enabled after reset release.
6.2.1
Malfunction Detection Methods Using Watchdog Timer
malfunction detected, shown below. detection time, select output, clear binary counter. Clear binary counter repeatedly within specified detection time. malfunctions such endless loops deadlock conditions occur some reason, watchdog timer output activated binary-counter overflow unless binary counters cleared. When WDTCR1<WDTOUT> this time, reset request generated then internal hardware initialized. When WDTCR1<WDTOUT> "0", watchdog timer interrupt (INTWDT) generated. watchdog timer temporarily stops counting IDLE mode, automatically restarts (continues counting) when IDLE mode inactivated.
Note:The watchdog timer consists internal divider two-stage binary counter. When clear code written, only binary counter cleared, internal divider. minimum binary-counter overflow time, that depends timing which clear code (4EH) written WDTCR2 register, time WDTCR1<WDTT>. Therefore, write clear code using cycle shorter than time WDTCR1<WDTT>.
Example :Setting watchdog timer detection time 221/fc [s], resetting malfunction detection
(WDTCR2), (WDTCR1), 00001101B (WDTCR2), Clears binary counters. WDTT WDTOUT Clears binary counters (always clears immediately before after changing WDTT).
Within detection time
(WDTCR2),
Clears binary counters.
Within detection time
(WDTCR2), Clears binary counters.
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TMP88PH40MG
Watchdog Timer Control Register
WDTCR1 (0034H) WDTEN WDTT WDTOUT (Initial value: **** 1001)
WDTEN
Watchdog timer enable/disable
Disable (Writing disable code WDTCR2 required.) Enable NORMAL mode DV1CK DV1CK 226/fc 224/fc 222fc 220/fc
Write only
WDTT
Watchdog timer detection time
225/fc 223/fc 221fc 219/fc
Write only
WDTOUT
Watchdog timer output select
Interrupt request Reset request
Write only
Note After clearing WDTCR1<WDTOUT> "0", program cannot "1". Note High-frequency clock [Hz], Don't care Note WDTCR1 write-only register must used with read-modify-write instructions. WDTCR1 read, unknown data read. Note clear WDTCR1<WDTEN>, register accordance with procedures shown "6.2.3 Watchdog Timer Disable". Note watchdog timer disabled during watchdog timer interrupt processing, watchdog timer interrupt will never cleared. Therefore, clear watchdog timer clear code (4EH) WDTCR2 before disabling disable watchdog timer sufficient time before overflows. Note watchdog timer consists internal divider two-stage binary counter. When clear code (4EH) written, only binary counter cleared, internal divider. Depending timing which clear code (4EH) written WDTCR2 register, overflow time binary counter minimum time WDTCR1<WDTT>. Thus, write clear code using shorter cycle than time WDTCR1<WDTT>.
Watchdog Timer Control Register
WDTCR2 (0035H) (Initial value: **** ****)
WDTCR2
Write Watchdog timer control code
4EH: Clear watchdog timer binary counter (Clear code) B1H: Disable watchdog timer (Disable code) Others: Invalid
Write only
Note disable code valid only when WDTCR1<WDTEN> Note Don't care Note binary counter watchdog timer must cleared interrupt task. Note Write clear code (4EH) using cycle shorter than time WDTCR1<WDTT>. Note WDTCR2 write-only register must used with read-modify-write instructions. WDTCR2 read, unknown data read.
6.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> enables watchdog timer. Since WDTCR1<WDTEN> initialized during reset, watchdog timer enabled automatically after reset release.
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Watchdog Timer (WDT)
Watchdog Timer Control TMP88PH40MG
6.2.3
Watchdog Timer Disable
disable watchdog timer, register accordance with following procedures. Setting register other procedures causes malfunction microcontroller. interrupt master flag (IMF) "0". WDTCR2 clear code (4EH). WDTCR1<WDTEN> "0". WDTCR2 disable code (B1H).
Note:While watchdog timer disabled, binary counters watchdog timer cleared.
Example :Disabling watchdog timer
(WDTCR2), 04EH (WDTCR1), 0B101H Clears binary coutner WDTEN WDTCR2 Disable code
Table Watchdog Timer Detection Time (Example: MHz) Watchdog Timer Detection Time[s]
WDTT DV1CK 1.678 419.430 104.858 26.214 NORMAL Mode DV1CK 3.355 838.861 209.715 52.429
Note: watchdog timer disabled during watchdog timer interrupt processing, watchdog timer interrupt will never cleared. Therefore, clear watchdog timer clear code (4EH) WDTCR2 before disabling disable watchdog timer sufficient time before overflows.
6.2.4
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> cleared "0", watchdog timer interrupt request (INTWDT) generated binary-counter overflow. watchdog timer interrupt non-maskable interrupt which accepted regardless interrupt master flag (IMF). When watchdog timer interrupt generated while other interrupt including watchdog timer interrupt already accepted, watchdog timer interrupt processed immediately previous interrupt held pending. Therefore, watchdog timer interrupts generated continuously without execution RETN instruction, many levels nesting cause malfunction microcontroller. generate watchdog timer interrupt, stack pointer before setting WDTCR1<WDTOUT>.
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TMP88PH40MG
Example :Setting watchdog timer interrupt
02BFH (WDTCR1), 00001000B Sets stack pointer WDTOUT
6.2.5
Watchdog Timer Reset
When binary-counter overflow occurs while WDTCR1<WDTOUT> "1", watchdog timer reset request generated. When watchdog timer reset request generated, internal hardware reset. reset time maximum 24/fc max. MHz).
219/fc 217/fc
Clock Binary counter Overflow INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
(WDTT=11B)
Internal reset
(WDTCR1<WDTOUT>= "1")
reset occurs Write WDTCR2
Figure Watchdog timer Interrupt Reset
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Watchdog Timer (WDT)
Watchdog Timer Control TMP88PH40MG
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TMP88PH40MG
Time Base Timer (TBT)
Time Base Timer
time base timer generates time base scanning, dynamic displaying, etc. also provides time base timer interrupt (INTTBT). INTTBT Time Base Timer Interrupt generated first falling edge source clock divider output timing generator which selected TBTCK. after time base timer been enabled. divider cleared program; therefore, only first interrupt generated ahead interrupt period Figure interrupt frequency (TBTCK) must selected with time base timer disabled (TBTEN="0"). (The interrupt frequency must changed with disble from enable state.) Both frequency selection enabling performed simultaneously.
fc/223,fc/224 fc/221,fc/222 fc/216,fc/217 fc/214,fc/215 fc/213,fc/214 fc/212,fc/213 fc/211,fc/212 fc/29,fc/210
Source clock
Falling edge detector INTTBT interrupt request
TBTCK TBTCR Time base timer control register TBTEN
Figure Time Base Timer configuration
Source clock
TBTCR<TBTEN>
INTTBT interrupt request Interrupt period Enable
Figure Time Base Timer Interrupt
Example :Set time base timer frequency fc/216 [Hz] enable INTTBT interrupt.
(EIRL) (TBTCR) 00000010B (TBTCR) 00001010B TBTCK (Freq. set) TBTEN (TBT enable)
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Time Base Timer (TBT)
Time Base Timer TMP88PH40MG
Time Base Timer controled Time Base Timer control register (TBTCR). Time Base Timer Control Register
TBTCR (00036H) TBTEN TBTCK (Initial Value: 0000 0000)
TBTEN
Time Base Timer Enable Disable
Disable Enable NORMAL, IDLE Mode DV1CK=0 fc/2
DV1CK=1 fc/224 fc/222 fc/217 fc/215 fc/214 fc/213 fc/212 fc/210
fc/221 fc/216 fc/214 fc/213 fc/212 fc/211 fc/29
TBTCK
Time Base Timer interrupt Frequency select [Hz]
Note High-frequency clock [Hz], Don't care Note Always bit4 bit7 TBTCR register.
Table Time Base Timer Interrupt Frequency Example 20.0
Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL, IDLE Mode DV1CK 2.38 9.53 305.18 1220.70 2441.40 4882.83 9765.63 39063.00 DV1CK 1.20 4.78 153.50 610.35 1220.70 2441.40 4882.83 19531.25
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TMP88PH40MG
16-Bit TimerCounter (TC1)
Configuration
TC1S
INTTC1 interrupt
Decoder
Command start
Start
Clear
fc/211, fc/212 fc/27, fc/28 fc/23, fc/24
Source clock
Clear
16-bit up-counter
Match
Capture
TC1DRB
TC1DRA
ACAP1 TC1CK
16-bit timer register
TC1CR control register
Figure TimerCounter (TC1)
TimerCounter Control
TimerCounter controlled TimerCounter control register (TC1CR) 16-bit timer registers (TC1DRA TC1DRB). Timer Register
TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TC1DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0010H) Read/Write TC1DRBL (0012H) Read only
TimerCounter Control Register
TC1CR (000FH) ACAP1 TC1S TC1CK TC1M Read/Write (Initial value: 0000 0000)
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16-Bit TimerCounter (TC1)
TimerCounter Control TMP88PH40MG
ACAP1
Auto capture control
0:Auto-capture disable Stop counter clear Command start Reserved Reserved
1:Auto-capture enable
TC1S
start control
NORMAL, IDLE mode DV1CK TC1CK source clock select [Hz] operating mode select Timer mode Reserved Reserved Reserved fc/211 fc/27 fc/23 Reserved DV1CK fc/212 fc/28 fc/24
TC1M
Note High-frequency clock [Hz] Note timer register consists shift registers. value timer register becomes valid rising edge first source clock pulse that occurs after upper byte (TC1DRAH TC1DRBH) written. Therefore, write lower byte upper byte this order recommended write register with 16-bit access instruction). Writing only lower byte (TC1DRAL) does enable setting timer register. Note mode source clock, write TC1CR during TC1CR<TC1S>=00. Note timer registers, following relationship must satisfied. TC1DRA Note TC1CR Register bit7 "0". Note auto-capture function operative condition TC1. captured value fixed it's read after execution timer stop auto-capture disable. Read capture value capture enabled condition. Note Since up-counter value captured into TC1DRB source clock up-counter after setting TC1CR<ACAP1> "1". Therefore, read captured value, wait least cycle internal source clock before reading TC1DRB first time.
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TMP88PH40MG
Function
8.3.1 Timer mode
timer mode, up-counter counts using internal clock. When match between up-counter timer register (TC1DRA) value detected, INTTC1 interrupt generated up-counter cleared. After being cleared, up-counter restarts counting. Setting TC1CR<ACAP1> captures upcounter value into timer register (TC1DRB) with auto-capture function. auto-capture function operative condition TC1. captured value fixed it's read after execution timer stop auto-capture disable. Read capture value capture enabled condition. Since upcounter value captured into TC1DRB source clock up-counter after setting TC1CR<ACAP1> "1". Therefore, read captured value, wait least cycle internal source clock before reading TC1DRB first time. Table
TC1CK DV1CK Resolution [µs] 102.4 Maximum Time Setting 6.7108 0.4194 26.214
Source Clock TimerCounter (Example: MHz)
NORMAL, IDLE Mode DV1CK Resolution [µs] 204.8 12.8 Maximum Time Setting 13.4216 0.8388 52.428
Example :Setting timer mode with source clock fc/211 [Hz] generating interrupt second later MHz, CGCR<DV1CK> "0")
(TC1CR), 00000000B (TC1CR), 00010000B (EIRD). (TC1DRA), 2625H Sets timer register 211/fc 2625H) IMF= Enables INTTC1 IMF= Selects source clock mode Starts
Example :Auto-capture
(TC1CR), 01010000B (TC1DRB) ACAP1 Wait least cycle internal source clock Reads capture value
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16-Bit TimerCounter (TC1)
Function TMP88PH40MG
Timer start Source clock Counter TC1DRA
INTTC1 interruput request
Match detect Timer mode
Counter clear
Source clock
Counter
Capture
Capture
TC1DRB
ACAP1 Auto-capture
Figure Timer Mode Timing Chart
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TMP88PH40MG
8-Bit TimerCounter (TC3)
Configuration
TC3S
INTTC3 Interrupt Clear
fc/213, fc/2 fc/212, fc/2 fc/211 fc/2 fc/210, fc/2 fc/29 fc/2 fc/28 fc/2 fc/27 fc/2
Source clock
8-bit up-counter
Match detect
TC3DRB
Capture
TC3DRA
8-bit timer register
TC3CK
TC3CR
control register
Note: Function input operate depending port setting. more details, chapter "I/O Port".
ACAP
TC3S
Figure TimerCounter (TC3)
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8-Bit TimerCounter (TC3)
Configuration TMP88PH40MG
TimerCounter Control
TimerCounter controlled TimerCounter control register (TC3CR) 8-bit timer registers (TC3DRA TC3DRB). Timer Register Control Register
TC3DRA (001CH) TC3DRB (001DH) Read/Write (Initial value: 1111 1111)
Read only (Initial value: 1111 1111)
TC3CR (001EH)
ACAP
TC3S
TC3CK
TC3M (Initial value: *0*0 0000)
ACAP TC3S
Auto capture control start control
Auto capture Stop counter clear Start NORMAL, IDLE mode DV1CK=0 fc/2
DV1CK=1 fc/214 fc/213 fc/212 fc/211 fc/210 fc/29 fc/28 Reserved
fc/212 fc/211 fc/210 fc/29 fc/28 fc/27
TC3CK
source clock select [Hz]
TC3M
operating mode select
Timer mode Reserved
Note High-frequency clock [Hz], Don't care Note source clock when TimerCounter stops (TC3CR<TC3S> Note timer registers, following relationship must satisfied. TC3DRA Note When read instruction executed TC3CR, read don't care. Note program TC3DRA when timer running (TC3CR<TC3S>
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TMP88PH40MG
Function
9.3.1 Timer mode
timer mode, up-counter counts using internal clock. When match between up-counter timer register (TC3DRA) value detected, INTTC3 interrupt generated up-counter cleared. After being cleared, up-counter restarts counting. Setting TC3CR<ACAP> captures upcounter value into timer register (TC3DRB) with auto-capture function. count value during timer operation checked executing read instruction TC3DRB.
Note:00H which stored up-counter immediately after detection match captured into TC3DRB. (Figure 9-2)
Clock TC3DRA Up-counter
Match detect
TC3DRB
Note: case that TC3DRB
Figure Auto-Capture Function
Table Source Clock TimerCounter (Example: MHz)
TC3CK DV1CK Resolution [µs] 409.6 204.8 102.4 51.2 25.6 12.8 Maximum Time Setting [ms] 104.45 52.22 26.11 13.06 6.53 3.06 1.63 Resolution [µs] 819.2 409.6 204.8 102.4 51.2 25.6 12.8 NORMAL, IDLE mode DV1CK Maximum Time Setting [ms] 208.90 104.45 52.22 26.11 13.06 6.53 3.06
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8-Bit TimerCounter (TC3)
Configuration TMP88PH40MG
Timer start Source clock Counter
TC3DRA INTTC3 interrupt
Match detect
Counter clear
Timer mode
Source clock Counter
Capture
Capture
TC3DRB
TC3CR<ACAP> Auto capture
Figure Timer Mode Timing Chart
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TMP88PH40MG
8-Bit TimerCounter (TC4)
10.1 Configuration
fc/2 fc/2 fc/27, fc/28 fc/25, fc/26 fc/2 fc/2
Source Clock
Clear 8-bit up-counter TC4S Match detect
INTTC4 Interrupt
TC4M TC4S TC4CR TC4CK TC4DR
control register
8-bit timer register
Figure 10-1 TimerCounter (TC4)
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8-Bit TimerCounter (TC4)
10.1 Configuration TMP88PH40MG
10.2 TimerCounter Control
TimerCounter controlled TimerCounter control register (TC4CR) timer registers (TC4DR). Timer Register Control Register
TC4DR (001BH) Read/Write (Initial value: 1111 1111)
TC4CR (001AH)
TC4S
TC4CK
TC4M
Read/Write (Initial value: **00 0000)
TC4S
start control
Stop counter clear Start NORMAL, IDLE mode DV1CK fc/2
DV1CK fc/212 fc/28 fc/26 fc/24 Reserved Reserved Reserved Reserved
fc/27 fc/25 fc/23 Reserved Reserved Reserved
TC4CK
source clock select [Hz]
TC4M
operating mode select
Timer mode Reserved Reserved Reserved
Note High-frequency clock [Hz], Don't care Note timer registers, following relationship must satisfied. TC4DR Note start timer operation (TC4CR<TC4S> disable timer operation (TC4CR<TC4S> change TC4CR<TC4M, TC4CK> setting. During timer operation (TC4CR<TC4S> change either. setting programmed during timer operation, counting performed correctly. Note TC4CR read don't care when these bits read. Note change TC4DR setting when timer running.
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TMP88PH40MG
10.3 Function
10.3.1 Timer Mode
timer mode, up-counter counts using internal clock. When match between up-counter TC4DR value detected, INTTC4 interrupt generated up-counter cleared. After being cleared, up-counter restarts counting. Table 10-1 Internal Source Clock TimerCounter (Example: MHz)
TC4CK DV1CK Resolution [µs] 102.4 Maximum Time Setting [ms] 26.11 1.63 0.41 0.10 Resolution [µs] 204.8 12.8 NORMAL, IDLE Mode DV1CK Maximum Time Setting [ms] 52.22 3.28 0.82 0.20
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8-Bit TimerCounter (TC4)
10.1 Configuration TMP88PH40MG
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TMP88PH40MG
Motor Control Circuit (PMD: Programmable motor driver)
TMP88PH40MG contains channel motor control circuits used sinusoidal waveform output. This motor control circuit control brushless motors motors with without sensors. With primary functions like those listed below incorporated hardware, helps accomplish sine wave motor control easily, with software load significantly reduced. Rotor position detect function detect rotor position, with without sensors determine rotor position when detection matched number times, prevent erroneous detection position detection inhibit period immediately after PWM-on Independent timer timer capture functions motor control Contains one-channel magnitude comparison timer two-channel coincidence comparison timers that operate synchronously position detection waveform generating function Generates 12-bit with resolution frequency interrupt occurrence dead time PWM-on Protective function Provides overload protective function based protection signal input Emergency stop function case failure made stop emergency input timer overflow interrupt easily cleared software runaway Auto commutation/Auto position detection start function Comprised dual-buffers, activate auto commutation synchronously with position detection timer position detection period using timer function start auto position detection time Electrical angle timer function count degrees electrical angle with period range output counted electrical angle waveform arithmetic circuit Waveform arithmetic circuit Calculate output duty cycle from sine wave data voltage data which read from based electrical angle timer Output calculation result waveform synthesis circuit
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TMP88PH40MG
11.1 Outline Motor Control
following explains method controlling brushless motor with sine wave drive. brushless motor, rotor windings which apply electric current determined from rotor's magnetic pole position, current-applied windings changed rotor turns. rotor's magnetic pole position determined using sensor such hall detecting polarity change (zero-cross) points induced voltage that develops motor windings (sensorless control). sensorless case, induced voltage detected applying electric current phases applying electric current remaining other phase. this two-phase current case, there current application patterns shown Table 11-1, which changed synchronously with phases rotor. this two-phase current case, current time each phase degrees relative degrees induced voltage. Table 11-1 Current Application Patterns
Current Application Pattern Mode Mode Mode Mode Mode Mode Upper Transistor Lower Transistor Current Winding
Note: upper lower transistors controlled.
brushless motors, number revolutions controlled applied voltage, voltage application controlled PWM. this time, current windings need changed synchronism with phases voltage induced revolutions. Control timing cases where current windings changed means sensorless control illustrated Figure 11-4. three-phase motors, zero-crossing occurs times during cycle induced voltage (electrical angle degrees), that electrical angle from zero-cross point next degrees. Assuming that this period comprises mode, rotor position divided into modes zero-cross points. current application patterns shown above correspond these modes. timing which current application patterns changed (commutation) phase degrees electrical angle, with respect position detection induced voltage. Mode time obtained detecting zero-cross point some timing finding elapsed time from preceding zero-cross point. Because mode time corresponds degrees electrical angle, following applies case illustrated Figure 11-4. Current windings changeover (commutation) timing degrees electrical angle mode time/2 Position detection start timing Failure determination timing
degrees electrical angle mode time degrees electrical angle mode time
Timings calculated this way. position detection start timing needed prevent erroneous detection induced voltage reasons that even after current application turned off, current continues flowing motor reactance. Control exercised calculating above timings successively each zero-cross points detected times during degrees electrical angle activating commutation, position detection start, other operations according that timing. this way, operations synchronized phases induced voltage motor. timing needed motor control this example freely desired using internal timers microcontroller's unit. Also, sine wave control requires controlling duty cycle each pulse. Control duty cycles accomplished counting degrees electrical angle calculating sine wave data voltage data counted degree electrical angle. Page
TMP88PH40MG
Speed control Error handling, etc. circuit Three-phase Protective control Position detection Electrical angle timer Waveform calculation
current PDU, PDV,
motor
Power drive Upper phase: Lower phase:
Figure 11-1 Conceptual Diagram Motor Control
Mode Induced voltage Six-phase output
Zero crossing
phase
phase
phase
phase phase phase phase phase phase Position detection Commutation Position detection start Failure determination
Internal signal
Figure 11-2 Example Sensorless Motor Control Timing Chart
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TMP88PH40MG
11.2 Configuration Motor Control Circuit
motor control circuit consists various units. These include position detection unit detect zero-cross points induced voltage position sensor signal, timer unit generate events three instances electrical angle timing, three-phase output unit produce three-phase output waveforms. Also included electrical angle timer unit count degrees electrical angle waveform arithmetic unit calculate sinusoidal waveform output duty cycles. input/output units configured shown diagram below. When using ports function, Port input/output control register (P3CRi) input ports, output ports, data output latch (P3i) then port input/output control register Other input/output ports same function.
core
Data address buses
Motor control circuit Timer circuit Electrical angle timer circuit Waveform generation circuit Waveform arithmetic circuit
Position detection circuit
Position signal input
Error detection input
Figure 11-3 Block Diagram Motor Control Circuit
Note Always instruction data 16-bit data registers. Note circuit initially enabled. output, input port (P36) high level disable circuit before using output. Note circuit initially enabled. When using Port input/output ports, disable EMG. Note When going STOP mode, sure turn functions before entering STOP mode.
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TMP88PH40MG
11.3 Position Detection Unit
Position Detection Unit identifies motor's rotor position from input patterns position signal input port. Applied this position signal input port voltage status motor windings case sensorless motors Hall element signal case motors with sensors included. expected patterns corresponding specific rotor positions Output Register (MDOUT) beforehand, when input position signal expected value match rotation, position detection interrupt (INTPDC) generated. Also, unmatch detection mode used detect direction motor rotation, where when status position detection input port changes from status which start sampling, position detection interrupt generated. three-phase brushless motors, there patterns position signals, each mode, summarized Table 11-2 from timing chart Figure 11-2. Once predicted position signal pattern MDOUT register, position detection interrupt generated moment position signal input port goes mode indicated this expected value. position signals each phase diagram internal signals which cannot observed from outside. Table 11-2 Position Signal Input Patterns
Position Detection Mode Mode Mode Mode Mode Mode Mode Phase (PDU) Phase (PDV) Phase (PDW)
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TMP88PH40MG
11.3.1 Configuration position detection unit
output register MDOUT E,D,C Position signal expected value Position signal input PDNUM Latch Clock selector
Sampling control
Latch
MDOUTsync Coincidence detection Erroneous detection prevention circuit Counter Position detection interrupt INTPDC
fc/4 Sampling control circuit
Reset control
Timer interrupt INTTMR2/3 PWMON
Delay circuit
SDREG Sampling delay register
PDCRA PDCRB Position detection control register
Figure 11-4 Configuration Position Detection Circuit
position detection unit controlled Position Detection Control Register (PDCRA, PDCRB). After position detection function enabled, unit starts sampling position detection port with Timer software. case ordinary mode, when status position detection input port matches expected value Output Register, unit generates position detection interrupt finishes sampling, waiting start next sampling. When unmatch detection mode selected position detection, unit stores sampled status position detection port memory time started sampling. When port input status changes from status which start sampling, interrupt generated. unmatch detection mode, port status start sampling read (PDCRC<PDTCT>). When starting stopping position detection synchronously with timer, position detection started Timer position detection stopped Timer Sampling mode selected from three modes available: mode where sampling performed only while mode where sensors such Hall elements sampled regularly, mode where sampling performed while lower side conducting current (when performing sampling only while DUTY must three phases common). When sampling mode selected detecting position while lower phases conducting current, sampling performed period from when sampling delay time elapsed after lower side started conducting current till when current application turned off. Sampling performed independently each phase, sampling result retained while sampling idle. while sampling some phase idle, input expected value other phase being sampled match, position detected interrupt generated.
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sampling delay provided modes where sampling made while lower phases conducting current. helps prevent erroneous detection noise that occurs immediately after transistor turns starting sampling time after signal turned When detecting position while lower phases conducting current, method selected whether recount occurrences matched position detection after being compared each signal (logical three-phase signals) (e.g., starting from each cycle) counting occurrences matching continuously PDCRB<SPLMD> used enable/disable recounting occurrences matching while on).
11.3.2 Position Detection Circuit Register Functions
PDCRC Hold result position detection edge (Detect position detected position) Monitor sampling status Hold position signal input status These bits hold comparison result position detection falling rising edge pulse. Bits when position detected falling rising edge, respectively. They show whether position detected current pulse, during off, immediately preceding pulse. When read, this shows sampling status. This holds status position signal input time position detection started unmatch mode.
EMEM
SMON PDTCT
PDCRB SPLCK SPLMD Sampling period Sampling mode Select fc/22, fc/23, fc/24, fc/25 position detection sampling period. Select three modes: sampling only when signal active (when on), sampling regularly, sampling when lower side phases conducting current. ordinary mode, when port status expected value match continuously match many times sampling counts set, position detection signal output interrupt generated. unmatch detection mode, when said status value match continuously unmatch many times sampling counts set, position detection signal output interrupt generated.
PDCMP
Sampling count
PDCRA Sampling stopped software setting this (e.g., writing this register). Sampling performed before stopping when position detection results match, position detection interrupt generated, with sampling thereby stopped. Sampling started setting this (e.g., writing this register). Sampling stopped trigger from Timer setting this Sampling performed before stopping when position detection results match, position detection interrupt generated, with sampling thereby stopped. Sampling started trigger from Timer setting this Select whether three pins (PDU/PDV/PDW) (PDU only) position signal input. When selected, expected values ignored. When performing position detection with pins other than PDU, position signal input masked setting unused pin(s) output. When performing sampling while occurrences matching recounted each time signal turns setting this (when recounting occurrences matching, count reset each time turns off). When this occurrences matching counted continuously regardless interval. Setting this selects ordinary mode where position detected when expected value register port input unmatch then match. Setting this selects unmatch detection mode where position detected time port status changes another from status which when sampling started. position detection function activated setting this
SWSTP
Stop sampling software
SWSTT SPTM3 STTM2
Start sampling software Stop sampling using Timer Start sampling using Timer Number position signal input pins
PDNUM
RCEN
Recount occurrences matching when
DTMD
Position detection mode
PDCEN
Position detection function
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TMP88PH40MG
SDREG SDREG Sampling delay time which stop sampling order prevent erroneous detection noise that occurs immediately after output turns (immediately after transistor turns on). (Figure 11-5)
PWMON period
Position detection match Sampling period Sampling delay Sampling pause Align arrow start counter switching.
Number position detection matches Match
Figure 11-5 Position Detection Sampling Timing with PWMON Period Selected
EMEM: Detects when position detection match occurred (the value held aftr position detection). (Check whether sampling started previous pulse)
CASE1 CASE2 CASE3 CASE4
EMEM value
Match (Sampling start)
match with means that started previous pulse.
Erroneous detection
Figure 11-6 Detection Timing Position Detection Position
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Position Detection Circuit Registers [Addresses (PMD1)]
PDCRC (01FA2H) EMEM SMON PDTCT (Initial value: **00 0000)
EMEM
Hold result position detection edge (Detect position detected position) Monitor sampling status Hold position signal input status
Detected current pulse Detected while Detected current pulse Detected preceding pulse Sampling idle Sampling progress Holds status position signal input during unmatch detection mode. Bits correspond phases.
SMON PDTCT
PDCRB (01FA1H)
SPLCK
SPLMD
PDCMP
(Initial value: 0000 0000)
fc/22 [Hz] (200 MHz) SPLCK Select sampling input clock fc/23 fc/24 fc/25 (400 MHz) (800 MHz) (1.6 MHz)
SPLMD
Sampling mode
Sample when Sample regularly Sample when lower phases conducting current Reserved times (Counts assumed time.)
PDCMP
Position detection matched counts
Note: When changing setting, keep PDCEN reset (disable position detection function).
PDCRA (01FA0H)
SWSTP
SWSTT
SPTM3
STTM2
PDNUM
RCEN
DTMD
PDCEN (Initial value: 0000 0000)
SWSTP SWSTT SPTM3 STTM2 PDNUM RCEN DTMD PDCEN
Stop sampling software Start sampling software Stop sampling using Timer Start sampling using Timer Number position signal input pins Recount occurrences matching when Position detection mode Enable/Disable position detection function
operation Stop sampling operation Start sampling Disable Enable Disable Enable Compare three pins (PDU/PDV/PDW) Compare (PDU) only Continue counting from previously Recount each time turns Ordinary mode Unmatch detection mode Disable Enable (Sampling starts)
Note: Read-modify-write instructions, such manipulation instruction, cannot access PDCRA because contains write only bit.
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TMP88PH40MG
SDREG (01FA3H)
(Initial value: *000 0000)
SDREG
Sampling delay
23/fc bits maximum 50.8 resolution MHz)
Note: When changing setting, keep PDCEN reset (disable position detection function).
11.3.3 Outline Processing Position Detection Unit
Software mode pattern Hardware
Write expected value
MDOUT
Start position detection Sample position signal input Match with expected value? Increment matching counts Specified count reached?
INTTMR2
Timer unit
Interrupt handling Increment mode counts
INTPDC
Generate INTPDC interrupt position detection
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TMP88PH40MG
11.4 Timer Unit
Mode timer control registers MTCRA Overflow fc/4 Clock selector
Mode timer Timer reset control circuit
Debug output
MTCRB Capture overwrite
Capture control circuit
Capture
Overload protective interrupt INTCLM Position detection interrupt INTPDC
MCAP Mode capture register Timer interrupt INTTMR1 (Commutation) CMP1 Timer compare register Timer magnitude comparison Timer interrupt INTTMR2 (Position detection start)
CMP2
Timer matching comparison
CMP3
Timer matching comparison
Timer interrupt INTTMR3 (Overflow)
Figure 11-7 Timer Circuit Configuration
timer unit counter (mode timer) which cleared position detection interrupt (INTPDC). Using this counter, generate three types timer interrupts (INTTMR1 These timer interrupts used produce commutation trigger, position detection start trigger, etc. Also, mode timer capture function which automatically captures register data synchronism with position detection overload protection. This capture function allows motor revolutions calculated measuring position detection intervals.
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TMP88PH40MG
11.4.1 Configuration Timer Unit
timer unit consists mainly mode timer, three timer comparator, mode capture register, controlled timer control registers timer compare registers. mode timer reset signal from position detection circuit, Timer overload protective circuit. mode timer overflows without being reset, stops FFFFH sets overflow flag control register. value mode timer during counting read capturing count software reading capture register. Timer Timers generate interrupt signal magnitude comparison matching comparison, respectively. Therefore, Timer generate interrupt signal even when could write compare register time counter value time writing happens exceed register's value. When Timers interrupts occurs, next interrupts enabled writing value respective compare registers (CMP1, CMP2, CMP3). When capturing position detection enabled, capture register timer value captured each time position detected. this way, capture register always holds latest value.
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TMP88PH40MG
11.4.1.1 Timer Circuit Register Functions
MTCRB Debug output produced setting this Because interrupt signals interrupt control circuit used each interrupt, hardware debugging without software delays possible. debug output diagram (Figure 11-8). Output ports: PMD1. This shows that timer overflowed. When this timer value captured using overload protection signal (CL) trigger. When this timer value captured software (e.g., writing this register). When this timer value captured using position detection signal trigger.
DBOUT
Debug output
TMOF CLCP SWCP PDCCP
Mode timer overflow Capture mode timer overload protection Capture mode timer software Capture mode timer position detection
MTCRA TMCK RBTM3 RBCL SWRES RBPDC Select clock Reset mode timer from Timer Reset mode timer overload protection Reset mode timer software Reset mode timer position detection Enable/disable mode timer Select timer clock. When this mode timer reset trigger from Timer When this mode timer reset overload protection signal (CL) trigger. When this mode timer reset software (e.g., writing this register) When this mode timer reset position detection signal trigger. mode timer started setting this Therefore, Timers must with before setting this bit. this after setting CMP, settings become ineffective.
TMEN
MCAP
Mode capture
Position detection interval read out.
CMP1 CMP2 CMP3
Timer (commutation) Timer (position detection start) Timer (overflow)
Timers enabled while mode timer operating. interrupt generated once setting corresponding this register. interrupt disable when interrupt generated timer reset. timer again, register back again even data same.
Timer interrupt (commutation) Timer interrupt (position detection start) Timer interrupt position detection interrupt Debug output (P67, P77)
Figure 11-8 DBOUT Debug Output Diagram
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TMP88PH40MG
Timer Circuit Registers [Addresses (PMD1)]
MTCRB (01FA5H) DBOUT TMOF CLCP SWCP PDCCP (Initial value: 0*0*0 000*)
DBOUT TMOF CLCP SWCP PDCCP
Debug output Mode timer overflow Capture mode timer overload protection Capture mode timer software Capture mode timer position detection
Disable Enable (P67 PMD1, PMD2) overflow Overflowed Disable Enable operation Capture Disable Enable
Note: Read-modify-write instructions, such manipulation instruction, cannot access MTCRB because contains write-only bit.
MTCRA (01FA4H)
TMCK
RBTM3
RBCL
SWRES
RBPDC
TMEN (Initial value: 0000 0000)
000: fc/23 (400 MHz) 010: fc/24 (800 MHz) 100: fc/25 (1.6 MHz) TMCK Select clock 110: fc/26 (3.2 MHz) 001: fc/27 (6.4 MHz) 011: Reserved 101: Reserved 111: Reserved RBTM3 RBCL SWRES RBPDC TMEN Reset mode timer from Timer Reset mode timer overload protection Reset mode timer software Reset mode timer position detection Enable/disable mode timer Disable Enable Disable Enable operation Reset Disable Enable Disable Enable timer start
Note When changing MTCRA<TMCK> setting, keep MTCRA<TMEN> reset (disable mode timer). Note Read-modify-write instructions, such manipulation instruction, cannot access MTCRA because contains write-only bit.
MCAP (01FA7H, 01FA6H)
(Initial value: 0000 0000 0000 0000)
MCAP
Mode capture
Position detection interval
CMP1 (01FA9H, 01FA8H)
(Initial value: 0000 0000 0000 0000)
CMP2 (01FABH, 01FAAH)
(Initial value: 0000 0000 0000 0000)
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TMP88PH40MG
CMP3 (01FADH, 01FACH)
(Initial value: 0000 0000 0000 0000)
CMP1 CMP2 CMP3
Timer Timer Timer
Magnitude comparison compare register Matching comparison compare register Matching comparison compare register
Note: Read-modify-write instructions, such manipulation instruction, cannot access MTCRB MTCRA register because these registers contain write-only bits.
11.4.1.2 Outline Processing Timer Unit
Software Interrupt handling Read MCAP Calculate timer value MCAP MCAP MCAP timer Processing unnecessary
CMP1, CMP2, CMP3 Commutation INTTMR1 MCAP
Hardtware INTPDC Position detection unit
Start Start Mode timer count Mode timer MCAP Clear mode timer Greater than compare Match with compare Match with compare Generate INTTMR1 interrupt Generate INTTMR2 interrupt Generate INTTMR3 interrupt timer
Processing unnecessary
Position detection start INTTMR2 position detection Error determination unit INTTMR3
timer
Interrupt handling error handling
timer
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TMP88PH40MG
11.5 Three-phase Output Unit
Three-phase Output Unit function generate three-phase waves with desired pulse width commutation function capable brushless motor control. addition, protective functions such overload protection emergency stop functions necessary protect power drive unit, dead time adding function which helps prevent in-phase upper/lower transistors from getting shorted simultaneous turn-on when switched over. output (U,V,W,X,Y,Z), port register PxDR PxCR output initially active low, that output needs used active high, MDCRA Register accordingly.
11.5.1 Configuration three-phase output unit
three-phase output unit consists pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop overload), dead time control circuit.
11.5.1.1 Pulse width modulation circuit (PWM waveform generating unit)
This circuit produces three-phase independent waveforms with equal frequency. waveform mode, triangular wave modulation sawtooth wave modulation selected using Control Register (MDCRA) frequency using Period Register (MDPRD). following shows relationship between value this register counter clock MDCRB Register, PWMCK. Sawtooth wave PWM: MDPRD Register value -PWM frequency PWMCK Triangular wave PWM: MDPRD Register value -PWM frequency WMCK Period Register (MDPRD) comprised dual-buffers, that CMPU, Register updated with period. When waveform arithmetic circuit operating, waveform output unit receives calculation results from waveform arithmetic circuit using results CMPU, Register value, outputs independent three-phase waveforms. When waveform calculation function enabled waveform arithmetic circuit transfer calculation results into CMPU Registers enabled (with EDCRA Register CMPU Registers disabled against writing. When waveform calculation function enabled (with EDCRA Register transfer calculation results into CMPU, Registers disabled (with EDCRA Register calculation results transferred buffers CMPU, Registers, output port. Read-accessing CMPU, registers read calculation results waveform arithmetic circuit that have been input buffer. After changing read calculation result data software, writing changed data CMPU, registers enables arbitrary waveform other than sinusoidal wave output. When registers read after writing, values written registers read accessed before calculation results transferred after calculation finished.
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TMP88PH40MG
[Sawtooth wave]
MDCNT
Data update
[MDPRD] [CMPU] Time PWMU waveform [Triangular wave] MDCNT Data update
[MDPRD] [CMPU] Time PWMU waveform
Figure 11-9 Waveforms
values Compare Registers (CMPU/V/W) carrier wave generated Counter (MDCNT) compared relative magnitude comparator produce waveforms. Counter 12-bit up/down counter with MHz) resolution. three-phase output control, methods generating three-phase waveforms set. Three-phase independent mode: Values independently three-phase Compare Registers produce three-phase independent waveforms. This method used produce sinusoidal other desired drive waveforms. Three-phase common mode: value only U-phase Compare Register produce three in-phase waveforms using phase value. This method used motor square wave drive. three-phase Compare Registers each have comparison register comprise dual-buffer structure. values Compare Registers loaded into their respective comparison registers synchronously with period.
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TMP88PH40MG
11.5.1.2 Commutation control circuit
Output ports controlled depending contents Output Register (MDOUT). contents this register divided into two, selecting synchronizing signal port output, setting port output. synchronizing signal selected from Timers position detection signal, without sync. Port output synchronized this synchronizing signal before being further synchronized signal sync. MDOUT Register's synchronizing signal select becomes effective immediately after writing. Other bits dual-buffered, updated selected synchronizing signal. Example: Commutation timing timer period with synchronization specified
INTTMR
Commutation
Output ports active high active independently each other using MDCRA Register bits Furthermore, phases individually selected between output output using MDOUT Register bits When output selected, waveforms output; when output selected, waveform which fixed high output. MDOUT Register bits expected position signal value position detection circuit.
control register
MDCRA
control synchronizing clock Up/Down counter interrupt INTPWM
fc/2
MDCRB
Clock selector Selector/ Latch Selector/ Latch
MDCNT
Stop MDCNT
period register
MDPRD
compare register
CMPU
PWMU Buffer Three-phase common/ Three-phase
CMPV
PWMV
Buffer
CMPW
PWMW Buffer
Figure 11-10 Pulse Width Modulation Circuit
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output register
MDOUT
synchronizing clock fc/4 Selector
Position detection interrupt INTPDC Timer interrupt INTTMR1 Timer interrupt INTTMR2
Selector
Gate control Reset
Latch
MDOUT sync PWMU
PWMV
PWMW
Figure 11-11 Commutation Control Circuit
Dead time register fc/8
delay circuit delay circuit
control register MDCRA
delay circuit
Figure 11-12 Dead Time Circuit
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11.5.2 Register Functions Waveform Synthesis Circuit
MDCRB PWMCK Select counter clock Select counter clock.
MDCRA HLFINT Select half-period interrupt When this INTPWM generated every half period triangular wave peak valley) case center output PINT other cases, this setting meaning. Select whether duty cycle independently three phases using CMPU Registers common three phases setting CMPU Register only. Select upper-phase output port polarity. Make sure waveform synthesis function (MDCRA Register idle before selecting this port polarity. Select lower-phase output port polarity. Make sure waveform synthesis function (MDCRA Register idle before selecting this port polarity. Select frequency which generate interrupt from four choices available: every period once every periods. When setting this altered while operating, interrupt generated time altered. Select mode. mode edge (sawtooth wave), mode center (triangular wave). When enabling this circuit (for waveform output), sure output port polarity other bits this register (other than MDCRA beforehand.
DTYMD POLH POLL
DUTY mode Upper-phase port polarity Lower-phase port polarity
PINT
interrupt frequency
PWMMD PWMEN
mode Enable/Disable waveform generation circuit
Dead time dead time between upper-phase lower-phase outputs.
MDOUT UPDWN counter flag This indicates whether counter counting down. When edge (sawtooth wave) selected, always data compared with position detection input port. comparison data adopted expected value simultaneously when port output sync settings made with MDOUT reflected ports. (This expected position detection input value output with MDOUT next time.) Select whether synchronize port output period after being synchronized synchronizing signal selected with SYNCS. selected synchronized PWM, output kept waiting next after being synchronized with SYNCS. Waveform settings overwritten settings written register during this time, output generated with those settings. W-phase port outputs. (See Table 11-3) Select synchronizing signal with which output UVW-phase settings ports. synchronizing signal selected from Timers position detection, asynchronous. Select asynchronous when initial setting, otherwise above setting isn't reflected immediately. W-phase port outputs. (See Table 11-3)
PDEXP
Mode compare register
PSYNC
Select synchronization
WPWM VPWM UPWM
Control UVW-phase outputs
SYNCS
Select port output sync signal
Control UVW-phase outputs
MDCNT
counter
This 12-bit read-only register used count periods.
MDPRD
period
This register determines period, dual-buffered, allowing period altered even while counter operating. buffers loaded every period. When selected counter clock, make sure least significant
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TMP88PH40MG
CMPU CMPV CMPW
pulse width
This comparison register determines pulse widths output respective phases. This register dual-buffered, pulse widths determined comparing buffer counter.
Waveform Synthesis Circuit Registers [Addresses (PMD1)]
MDCRB (01FAFH) PWMCK (Initial value: **** **00)
fc/2 [Hz] (100 MHz) PWMCK counterSelect clock fc/22 fc/23 fc/24 (200 MHz) (400 MHz) (800 MHz)
Note: When changing setting, keep PWMEN reset (disable wave form synthesis function).
MDCRA (01FAEH)
HLFINT
DTYMD
POLH
POLL
PINT
PWMMD
PWMEN (Initial value: 0000 0000)
HLFINT DTYMD POLH POLL
Select half-period interrupt DUTY mode Upper-phase port polarity Lower-phase port polarity
Interrupt specified PINT Interrupt every half period when PINT phase common Three phases independent Active Active high Active Active high Interrupt every period Interrupt once every periods Interrupt once every periods Interrupt once every periods mode0 (Edge: Sawtooth wave) mode1 (Center: Triangular wave) Disable Enable (Waveform output)
PINT
Select interrupt (trigger)
PWMMD PWMEN
mode Enable/disable waveform synthesis function
(01FBEH)
(Initial value: **00 0000)
Dead time
23/fc (maximum 25.2 MHz)
Note: When changing setting, keep MDCRA<PWMEN> reset (disable wave form synthesis function).
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Motor Control Circuit (PMD: Programmable motor driver)
TMP88PH40MG
MDOUT (01FB3H, 01FB2H)
UPDWN SYNCS
PDEXP
PSYNC
WPWM
VPWM
UPWM (Initial value: 00000000 00000000)
UPDWN
counter flag Comparison register position detection Select synchronization W-phase output V-phase output U-phase output
Counting Counting down W-phase expected value V-phase expected value U-phase expected value Asynchronous Synchronized level output waveform output level output waveform output level output waveform output Asynchronous Synchronized position detection Synchronized Timer Synchronized Timer
PDEXP
PSYNC WPWM VPWM UPWM
SYNCS
Select port output synchronizing signal Control W-phase output Control V-phase output Control U-phase output
table
11.5.3 Port output with UOC/VOC/WOC bits UPWM/VPWM/WPWM bits
Table 11-3 Example Output Settings
U-phase output polarity: Active high (POLH,POLL UPWM output phase
U-phase output polarity: Active (POLH,POLL UPWM output phase
level output phase phase
level output phase phase
phase
phase
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TMP88PH40MG
MDCNT (01FB5H, 01FB4H)
(Initial value: ****000000000000)
counter
period counter value
MDPRD (01FB7H, 01FB6H)
(Initial value: ****000000000000)
period
period MDPRD 010H
CMPU (01FB9H, 01FB8H)
(Initial value: ****000000000000)
CMPV (01FBBH, 01FBAH)
(Initial value: ****000000000000)
CMPW (01FBDH, 01FBCH)
(Initial value: ****000000000000)
CMPU CMPV CMPW
compare register compare register compare register
U-phase duty cycle V-phase duty cycle W-phase duty cycle
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Motor Control Circuit (PMD: Programmable motor driver)
TMP88PH40MG
11.5.4 Protective Circuit
This circuit consists protective circuit overload protective circuit. These circuits activated driving their respective port inputs active.
control register EMGCRB EMGCRA Under protection disable code register EMGREL MDOUT protective control
Overload protective input Timer interrupt INTTMR1 synchronizing clock sync Overload protective interrupt INTCLM Stop MDCNT
detection
Reset control
Overload protective control
input INTEMG interrupt
Figure 11-13 Configuration Protective Circuit
protective circuit This protective circuit used emergency stop, when protective circuit enabled. When signal input port goes active (negative edge triggered), ports immediately disabled high-impedance against output interrupt (INTEMG) generated. Control Register (EMGCRA) used protection. EMGCRA<EMGST> shows value when read, means that protective circuit operating. return from protective state, reset MDOUT Register bits EMGCRA<RTE> Returning from protective state effective when protective input been released back high. disable function, data "5AH" "A5H"sequentially disable Register (EMGREL) reset EMGCRA<EMGEN> When function disabled, interrupts (INTEMG) generated. protective circuit initially enabled. Before disabling fully study adequacy. Overload protective circuit overload protective circuit using Control Registers (EMGCRA/B). activate overload protection, EMGCRB<CLEN> enable overload protective circuit. circuit starts operating when overload protective input pulled low. return from overload state, there three methods use: return timer (EMGCRB<RTTM1>), return sync (EMGCRB<RTPWM>), return manually (EMGCRB<RTCL>). These methods usable when overload protective input been released back high.
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TMP88PH40MG
number times overload protective input sampled using EMGCRA<CLCNT>. sampling times range times period (when MHz). level detected many times specified number, overload protection assumed. output disabled phases during overload protection using EMGCRB<CLMD>. This facility allows selecting disable phases, phases, phases, upper phases/all lower phases. When selected disable upper phases/all lower phases, port output determined their turn-on status immediately before being disabled. When more upper phases active, upper phases turned lower phases turned off; when more lower phases active, upper phases turned lower phases turned When output phase off, output inactive (low case high active). When overload protective circuit disabled, overload protective interrupts (INTCLM) generated.
(Current) setting current Overload protection setting current
Input Input output ("H" active) Overload protection (Output off) protection (High-Z output)
(time)
Figure 11-14 Example Protection Circuit Operation
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Motor Control Circuit (PMD: Programmable motor driver)
TMP88PH40MG
11.5.5 Functions Protective Circuit Registers
EMGREL
disable
protective circuit disable from disabled state writing "5AH" "A5H" this register that order. After that, EMGCRA Register needs set.
EMGCRB Return from overload protective state When this motor control circuit returned from overload protective state software (e.g., writing this register). Also, current state known reading this bit. MDOUT outputs return from overload protective state remain before overload protective input driven active. When this motor control circuit returned from overload protective state sync. RTCL RTCL priority. When this motor control circuit returned from overload protective state Timer sync. RTCL RTCL priority. status overload protection known reading this bit. Select phases disabled against output during overload protection. This facility allows selecting disable phases, phases, phases, upper phases/all lower phases. stop counter during overload protection. Enable disable overload protective function.
RTCL
RTPWM RTTM1 CLST CLMD
Return sync Return timer sync Overload protective state Select output disabled phases during overload protection Stop counter during overload protection Enable/Disable overload protection
CNTST CLEN
EMGCRA CLCNT EMGST Overload protection sampling time protective state Return from protective state length time overload protective input port sampled. status protection known reading this bit. motor control circuit returned from protective state setting this When returning, MDOUT Register bits Then EMGCRA Register MDOUT waveform output. Then MDCRA Register. protective circuit activated setting this This circuit initially enabled. disable this circuit, make sure code written EMGREL1 Register beforehand.)
EMGEN
Enable/Disable protective circuit
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TMP88PH40MG
Protective Circuit Registers [Addresses (PMD1)]
EMGREL (01FBFH) (Initial value: 0000 0000)
EMGREL
disable
disable writing then A5H.
Note: Read-modify-write instructions, such manipulation instruction, cannot access EMGREL register because this register write only.
EMGCRB (01FB1H)
RTCL
RTPWM
RTTM1
CLST
CLMD
CNTST
CLEN (Initial value: 0000 0000)
RTCL
Return from overload protective state Enable/Disable return from overload protective state sync Enable/Disable return from overload protective state timer Overload protective state
operation Return from protective state Disable Enable
RTPWM
Disable Enable operation Under protection phases disabled against output phases disab
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