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TLCS-870/X Series
TMP88FW44FG
TMP88FW44FG
information contained herein subject change without notice. 021023 TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A Toshiba products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage Toshiba products listed this document shall made customer's risk. 021023_B products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. 060106_Q information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights TOSHIBA others. 021023_C products described this document include products subject foreign exchange foreign trade laws. 021023_F discussion reliability microcontrollers predicted, please refer Section chapter entitled Quality Reliability Assurance/Handling Precautions. 030619_S
2006 TOSHIBA CORPORATION Rights Reserved
Revision History
Date 2006/4/28 2006/6/2 2007/5/10 2007/6/28 2007/7/10 Revision First Release Contents Revised Contents Revised Contents Revised Contents Revised
Table Contents
TMP88FW44FG
Features Assignment Block Diagram Names Functions
Functional Description
Functions Core
Memory Address Map. Program Memory (ROM) Data Memory (RAM) System Clock Control Circuit
Clock Generator Timing Generator Standby Control Circuit Controlling Operation Modes External Reset Input Adress Trap Reset Watchdog Timer Reset System Clock Reset
2.1.1 2.1.2 2.1.3 2.1.4
2.1.5
2.1.4.1 2.1.4.2 2.1.4.3 2.1.4.4 2.1.5.1 2.1.5.2 2.1.5.3 2.1.5.4
Reset Circuit
Interrupt Control Circuit
Interrupt latches (IL39 IL2) Interrupt enable register (EIR) Interrupt Sequence
Interrupt acceptance processing packaged follows. Saving/restoring general-purpose registers
Using Automatic register bank switcing Using register bank switching Using PUSH instructions Using data transfer instructions
3.2.1 3.2.2
Interrupt master enable flag (IMF) Individual interrupt enable flags (EF39 EF3)
3.3.1 3.3.2
3.3.3 3.4.1 3.4.2
3.3.2.1 3.3.2.2 3.3.2.3 3.3.2.4
Software Interrupt (INTSW) External Interrupts
Address error detection Debugging
Interrupt return
Special Function Register
Input/Output Ports
5.10 5.11 5.12 5.13 Port (P03 P00) Port (P17 P10) Port (P22 P20) Port (P37 P30) Port (P47 P40) Port (P57 P50) Port (P67 P60) Port (P77 P70) Port (P87 P80) Port (P97 P90) Port (PA7 PA0) Port (PB7 PB0) Port (PC3 PC0)
Time Base Timer (TBT) Divider Output (DVO)
Time Base Timer Divider Output (DVO)
Watchdog Timer (WDT)
Watchdog Timer Configuration Watchdog Timer Control
Malfunction Detection Methods Using Watchdog Timer Watchdog Timer Enable Watchdog Timer Disable Watchdog Timer Interrupt (INTWDT). Watchdog Timer Reset
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5
16-Bit TimerCounter (TC1)
Configuration TimerCounter Control Function.
Timer mode. External Trigger Timer Mode Event Counter Mode Window Mode Pulse Width Measurement Mode. Programmable Pulse Generate (PPG) Output Mode
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6
16-Bit Timer (CTC)
Configuration
Control Function.
Timer mode with software start. Timer mode with external trigger start Event counter mode. Programmable Pulse Generate (PPG) output mode
9.3.1 9.3.2 9.3.3 9.3.4
8-Bit TimerCounter (TC3)
10.1 10.2 10.3 Configuration TimerCounter Control Function
10.3.1 Timer mode. Figure 10-3 10.3.3 Capture Mode
8-Bit TimerCounter (TC4)
11.1 11.2 11.3 Configuration TimerCounter Control Function
Timer Mode. Event Counter Mode Programmable Divider Output (PDO) Mode Pulse Width Modulation (PWM) Output Mode
11.3.1 11.3.2 11.3.3 11.3.4
8-Bit TimerCounter 5,6(TC5,
12.1 12.2 12.3 Configuration TimerCounter Control Function
8-Bit Timer Mode (TC5 8-Bit Event Counter Mode (TC5, 8-Bit Programmable Divider Output (PDO) Mode (TC5, 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 16-Bit Timer Mode (TC5 16-Bit Event Counter Mode (TC5 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5
12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8
Motor Control Circuit (PMD: Programmable motor driver)
13.1 13.2 13.3 Outline Motor Control Configuration Motor Control Circuit Position Detection Unit
Configuration position detection unit. Position Detection Circuit Register Functions. Outline Processing Position Detection Unit
13.4 13.5
13.3.1 13.3.2 13.3.3 13.4.1
Timer Unit
Configuration Timer Unit
Timer Circuit Register Functions Outline Processing Timer Unit
13.4.1.1 13.4.1.2
Three-phase Output Unit
13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.6.1
Configuration three-phase output unit.
Pulse width modulation circuit (PWM waveform generating unit) Commutation control circuit
13.5.1.1 13.5.1.2
13.6
Electrical Angle Timer Waveform Arithmetic Circuit
Electrical Angle Timer Waveform Arithmetic Circuit
Functions Electrical Angle Timer Waveform Arithmetic Circuit Registers List Related Control Registers
Register Functions Waveform Synthesis Circuit. Port output with UOC/VOC/WOC bits UPWM/VPWM/WPWM bits. Protective Circuit. Functions Protective Circuit Registers
13.6.1.1 13.6.1.2
Asynchronous Serial interface (UART1)
14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 Configuration Control Transfer Data Format Transfer Rate. Data Sampling Method STOP Length Parity Transmit/Receive Operation
Data Transmit Operation Data Receive Operation
14.8.1 14.8.2
Status Flag
Parity Error. Framing Error. Overrun Error Receive Data Buffer Full. Transmit Data Buffer Empty Transmit Flag
14.9.1 14.9.2 14.9.3 14.9.4 14.9.5 14.9.6
Asynchronous Serial interface (UART2)
15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 Configuration Control Transfer Data Format Transfer Rate. Data Sampling Method STOP Length Parity Transmit/Receive Operation
Data Transmit Operation Data Receive Operation
15.8.1 15.8.2
Status Flag
Parity Error. Framing Error. Overrun Error Receive Data Buffer Full. Transmit Data Buffer Empty Transmit Flag
15.9.1 15.9.2 15.9.3 15.9.4 15.9.5 15.9.6
Synchronous Serial Interface (SIO)
16.1 16.2 16.3
Configuration Control Serial clock
Clock source Shift edge.
Leading edge Trailing edge Internal clock External clock 16.3.1.1 16.3.1.2 16.3.2.1 16.3.2.2
16.3.1 16.3.2
16.4 16.5 16.6
Number bits transfer Number words transfer Transfer Mode
4-bit 8-bit transfer modes 4-bit 8-bit receive modes 8-bit transfer receive mode
16.6.1 16.6.2 16.6.3
10-bit Converter (ADC)
17.1 17.2 17.3 Configuration Register configuration Function.
Software Start Mode Repeat Mode Register Setting
17.4 17.5 17.6
17.3.1 17.3.2 17.3.3
STOP mode during Conversion. Analog Input Voltage Conversion Result Precautions about Converter
Analog input voltage range Analog input shared pins Noise Countermeasure
17.6.1 17.6.2 17.6.3
8-Bit High-speed (HPWM0 HPWM1)
18.1 18.2 18.3 Configuration Control Functional Description
Operation modes
8-bit mode 7-bit mode 6-bit mode 18.3.1.1 18.3.1.2 18.3.1.3
18.3.1
18.3.2
Setting output data.
Flash Memory
19.1 19.2 Flash Memory Control Command Sequence
Byte Program Sector Erase (4-kbyte Erase) Chip Erase (All Erase) Product Entry Product Exit Read Protect Flash Memory Command Sequence Execution Control (FLSCR<FLSMD>) 19.1.1
19.3 19.4
19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6
Toggle (D6) Access Flash Memory Area.
19.4.1 19.4.2
Flash Memory Control Serial PROM Mode. Flash Memory Control mode.
write flash memory executing user write control program area mode) write flash memory executing control program area loader mode within serial PROM mode)
19.4.1.1
19.4.2.1
Serial PROM Mode
20.1 20.2 20.3 Outline Memory Mapping Serial PROM Mode Setting
Serial PROM Mode Control Pins Function. Example Connection On-Board Writing. Activating Serial PROM Mode
20.4 20.5 20.6
20.3.1 20.3.2 20.3.3 20.3.4
Interface Specifications UART Operation Command Operation Mode.
Flash Memory Erasing Mode (Operating command: F0H) Flash Memory Writing Mode (Operation command: 30H) Loader Mode (Operation Command: 60H) Flash Memory Output Mode (Operation Command: 90H) Product Code Output Mode (Operation Command: C0H). Flash Memory Status Output Mode (Operation Command: C3H) Flash Memory Read Protection Setting Mode (Operation Command: FAH)
20.7 20.8
20.6.1 20.6.2 20.6.3 20.6.4 20.6.5 20.6.6 20.6.7
Error Code Checksum (SUM)
Calculation Method Calculation data
20.9 Intel Format (Binary) 20.10 Passwords
20.10.1 20.10.2 20.10.3 Password String. Handling Password Error Password Management during Program Development
20.8.1 20.8.2
20.11 20.12 20.13 20.14 20.15 20.16
Product Code Flash Memory Status Code Specifying Erasure Area Port Input Control Register Flowchart UART Timing
Input/Output Circuitry
21.1 21.2 Control pins Input/output ports.
Electrical Characteristics
22.1 22.2 Absolute Maximum Ratings Operating Conditions
mode (Flash Programming erasing) mode (Except Flash Programming erasing) Serial PROM mode
22.3
22.2.1 22.2.2 22.2.3
Characteristics.
22.4 22.5 22.6 22.7 22.8
Characteristics Characteristics Flash Characteristics Recommended Oscillating Conditions. Handling Precaution
Package Dimensions
This technical document that describes operating functions electrical specifications 8-bit microcontroller series TLCS-870/X (LSI).
viii
TMP88FW44FG
CMOS 8-Bit Microcontroller
TMP88FW44FG
Product TMP88FW44FG (FLASH) 122880 bytes 4224 bytes Package QFP100-P-1420-0.65A
Features
8-bit single chip microcomputer TLCS-870/X series Instruction execution time 0.20 MHz) types basic instructions interrupt sources (External Internal Input Output ports pins) Large current output: 24pins (Typ. 20mA), direct drive Prescaler Time base timer Divider output function (DVO) Watchdog Timer Select "internal reset request" "interrupt request". 16-bit timer counter: Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 16-bit timer/counter(CTC): CTC:Timer,event counter (Programmable Pulse) output 8-bit timer counter Timer, Event counter, Capture modes 8-bit timer counter
This product uses Super Flash technology under licence Silicon Storage Technology, Inc. Super Flash registered trademark Silicon Storage Technology, Inc.
060116EBP
information contained herein subject change without notice. 021023_D TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunctionor failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. 021023_B products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. 060106_Q information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights TOSHIBA others. 021023_C products described this document subject foreign exchange foreign trade laws. 021023_E discussion reliability microcontrollers predicted, please refer Section chapter entitled Quality Reliability Assurance/Handling Precautions. 030619_S
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Features
TMP88FW44FG
Timer, Event counter, Pulse width modulation (PWM) output, Programmable divider output (PDO) modes 8-bit timer counter Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes Programmable motor driver (PMD) Sine wave drive circuit (built-in sine wave data-table RAM) Rotor position detect function Motor contro timer capture function Overload protective function Auto commutation auto position detection start function 8-bit UART 8-bit SIO: 10-bit successive approximation type converter Analog input: 8-bit High-speed (HPWM0 HPWM1) Clock oscillation circuit power consumption operation modes) STOP mode: Oscillation stops. (Battery/Capacitor back-up.) IDLE mode: stops. Only peripherals operate using high frequency clock. Release interruputs (CPU restarts). Operation voltage:
20MHz
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TMP88FW44FG
Assignment
(TXD3) (RXD3) AVSS AVDD
XOUT TEST (TC3) (PWM4/PDO4/TC4/INT4)
Figure Assignment
(STOP/INT5) (Z1) (Y1) (X1) (W1) (V1) (U1) (EMG1) (CL1) (PDW1) (PDV1) (PDU1) (SCK) (BOOT/SI/RXD1) (SO/TXD1) (PPG2) (CTC)
RESET
(RXD2/TC6) TXD2/PDO6/PWM6/PPG6) (HPWM0) (HPWM1) (INT0) (INT1) (TC1/INT2) (TC5/DVO) (PWM5/PDO5/PPG1) (PDU2) (PDV2) (PDW2) (CL2) (EMG2) (U2) (V2) (W2) (X2) (Y2) (Z2)
VAREF (AIN15) (AIN14) (AIN13) (AIN12) (AIN11) (AIN10) (AIN9) (AIN8) (AIN7/DBOUT1) (AIN6) (AIN5) (AIN4) (AIN3) (AIN2) (AIN1) (AIN0)
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Block Diagram
TMP88FW44FG
Block Diagram
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TMP88FW44FG
Figure Block Diagram
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Names Functions
TMP88FW44FG
Names Functions
TMP88FW44FG mode, parallel PROM mode, serial PROM mode. Table shows functions mode. serial PROM mode explained later separate chapter. Table Names Functions(1/4)
Name
HPWM1
Number
Input/Output
Functions PORT03 High-spped PWM1 output PORT02 High-spped PWM0 output PORT01 PDO6/PWM6/PPG6 output UART data output PORT00 input UART data input PORT17 control input PORT16 control input PORT15 control input PORT14 PPG1 output PWM5/PDO5 output PORT13 Divider Output input PORT12 External interrupt input input PORT11 External interrupt input PORT10 External interrupt input PORT22 External interrupt input input PWM4/PDO4 output PORT21 input PORT20 External interrupt input STOP mode release signal input PORT37 over load protection input1 PORT36 emergency stop input1 PORT35 control output
HPWM0
PDO6/PWM6/PPG6
TXD2 RXD2 PDW2 PDV2 PDU2
PPG1 PWM5/PDO5
INT2 INT1
INT0
INT4
PWM4/PDO4
INT5 STOP
EMG1
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TMP88FW44FG
Table Names Functions(2/4)
Name
PPG2
Number
Input/Output PORT34 control output PORT33 control output PORT32 control output PORT31 control output PORT30 control output PORT47 input PORT46 PORT45 UART data output Serial Data Output
Functions
TXD1 RXD1 BOOT
PORT44 UART data input Serial Data Input Serial PROM mode control input PORT43 Serial Clock PORT42 control input PORT41 control input PORT40 control input PORT57 control output PORT56 control output PORT55 control output PORT54 control output PORT53 control output PORT52 control output PORT51 emergency stop input2 PORT50 over load protection input2 PORT67 Analog Input7 debug output1
PDU1 PDV1 PDW1
EMG2
AIN7 DBOUT1
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Names Functions
TMP88FW44FG
Table Names Functions(3/4)
Name AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 TXD3 RXD3 Number Input/Output PORT66 Analog Input6 PORT65 Analog Input5 PORT64 Analog Input4 PORT63 Analog Input3 PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 PORT77 Analog Input15 PORT76 Analog Input14 PORT75 Analog Input13 PORT74 Analog Input12 PORT73 Analog Input11 PORT72 Analog Input10 PORT71 Analog Input9 PORT70 Analog Input8 PORT87 PORT86 PORT85 PORT84 PORT83 PORT82 PORT81 UART data output PORT80 UART data input PORT97 PORT96 PORT95 PORT94 Functions
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TMP88FW44FG
Table Names Functions(4/4)
Name XOUT
RESET
Number
Input/Output PORT93 PORT92 PORT91 PORT90 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTC3 PORTC2 PORTC1 PORTC0
Functions
Resonator connecting pins high-frequency clock Resonator connecting pins high-frequency clock Reset signal Test out-going test Serial PROM mode control pin. Usually level. high level when Serial PROM mode starts. Analog Base Voltage Input Conversion Analog Power Supply Analog Power Supply 0(GND)
TEST
VAREF AVDD AVSS
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Names Functions
TMP88FW44FG
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TMP88FW44FG
Functional Description
Functions Core
core consists mainly CPU, system clock control circuit, interrupt control circuit. This chapter describes core, program memory, data memory, reset circuit TMP88FW44FG.
2.1.1
Memory Address
memory TMP88FW44FG consists four blocks: ROM, RAM, (Special Function Registers), DBR/EBR (Data Buffer Registers), which mapped into 1-Mbyte address space. generalpurpose registers consist banks, which mapped into address space. Figure shows memory address TMP88FW44FG.
(128 bytes) bytes)
010BFH
00000H 0003FH 00040H 000BFH 000C0H
bytes bytes
4096 bytes
Special Function Register General-purpose Register Bank registers banks) Random-Access Memory
DBR/EBR
01F70H
bytes
01FFFH 04000H
Data Buffer Register (peripheral hardware control register status register)
122624 bytes
Program Memory
120K Kbytes)
21EFFH
FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH
bytes bytes bytes
Interrupt Vector Table Vector Table Vector Call Instructions Interrupt Vector Table
SFR: Special Function Registers Input/output port Peripheral hardware control register Peripheral hardware status register RAM: Random Access Memory System control register Data memory Interrupt control register Stack Program status word General-purpose register bank ROM: Read-Only Memory Program memory Vector Table
DBR: Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register EBR: Extra Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register
Figure Memory address
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Functional Description
Functions Core TMP88FW44FG
2.1.2
Program Memory (ROM)
TMP88FW44FG contains 120Kbytes program memory (Flash) located addresses 04000H 21EFFH addresses FFF00H FFFFFH.
2.1.3
Data Memory (RAM)
TMP88FW44FG contains 4Kbytes +128bytes RAM. first 128bytes location (00040H 000BFH) internal shared with general-purpose register bank. content data memory indeterminate power-on, sure initialize initialize routine. Example :Clearing internal TMP88FW44FG (clear addresses except bank
SRAMCLR: 0048H 1077H (HL+), SRAMCLR start address initialization data (00H) byte counts (-1)
Note:Because general-purpose registers exist RAM, never clear current bank address RAM. above example, cleared except bank
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TMP88FW44FG
2.1.4
System Clock Control Circuit
System Clock Control Circuit consists clock generator, timing generator, standby control circuit.
Timing generator control register Clock generator High-frequency clock oscillator circuit XOUT Timing generator Standby control circuit 00038H SYSCR1 System clocks 00039H SYSCR2 TBTCR 00036H
System control register
Figure System Clock Control Circuit
2.1.4.1 Clock Generator
Clock Generator generates fundamental clock which serves reference system clocks supplied core peripheral hardware units. high-frequency clock (frequency obtained easily connecting resonator XOUT pins. clock generated external oscillator also used. this case, enter external clock from leave XOUT open. TMP88FW44FG does support network that produces time constant.
High-frequency Clock XOUT XOUT
(Open)
Using crystal ceramic resonator
Using external oscillator
Figure Example Connecting Resonator
Adjusting oscillation frequency
Note: Although hardware functions provided that allow fundamental clock monitored directly from outside, oscillation frequency adjusted forwarding pulse fixed frequency (e.g., clock output) port monitoring program while interrupts watchdog timer disabled. systems that require adjusting oscillation frequency, adjustment program must created beforehand.
2.1.4.2
Timing Generator
Timing Generator generates various system clocks from fundamental clock that supplied core peripheral hardware units. Timing Generator following functions: Page
Functional Description
Functions Core TMP88FW44FG
Generate divider output (DVO) pulse Generate source clock time base timer Generate source clock watchdog timer Generate internal source clock timer counter Generate warm-up clock when exiting STOP mode Configuration Timing Generator Timing Generator 3-stage prescaler, 21-stage dividers, machine cycle counter. When reset when entering/exiting STOP mode, prescaler dividers cleared
Machine cycle counter
DV1CK
Prescaler
Selector
Divider
Divider
10111213141516171819 2021
Standby control circuit Watchdog timer
Timer counter
Time base timer
Divider Output etc.
Figure Configuration Timing Generator
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TMP88FW44FG
Divider Control Register
CGCR (0030H) DV1CK (Initial value: 000* *000)
DV1CK
Selects input clock first divider stage
fc/4 fc/8
Note high-frequency clock [Hz], Don't care Note CGCR Register bits show indeterminate value when read. Note sure write CGCR Register bits
Timing Generator Control Register
TBTCR (0036H) DVOEN DVOCK TBTEN TBTCK (Initial value: 0000 0000)
Note Don't care Note sure write TBTCR Register
Machine cycle Instruction execution internal hardware operations synchronized system clocks. minimum unit instruction execution referred "mgmachine cycle". TLCS870/X series types instructions, from 1-cycle instructions which executed machine cycle 15-cycle instructions that require maximum machine cycles. machine cycle consists four states S3), with each state comprised main system clock cycle.
1/fc Main system clock
States
Machine cycle (0.20 MHz)
Figure Machine Cycles
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Functional Description
Functions Core TMP88FW44FG
2.1.4.3
Standby Control Circuit
Standby Control Circuit starts/stops high-frequency clock oscillator circuit selects main system clock. System Control Registers (SYSCR1, SYSCR2) used control operation modes this circuit. Figure shows operation mode transition diagram, followed description System Control Registers. Single clock mode Only high-frequency clock oscillator circuit used. Because main system clock generated from high-frequency clock, machine cycle time single clock mode 4/fc [s]. NORMAL mode this mode, core peripheral hardware units operated with high-frequency clock. TMP88FW44FG enters this NORMAL mode after reset. IDLE mode this mode, watchdog timer turned while peripheral hardware units operated with high-frequency clock. IDLE mode entered into using System Control Register device placed this mode back into NORMAL mode interrupt from peripheral hardware external interrupt. When (interrupt master enable flag) (interrupt enabled), device returns normal operation after interrupt been serviced. When (interrupt disabled), device restarts execution beginning with instruction next that placed IDLE mode. STOP mode entire system operation including oscillator circuit halted, retaining internal state immediately before being stopped, with minimal amount power consumed. STOP mode entered into using System Control Register exited STOP input (level edge selectable). After elapse warm-up time, device restarts execution beginning with instruction next that placed STOP mode. Table Single Clock Mode
Oscillator Circuit Operation Mode High Frequency Frequency Core Peripheral Circuit Reset 4/fc Operate Stop STOP Stop Stop Machine Cycle Time
RESET Single Clock NORMAL IDLE Oscillate
Reset Operate
RESET Reset deasserted Instruction NORMAL mode Interrupt Input releasing mode STOP mode
Instruction IDLE mode
Figure Operation Mode Transition Diagram
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TMP88FW44FG
System Control Register
SYSCR1 (0038H) STOP RELM OUTEN (Initial value: 0000 00**)
STOP
Place device STOP mode Select method which device released from STOP mode Select operation mode after exiting STOP mode Select port output state during STOP mode
Keep core peripheral hardware operating Stop core peripheral hardware (placed STOP mode) Released rising edge STOP input Released high level STOP input Returns NORMAL mode Reserved High-impedance state Hold output When Returning NORMAL Mode DV1CK DV1CK 217/fc 217/fc 215/fc Reserved
RELM
REOUTEN
Unit warm-up time when exiting STOP mode
216/fc 216/fc 214/fc Reserved
Note When entering from NORMAL mode into STOP mode, always sure SYSCR1<RETM> Note When device released from STOP mode RESET input, always returns NORMAL mode regardless SYSCR1<RETM> set. Note High-frequency clock [Hz], Don't care Note values SYSCR1 Register bits indeterminate when read. Note When placed device STOP mode, make sure SYSCR1<OUTEN>. Note Releasing device from STOP mode causes STOP automatically cleared "0". Note Select appropriate value warm-up time according characteristic resonator used.
System Control Register
SYSCR2 (0039H) SYSCK IDLE (Initial value: 1000 ****)
SYSCK IDLE
Control high-frequency oscillator Select (write)/monitor (read) system clock Place device IDLE mode
Stop oscillation Continue start oscillating High-frequency clock (NORMAL/IDLE) Reserved Keep operating Stop (IDLE mode entered)
Operation Mode after Releasing STOP Mode NORMAL mode operation
SYSCK
Note When exiting STOP mode, SYSCR2<XEN SYSCK> automatically rewritten according SYSCR1<RETM>. Note When SYSCR2<XEN>is cleared device reset. Note WDT: Watchdog Timer, Don't care Note sure write SYSCR2 Register bit6. Note values SYSCR2 Register bits indeterminate when read. Note Change operation mode after disabling external interrupts. interrupts enabled after changing operation mode, clear interrupt latches appropriate advance.
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Functional Description
Functions Core TMP88FW44FG
2.1.4.4
Controlling Operation Modes
STOP mode STOP mode controlled System Control Register (SYSCR1) STOP input. STOP shared with port INT5 (external interrupt input STOP mode entered into setting STOP (SYSCR1 Register During STOP mode, device retains following state. Stop oscillation, thereby stopping operation internal circuits. data memory, register, program status word, port output latch hold state which they were immediately before entering STOP mode. Clear prescaler divider timing generator program counter holds instruction address instructions ahead that placed device STOP mode (e.g., "SET (SYSCR1).7"). device released from STOP mode active level edge STOP input selected SYSCR1<RELM>.
Note: Before entering STOP mode, sure disable interrupts. This because signal external interrupt changes state during STOP (from entering STOP mode till completion warm-up) interrupt latch that device accept interrupt immediately after exiting STOP mode. Also, when reenabling interrupts after exiting STOP mode, sure clear unnecessary interrupt latches beforehand.
Released level (when RELM device released from STOP mode high level STOP input. instruction place device STOP mode ignored when executed while STOP input level high, device immediately goes release sequence (warm-up) without entering STOP mode. Therefore, before STOP mode entered while RELM STOP input must verified program. There following methods this verification. Testing port status INT5 interrupt (interrupt generated falling edge INT5 input) Example :Entering STOP mode from NORMAL mode testing port
SSTOPH TEST (SYSCR1) (SYSCR1), 01010000B (P2DR) SSTOPH Place device STOP mode Select released from STOP mode level Wait until STOP input goes
Example :Entering STOP mode from NORMAL mode INT5 interrupt
PINT5 TEST (P2DR) enter STOP mode port input level high, eliminate noise enter STOP mode port input level high, eliminate noise Select released from STOP mode level (SYSCR1) Place device STOP mode
SINT5 RETI
SINT5 (SYSCR1), 01010000B
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TMP88FW44FG
STOP
XOUT NORMAL operation STOP mode Detect STOP input program before entering STOP mode Warm-up NORMAL operation
Released from STOP mode hardware Always released high level STOP input
Figure Released from STOP Mode Level
Note Once warm-up starts, device does return STOP mode even when STOP input pulled again. Note RELM changed (level mode) after being (edge mode), STOP mode remains unchanged unless rising edge STOP input detected.
Released edge (when RELM device released from STOP mode rising edge STOP input. This method used applications where relatively short time program processing repeated certain fixed intervals. Apply fixed-period signal (e.g., clock from low-power oscillating source) STOP pin. When RELM (edge mode), device placed STOP mode even when STOP input level high. Example :Entering STOP mode from NORMAL mode
(SYSCR1) 10010000B released edge when entering STOP mode
STOP
XOUT NORMAL operation Placed into STOP mode program STOP mode Warm-up NORMAL operation STOP mode
Released from STOP mode hardware rising edge STOP input.
Figure Released from STOP Mode Edge
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Functional Description
Functions Core TMP88FW44FG
device released from STOP mode following sequence described below. Only high-frequency oscillator oscillating. warm-up time inserted order allow clock oscillation stabilize. During warm-up, internal circuits remain idle. warm-up time selected from three choices according oscillator characteristics using SYSCR1<WUT>. After elapse warm-up time, device restarts normal operation beginning with instruction next that placed STOP mode. this time, prescaler divider timing generator start from zero-cleared state. Table Warm-up Time (Example: MHz)
Warm-up Time [ms] When Returning NORMAL Mode DV1CK 9.831 3.277 0.819 Reserved DV1CK 19.662 6.554 1.638 Reserved
Note: Because warm-up time obtained from fundamental clock dividing oscillation frequency fluctuates while exiting STOP mode, warm-up time becomes have some error. Therefore, warm-up time must handled approximate value.
device also released from STOP mode pulling RESET input low, which case device immediately reset normally reset RESET. After reset, device starts operating from NORMAL mode.
Note: When exiting STOP mode while device retained voltage, following caution required. Before exiting STOP mode, power supply voltage must raised operating voltage. this time, RESET level also high rises along with power supply voltage. device time-constant circuit added external chip, voltage RESET input does rise fast power supply voltage. Therefore, voltage level RESET input below RESET pin's noninverted, high-level input voltage (hysteresis input), device reset.
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Oscillator circuit
Oscillation
Stop
Main system clock Stop
Program counter (SYSCR1).
Instruction execution
Divider
Entering STOP mode (Example: Entered into (SYSCR1). instruction placed address
Figure Entering Exiting STOP Mode (when DV1CK
Instruction address Instruction address Exiting STOP mode
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Warm-up
STOP input
Oscillator circuit
Stop
Oscillation
Main system clock
Program counter
Instruction execution
Stop
Instruction address
Divider
Count
TMP88FW44FG
Functional Description
Functions Core TMP88FW44FG
IDLE mode IDLE mode controlled System Control Register (SYSCR2) maskable interrupt. During IDLE mode, device retains following state. watchdog timer stop operating. peripheral hardware continues operating. data memory, register, program status word, port output latch hold state which they were immediately before entering IDLE mode. program counter holds instruction address instructions ahead that placed device IDLE mode.
Example :Placing device IDLE mode
(SYSCR2)
Place device IDLE mode instruction)
Stop
Reset input
Reset
Interrupt request
(Released interrupt)
(Released normally)
Interrupt handling
Execute instruction next that placed device IDLE mode
Figure 2-10 IDLE Mode
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TMP88FW44FG
device released from IDLE mode normally interrupt selected with interrupt master enable flag (IMF). Released normally (when device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), restarts execution beginning with instruction next that placed IDLE mode. interrupt latch (IL) interrupt source used exit IDLE mode normally needs cleared using load instruction. Released interrupt (when device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), enters interrupt handling. After interrupt handling, device returns instruction next that placed IDLE mode. device also released from IDLE mode pulling RESET input low, which case device immediately reset normally reset RESET. After reset, device starts operating from NORMAL mode.
Note: watchdog timer interrupt occurs immediately before entering IDLE mode, device processes watchdog timer interrupt without entering IDLE mode.
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Main system clock
Functional Description
Functions Core
Interrupt request IDLE
Program counter (SYSCR2).
Instruction execution Operating
Watchdog timer
Entering IDLE mode (Example: Entered into instruction placed address
Main system clock
Interrupt request
Program counter Instruction address
Figure 2-11 Entering Exiting IDLE Mode
Operating Interrupt accepted Operating
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Instruction execution
IDLE
Watchdog timer
IDLE
Released normally
Main system clock
Interrupt request
Program counter
Instruction execution
IDLE
Watchdog timer
IDLE
Released interrupt
TMP88FW44FG
Exiting IDLE mode
TMP88FW44FG
2.1.5
Reset Circuit
TMP88FW44FG four ways generate reset: external reset input, address trap reset, watchdog timer reset, system clock reset. Table shows internal hardware initialized reset operation. power-on time, internal cause reset circuits (watchdog timer reset, address trap reset, system clock reset) initialized. Table Internal Hardware Initialization Reset Operation
Internal Hardware Program Counter (PC) Stack Pointer (SP) General-purpose Registers Register Bank Selector (RBS) Jump Status Flag (JF) Zero Flag (ZF) Carry Flag (CF) Half Carry Flag (HF) Sign Flag (SF) Overflow Flag (VF) Interrupt Master Enable Flag (IMF) Interrupt Individual Enable Flag (EF) Interrupt Latch (IL) Interrupt Nesting Flag (INF) Initial Value (FFFFEH FFFFCH) initialized initialized Watchdog timer initialized initialized initialized Output latch input/output port initialized initialized Control register description each control register. initialized description each input/output port. Enable Prescaler divider timing generator Internal Hardware Initial Value
2.1.5.1
External Reset Input
RESET hysteresis input with pull-up resistor included. holding RESET least three machine cycles (12/fc [s]) more while power supply voltage within rated operating voltage range oscillator oscillating stably, device reset internal state initialized. When RESET input released back high, device freed from reset starts executing program beginning with vector address stored addresses FFFFCH FFFFEH.
RESET
Reset input
Figure 2-12 Reset Circuit
2.1.5.2 Adress Trap Reset
should start looping reasons noise, etc. attempts fetch instructions from internal RAM,SFR DBR/EBR area, device generats internal reset. addess trap permission/prohibition address trap reset control register (ATAS,ATKEY). address trap permited initially internal reset generated fetching from internal RAM,SFR DBR/EBR area. address trap prohibited, instructions internal area executed. Page
Functional Description
Functions Core TMP88FW44FG
Address Trap Control Register
ATAS (1F94H) ATAS (initial value: **** ***0)
ATAS
Select address trap permission prohibition
Permit address trap Prohibit address trap available after setting control code ATKEY register)
Write only
Address Trap Control Code Register
ATKEY (1F95H) (initial value: **** ****)
ATKEY
Write control code prohibit address trap
D2H: Address trap prohibition code Others: Ineffective
Write only
Note: Read-modify-write instructions, such manipulation, cannot access ATAS ATKEY register because these register write only. Note development tools, address trap cannot prohibited internal RAM,SFR DBR/EBR area with address trap control registers. When using development tools, even address trap permission/prohibition setting changed user's program, this change ineffective. execute instructions from area, development tools must accordingly. Note While instruction address immediately before address trap area executing, program counter incremented point next address address trap area; address trap therefore taken immediately.
Development tool setting prohibit address trap: Modify iram (mapping attribute) area (00040H 000BFH) memory window. 000C0H "address trap prohibition area" eram (mapping attribute) area. Load user program Execute address trap prohibition code user's program
2.1.5.3
Watchdog Timer Reset
Refer Section "Watchdog Timer."
2.1.5.4
System Clock Reset
When SYSCR2<XEN> cleared when SYSCR2<XEN> cleared while SYSCR2<SYSCK> system clock turned off, causing become locked prevent this problem, upon detecting SYSCR2<XEN> SYSCR2<XEN> SYSCR2<SYSCK> SYSCR2<SYSCK> device automatically generates internal reset signal system clock continue oscillating.
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TMP88FW44FG
Interrupt Control Circuit
TMP88FW44FG total interrupt sources excluding reset. Interrupts nested with priorities. internal interrupt sources pseudo nonmaskable while rest maskable. Interrupt sources provided with interrupt latches (IL), which hold interrupt requests, independent vectors. interrupt latch generation interrupt request which requests accept interrupts. Interrupts enabled disabled software using interrupt master enable flag (IMF) interrupt enable flag (EF). more than interrupts generated simultaneously, interrupts accepted order which dominated hardware. However, there prioritized interrupt factors among non-maskable interrupts.
Interrupt Latch IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 Vector Address FFFFC FFFF8 FFFF4 FFFF0 FFFEC FFFE8 FFFE4 FFFE0 FFFDC FFFD8 FFFD4 FFFD0 FFFCC FFFC8 FFFC4 FFFC0 FFFBC FFFB8 FFFB4 FFFB0 FFFAC FFFA8 FFFA4 FFFA0 FFF9C FFF98 FFF94 FFF90 FFF8C FFF88
Interrupt Factors Internal/External Internal Internal External (Reset) INTSWI (Software interrupt) INTWDT (Watchdog timer interrupt)
INT0
Enable Condition Nonmaskable Pseudo nonmaskable Pseudo nonmaskable INT0EN EF10 EF11 EF12 EF13 EF14 EF15 EF16 EF17 EF18 EF19 EF20 EF21 EF22 EF23 EF24 EF25 EF26 EF27 EF28 EF29
Priority High
(External interrupt
Reserved External Internal INT1 (External interrupt INTTBT (TBT interrupt) Reserved Internal Internal Internal Internal Internal Internal INTEMG1 (ch1 Error detect interrupt) INTEMG2 (ch2 Error detect interrupt) INTCLM1 (ch1 Overload protection interrupt) INTCLM2 (ch2 Overload protection interrupt) INTTMR31 (ch1 Timer interrupt) INTTMR32 (ch2 Timer interrupt) Reserved External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal External
INT5 (External interrupt
INTPDC1 (ch1 Posision detect interrupt) INTPDC2 (ch2 Posision detect interrupt) INTPWM1 (ch1 Waveform generater interrupt) INTPWM2 (ch2 Waveform generater interrupt) INTEDT1 (ch1 Erectric angle Timer interrupt) INTEDT2 (ch2 Erectric angle Timer interrupt) INTTMR11 (ch1 Timer1 interrupt) INTTMR12 (ch2 Timer1 interrupt) INTTMR21 (ch1 Timer2 interrupt) INTTMR22 (ch2 Timer2 interrupt) INTTC1 (TC1 interrupt) INTCTC1 (CTC interrupt) INTTC6 (TC6 8bit/16bit interrupt) INT2 (External interrupt
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Interrupt Control Circuit
Interrupt latches (IL39 IL2) TMP88FW44FG
Interrupt Factors Internal External Internal Internal Internal Internal Internal Internal Internal Internal INTRXD2 (ch2 UART receive interrupt) INT4 (External interrupt INTRXD (ch1 UART receive interrupt) INTTXD (ch1 UART transmit interrupt) INTSIO (SIO interrupt) INTTC3 (TC3 interrupt) INTTC4 (TC4 interrupt) INTTC5 (TC5 interrupt) INTADC (A/D converter interrupt) INTTXD2 (ch2 UART transmit interrupt)
Enable Condition EF30 EF31 EF32 EF33 EF34 EF35= EF36 EF37 EF38 EF39
Interrupt Latch IL30 IL31 IL32 IL33 IL34 IL35 IL36 IL37 IL38 IL39
Vector Address FFF84 FFF80 FFF3C FFF38 FFF34 FFF30 FFF2C FFF28 FFF24 FFF20
Priority
Note watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> "Reset request" after reset released). described section "Watchdog Timer" details.
Interrupt latches (IL39 IL2)
interrupt latch provided each interrupt source, except software interrupt executed undefined instruction interrupt. When interrupt request generated, latch "1", requested accept interrupt interrupt enabled. interrupt latch cleared immediately after accepting interrupt. interrupt latches initialized during reset. interrupt latches located address 003CH, 003DH, 002EH, 002FH 002BH area. Each latch cleared individually instruction. However, should cleared software. clearing interrupt latch, load instruction should used then should "1". read-modifywrite instructions such manipulation operation instructions used, interrupt request would cleared inadequately interrupt requested while such instructions executed. Since interrupt latches read, status interrupt requests monitored software. interrupt latches instruction.
Note: main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
Example :Clears interrupt latches
(ILL), 1110100000111111B (ILH), 1110100000111111B (ILE), 1110100000111111B (ILD), 1110100000111111B (ILC), 1110100000111111B IL15 IL16 IL23 IL24 IL31 IL32 IL39
Example :Reads interrupt latches
(ILL) (ILE) (ILC) (ILH), (ILL) (ILD), (ILE) (ILC)
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TMP88FW44FG
Example :Tests interrupt latches
TEST (ILL). SSET then jump
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Interrupt Control Circuit
Interrupt enable register (EIR) TMP88FW44FG
Interrupt enable register (EIR)
interrupt enable register (EIR) enables disables acceptance interrupts, except pseudo nonmaskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt watchdog interrupt). Pseudo non-maskable interrupt accepted regardless contents EIR. consists interrupt master enable flag (IMF) individual interrupt enable flags (EF). These registers located address 003AH, 003BH, 002CH, 002DH 002AH area, they read written instructions (Including read-modify-write instructions such manipulation operation instructions).
3.2.1
Interrupt master enable flag (IMF)
interrupt enable register (IMF) enables disables acceptance whole maskable interrupt. While "0", maskable interrupts accepted regardless status each individual interrupt enable flag (EF). setting "1", interrupt becomes acceptable individuals enabled. When interrupt accepted, cleared after latest status stacked. Thus maskable interrupts which follow disabled temporarily. flag maskable interrupt return instruction [RETI] after executing interrupt service program routine, accept interrupt again. latest interrupt request generated already, available immediately after [RETI] instruction executed. pseudo non-maskable interrupt, non-maskable return instruction [RETN] adopted. this case, flag only when performs pseudo non-maskable interrupt service routine interrupt acceptable status (IMF=1). However, pseudo non-maskable interrupt service routine, maintains status (IMF="0"). located bit0 EIRL (Address: 003AH SFR), read written instruction. normally cleared [EI] [DI] instruction respectively. During reset, initialized "0".
3.2.2
Individual interrupt enable flags (EF39 EF3)
Each these flags enables disables acceptance maskable interrupt. Setting corresponding individual interrupt enable flag enables acceptance interrupt, setting disables acceptance. During reset, individual interrupt enable flags (EF39 EF3) initialized maskable interrupts accepted until they "1".
Note:In main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
Example :Enables interrupts individually sets
(EIRL), (EIRL), (EIRH), (EIRD), EF12 EF24
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TMP88FW44FG
Interrupt Latches
(Initial value: 0*000000 *00*0000) ILH,ILL (003DH, 003CH) IL15 IL13 IL12 IL11 IL10
(003DH)
(003CH)
(Initial value: 00000000 00000000) ILD,ILE (002FH, 002EH) IL31 IL30 IL29 IL28 IL27 IL26 IL25 IL24 IL23 IL22 IL21 IL20 IL19 IL18 IL17 IL16
(002FH)
(002EH)
(Initial value: 00000000) (002BH) IL39 IL38 IL37 IL36 IL35 IL34 IL33 IL32
(002BH)
Read IL39 Interrupt latches interrupt request Interrupt request interrupt service interrupt service level interrupt service more than level interrupt service more than level
Write Clears interrupt request (Note1) (Unable interrupt latch) Reserved Clear nesting counter Count-down step nesting counter (Note2) Reserved
Interrupt Nesting Flag
Note cannot alone cleard. Note Unable detect under-flow counter. Note nesting counter initially, performs count-up interrupt acceptance count-down executing interrupt return instruction. Note main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1". Note clear with read-modify-write instructions such operations.
Interrupt Enable Registers
(Initial value: 0*000000 *00*0**0) EIRH,EIRL (003BH, 003AH) EF15 EF13 EF12 EF11 EF10
EIRH (003BH)
EIRL (003AH)
(Initial value: 00000000 00000000) EIRD,EIRE (002DH, 002CH) EF31 EF30 EF29 EF28 EF27 EF26 EF25 EF24 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16
EIRD (002DH)
EIRE (002CH)
(Initial value: 00000000) EIRE (002AH) EF39 EF38 EF37 EF36 EF35 EF34 EF33 EF32
EIRE (002AH)
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Interrupt Control Circuit
Interrupt enable register (EIR) TMP88FW44FG
EF39
Individual-interrupt enable flag (Specified each bit) Interrupt master enable flag
Disables acceptance each maskable interrupt. Enables acceptance each maskable interrupt. Disables acceptance maskable interrupts Enables acceptance maskable interrupts
Note interrupt enable flag (EF39 EF3) same time. Note main program, before manipulating interrupt enable flag (EF) interrupt latch (IL), sure clear (Disable interrupt instruction). Then newly again required after operating (Enable interrupt instruction) interrupt service routine, because becomes automatically, clearing need execute normally interrupt service routine. However, using multiple interrupt interrupt service routine, manipulating should executed before setting IMF="1".
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TMP88FW44FG
Interrupt Sequence
interrupt request, which raised interrupt latch, held, until interrupt accepted interrupt latch cleared resetting instruction. Interrupt acceptance sequence requires machine cycles (2.4 MHz) after completion current instruction. interrupt service task terminates upon execution interrupt return instruction [RETI] (for maskable interrupts) [RETN] (for non-maskable interrupts). Figure shows timing chart interrupt acceptance processing.
3.3.1
Interrupt acceptance processing packaged follows.
interrupt master enable flag (IMF) cleared order disable acceptance following interrupt. interrupt latch (IL) interrupt source accepted cleared "0". contents program counter (PC) program status word, including interrupt master enable flag (IMF), saved (Pushed) stack sequence PSWH, PSWL, PCE, PCH, PCL. Meanwhile, stack pointer (SP) decremented entry address (Interrupt vector) corresponding interrupt service program, loaded vector table, transferred program counter. Read control code from vector table, MSB(4bit) register bank selecter (RBS). Count interrupt nesting counter. instruction stored entry address interrupt service program executed.
Note:When contents saved stack, contents also saved.
Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) Execute instruction Execute instruction
Execute instruction
Interrupt acceptance
Execute RETI instruction
Note Return address, Entry address, Address which RETI instruction stored Note condition that interrupt enabled, takes 62/fc maximum interrupt latch first machine cycle cycle instruction) start interrupt acceptance processing since interrupt latch set.
Figure Timing Chart Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address INTTBT entry address interrupt service program
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Interrupt Control Circuit
Interrupt Sequence TMP88FW44FG
Vector table address
Entry address
FFFE4H FFFE5H FFFE6H FFFE7H
control code Vector
12345H 12346H 12347H 12348H Interrupt service program
Figure Vector table address,Entry address
maskable interrupt accepted until even maskable interrupt higher than level current servicing interrupt requested. order utilize nested interrupt service, interrupt service program. this case, acceptable interrupt sources selectively enabled individual interrupt enable flags. don't read-modify-write instruction EIRL(0003AH) pseudo non-maskable interrupt service task. avoid overloaded nesting, clear individual interrupt enable flag whose interrupt currently serviced, before setting "1". non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise status cannot recovered non-maskable interrupt would simply nested.
3.3.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, program counter (PC) program status word (PSW, includes IMF) automatically saved stack, accumulator others not. These registers saved software necessary. When multiple interrupt services nested, also necessary avoid using same data memory area saving registers. following four methods used save/restore general-purpose registers.
3.3.2.1
Using Automatic register bank switcing
switching non-use register bank, restore general-purpose register hige speed. Usually bank register assigned main task bank register each interrupt service task. make data memory efficiency, common bank assigned non-multiple intrrupt factor. return back main-flow executing interrupt return instructions ([RETI]/[RETN]) from current interrupt register bank automatically. Thus, need restore program.
Example :Register bank switching
PINTxx: (interrupt processing) RETI VINTxx: PINTxx PINTxx vector address setting setting PINTxx Begin interrupt routine interrupt
3.3.2.2
Using register bank switching
switching non-use register bank, restore general-purpose register hige speed. Usually bank register assigned main task bank register each interrupt service task. Page
TMP88FW44FG
Example :Register bank switching
PINTxx: RBS, Begin interrupt routine (interrupt processing) RETI VINTxx: PINTxx PINTxx vector address setting setting PINTxx interrupt restore interrupt return
3.3.2.3
Using PUSH instructions
only specific register saved interrupts same source nested, general-purpose registers saved/restored using PUSH/POP instructions.
Example :Save/store register using PUSH instructions
PINTxx: PUSH Save register (interrupt processing) RETI Restore register RETURN
Address (Example) PSWL PSWH acceptance interrupt PSWL PSWH execution PUSH instruction PSWL PSWH execution instruction execution RETI instruction
Figure Save/store register using PUSH instructions
3.3.2.4 Using data transfer instructions
save only specific register without nested interrupts, data transfer instructions available.
Example :Save/store register using data transfer instructions
PINTxx: (GSAVA), Save register (interrupt processing) RETI (GSAVA) Restore register Return
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Interrupt Control Circuit
Interrupt Sequence TMP88FW44FG
Main task Bank
Interrupt acceptance
Main task
Interrupt service task
Bank
Interrupt acceptance
Switch bank instruction Switch bank automatically
Interrupt service task
Saving registers
Bank
Bank
Interrupt return
Restore bank automatically [RETI]/[RETN]
Restoring registers
Interrupt return
Saving/restoring register bank changeover
Saving/restoring general-purpose registers using PUSH/POP data transfer instruction
Figure Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return
Interrupt return instructions [RETI]/[RETN] perform follows.
[RETI] Maskable Interrupt Return contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag "1". interrupt nesting counter decremented, interrupt nesting flag changed. [RETN] Non-maskable Interrupt Return contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag only when non-maskable interrupt accepted interrupt enable status. However, interrupt master enable flag remains when clear interrupt service program. interrupt nesting counter decremented, interrupt nesting flag changed.
Interrupt requests sampled during final cycle instruction being executed. Thus, next interrupt accepted immediately after interrupt return instruction executed.
Note: When interrupt processing time longer than interrupt request generation time, interrupt service task performed main task.
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TMP88FW44FG
Software Interrupt (INTSW)
Executing instruction generates software interrupt immediately starts interrupt processing (INTSW highest prioritized interrupt). However, processing non-maskable inerrupt already underway, executing instruction will generate software interrupt will result same operation instruction. instruction only detection address error debugging.
3.4.1
Address error detection
read some cause such noise attempts fetch instruction from non-existent memory address during single chip mode. Code instruction, software interrupt generated address error detected. address error detection range further expanded writing unused areas program memory. Address trap reset generated case that instruction fetched from RAM, areas.
3.4.2
Debugging
Debugging efficiency increased placing instruction software break point setting address.
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Interrupt Control Circuit
External Interrupts TMP88FW44FG
External Interrupts
TMP88FW44FG external interrupt inputs. These inputs equipped with digital noise reject circuits (Pulse inputs less than certain time eliminated noise). Edge selection also possible with INT1,INT2 INT4. INT0/P10 configured either external interrupt input input/output port, configured input port during reset. Edge selection, noise reject control INT0/P10 function selection performed external interrupt control register (EINTCR).
Source INT0
INT0
Sub-Pin
Enable Conditions INT0EN=1
Release Edge (level) Falling edge
Digital Noise Reject Pulses less than 2/fc eliminated noise. Pulses 6/fc more considered signals. CGCR<DV1CK>=0). Pulses less than 15/fc 63/fc eliminated noise. Pulses 48/fc 192/fc more considered signals. CGCR<DV1CK>=0). Pulses less than 7/fc eliminated noise. Pulses 24/fc more considered signals.(at CGCR<DV1CK>=0). Pulses less than 2/fc eliminated noise. Pulses 6/fc more considered signals.
INT1
INT1
Falling edge Rising edge
INT2 INT4
INT2 INT4
P12/TC1 P22/TC4
EF29 EF31
INT5
INT5
P20/STOP
EF15
Falling edge
Note NORMAL IDLE mode, signal with noise input external interrupt pin, takes maximum "signal establishment time" from input signal's edge interrupt latch. INT1 49/fc EINTCR<INT1NC> "1") 193/fc EINTCR<INT1NC> "0") INT2 pins 25/fc Note When EINTCR<INT0EN> "0", even falling edge detected INT0 input. Note When with more than function used output change occurs data input/output status, interrupt request signal generated pseudo manner. this case, necessary perform appropriate processing such disabling interrupt enable flag.
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TMP88FW44FG
External Interrupt Control Register
EINTCR (0037H) INT1NC INT0EN INT4ES INT2ES INT1ES (Initial value: 0000 *00*)
INT1NC INT0EN
Noise reject time select P10/INT0 configuration
Pulses less than 63/fc eliminated noise Pulses less than 15/fc eliminated noise input/output port INT0 (Port should input mode) Rising edge Falling edge Rising edge Falling edge level Rising edge Falling edge
INT4
INT4 edge select
INT2 INT1
INT2 edge select INT1 edge select
Note High-frequency clock [Hz], Don't care Note When external interrupt control register (EINTCR) overwritten, noise canceller operate normally. recommended that external interrupts disabled using interrupt enable register (EIR). Note maximum time from modifying EINTCR<INT1NC> until noise reject time changed 26/fc. Note case RESET released while state INT4 keeps level, external interrupt request generated even INT4 edge select(EINTCR<INT4ES>) specified level. rising edge needed after RESET released.
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Interrupt Control Circuit
External Interrupts TMP88FW44FG
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TMP88FW44FG
Special Function Register
TMP88FW44FG adopts memory mapped system, peripheral control transfers performed through special function register (SFR) data buffer register (DBR,EBR). mapped address 0000H 003FH, mappped address 1F80H 1FFFH mapped address 1F70H 1F7FH. This chapter shows arrangement special function register (SFR) data buffer register (DBR,EBR) TMP88FW44FG.
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H TC3DRB TC3CR Reserved TC5CR TC6CR TTREG5 TTREG6 PWREG5 Reserved Reserved TC4CR TC4DR TC3DRA Read P0DR P1DR P2DR P3DR P4DR P5DR P6DR P7DR P8DR P9DR P0CR P1CR HPWMCR HPWMDR0 HPWMDR1 TC1CR TC1DRAL TC1DRAH TC1DRBL TC1DRBH CTC1CR1 CTC1CR2 CTC1DRL CTC1DRH Write
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Special Function Register
TMP88FW44FG
Address 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH
Read PWREG6 ADCCRA ADCCRB ADCDRL ADCDRH EIRC EIRE EIRD CGCR Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH PSWL PSWH
Write
WDTCR1 WDTCR2
Note access reserved areas program. Note Cannot accessed. Note Write-only registers interrupt latches cannot read-modify-write instructions (Bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.).
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TMP88FW44FG
Address 1F70H 1F71H 1F72H 1F73H 1F74H 1F75H 1F76H 1F77H 1F78H 1F79H 1F7AH 1F7BH 1F7CH 1F7DH 1F7EH 1F7FH Read UARTSR2 RDBUF2 PADR PACR PAODR PBDR PBCR PBODR PCDR PCCR PCODR Reserved Reserved Reserved Reserved Write UARTCR21 UARTCR22 TDBUF2
Note access reserved areas program. Note Cannot accessed. Note Write-only registers interrupt latches cannot read-modify-write instructions (Bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.).
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Special Function Register
TMP88FW44FG
Address 1F80H 1F81H 1F82H 1F83H 1F84H 1F85H 1F86H 1F87H 1F88H 1F89H 1F8AH 1F8BH 1F8CH 1F8DH 1F8EH 1F8FH 1F90H 1F91H 1F92H 1F93H 1F94H 1F95H 1F96H 1F97H 1F98H 1F99H 1F9AH 1F9BH 1F9CH 1F9DH 1F9EH 1F9FH 1FA0H 1FA1H 1FA2H 1FA3H 1FA4H 1FA5H 1FA6H 1FA7H 1FA8H 1FA9H 1FAAH 1FABH 1FACH 1FADH 1FAEH 1FAFH ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 MCAPL MCAPH CMP1L CMP1H CMP2L CMP2H CMP3L CMP3H MDCRA MDCRB PDCRC SDREG MTCRA MTCRB UARTSR RDBUF SIOSR SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 PDCRA PDCRB Read P0ODE P3ODE P4ODE P5ODE P8ODE P9ODE P3CR P4CR P5CR P6CR P7CR P8CR P9CR UARTSEL UARTCR1 UARTCR2 TDBUF ATAS ATKEY SIOCR1 SIOCR2 Write
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TMP88FW44FG
Address 1FB0H 1FB1H 1FB2H 1FB3H 1FB4H 1FB5H 1FB6H 1FB7H 1FB8H 1FB9H 1FBAH 1FBBH 1FBCH 1FBDH 1FBEH 1FBFH 1FC0H 1FC1H 1FC2H 1FC3H 1FC4H 1FC5H 1FC6H 1FC7H 1FC8H 1FC9H 1FCAH 1FCBH 1FCCH 1FCDH 1FCEH 1FCFH 1FD0H 1FD1H 1FD2H 1FD3H 1FD4H 1FD5H 1FD6H 1FD7H 1FD8H 1FD9H 1FDAH 1FDBH 1FDCH 1FDDH 1FDEH 1FDFH 1FE0H 1FE1H 1FE2H
ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1 ch.1
Read EMGCRA EMGCRB MDOUTL MDOUTH MDCNTL MDCNTH MDPRDL MDPRDH CMPUL CMPUH CMPVL CMPVH CMPWL CMPWH EDCRA EDCRB EDSETL EDSETH ELDEGL ELDEGH AMPL AMPH EDCAPL EDCAPH Reserved Reserved Reserved Reserved
Write
EMGREL
WFMDR
ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 MCAPL MCAPH PDCRC
PDCRA PDCRB SDREG MTCRA MTCRB CMP1L CMP1H CMP2L CMP2H CMP3L CMP3H MDCRA MDCRB EMGCRA EMGCRB MDOUTL
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Special Function Register
TMP88FW44FG
Address 1FE3H 1FE4H 1FE5H 1FE6H 1FE7H 1FE8H 1FE9H 1FEAH 1FEBH 1FECH 1FEDH 1FEEH 1FEFH 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H 1FF7H 1FF8H 1FF9H 1FFAH 1FFBH 1FFCH 1FFDH 1FFEH 1FFFH
ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2 ch.2
Read MDOUTH MDCNTL MDCNTH MDPRDL MDPRDH CMPUL CMPUH CMPVL CMPVH CMPWL CMPWH EDCRA EDCRB EDSETL EDSETH ELDEGL ELDEGH AMPL AMPH EDCAPL EDCAPH Reserved Reserved SPCR FLSCR
Write
EMGREL
WFMDR
Note access reserved areas program. Note Cannot accessed. Note Write-only registers interrupt latches cannot read-modify-write instructions (Bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.).
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TMP88FW44FG
Input/Output Ports
TMP88FW44FG contains input/output ports comprised pins.
Primary Function Port Port Port Port Port Port Port Port Port Port Port Port Port 4-bit port 8-bit port 3-bit port 8-bit port 8-bit port 8-bit port 8-bit port 8-bit port 8-bit port 8-bit port 8-bit port 8-bit port 4-bit port Secondary Functions Timer/counter input, serial interface input/output, high-speed output External interrupt input, timer/counter input/output, divider output, motor control circuit input External interrupt input, timer/counter input/output, STOP mode release signal input Motor control input/output Timer/counter output, serial interface input/output, motor control circuit input serial PROM mode control input Motor control circuit input/output Analog input motor control circuit output Analog input motor control circuit output Serial interface input/output
output ports contain latch, output data therefore retained latch. none input ports have latch, desirable that input data retained externally until read out, read several times before being processed. Figure shows input/output timing. timing which external data read from input/output ports state read cycle instruction execution. Because this timing cannot recognized from outside, transient input data such chattering needs dealt with program. timing which data forwarded input/output ports state write cycle instruction execution.
Fetch cycle Instruction execution cycle Fetch cycle Read cycle
Example:
Input strobe
Data input Input timing
Fetch cycle Instruction execution cycle
Fetch cycle (x),
Write cycle
Example:
Output latch pulse
Data output
Output timing
Note: read/write cycle positions vary depending instructions.
Figure Example Input/Output Timing
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Input/Output Ports
TMP88FW44FG
When operation performed read from input/output port except programmable input/output ports, whether input value content output latch read depends instruction executed, shown below. Instructions which read content output latch (src) SET/CLR/CPL (src).b SET/CLR/CPL (pp).g (src).b, (pp).b, (src). ADD/ADDC/SUB/SUBB/AND/OR/XOR ADD/ADDC/SUB/SUBB/AND/OR/XOR MXOR (src), Instructions which read input value instructions other than those listed above ADD/ADDC/SUB/SUBB/AND/OR/XOR (src),(HL) instructions, (HL) side thereof (src), (src), (HL) instructions, (src) side thereof
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TMP88FW44FG
Port (P03 P00)
Port 4-bit input/output port shared with serial interface input/output. This port switched between input output modes using port input/output control register (P0CR). When reset, P0CR register initialized with port input mode. Also, output latch (P0DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P0ODE) used select open-drain tri-state mode port. When reset, P0ODE register initialized with tristate mode selected port.
P0CRi Data input Data output Control output Control input Output latch
External input Control input values Note:
Figure Port
Port Input/Output Registers
P0DR (00000H)
HPWM1
HPWM0
TC6O TXD2
TC6I RXD2 (Initial value: **** 0000) Read/Write (Initial value: **** 0000) TC6O: PDO6, PWM6, PPG6
P0CR (0000AH)
P0CR
port input/output control (Specify bitwise)
Input mode Output mode
P0ODE (01F80H)
(Initial value: **** 0000)
P0ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out. Note Don't care
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Input/Output Ports
TMP88FW44FG
Port (P17 P10)
Port 8-bit input/output port shared with external interrupt input, timer/counter input/output, divider output. This port switched between input output modes using port input/output control register (P1CR). When reset, P1CR register initialized with port input mode. Also, output latch (P1DR) initialized when reset.
P1CRi Data input Data output Control output Control input Output latch
External input Control input values Note:
Figure Port
Port Input/Output Registers
P1DR (00001H) PDW2 PDV2 PDU2
PPG1
INT2
INT1
INT0
TC5O P1CR (0000BH)
TC5I
Read/Write (Initial value: 0000 0000) TC5O: PDO5, PWM5
(Initial value: 0000 0000)
P1CR
port input/output control (Specify bitwise)
Input mode Output mode
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TMP88FW44FG
Port (P22 P20)
Port 3-bit input/output port shared with external interrupt input STOP mode release signal. When using this port these functional pins input port, output latch When reset, output latch initialized recommend using external interrupt input, STOP mode release signal input, input port. When using this port output port, note that interrupt latch falling edge output pulse. note that outputs this port during STOP mode high-impedance state even SYSCR1<OUTEN> because port also used STOP port. When read instruction executed port, indeterminate values read from bits When read-modify-write instruction executed port, content output latch read out. When other instruction executed, external state read out.
SET/CLR/CPL, Data input Data output Control input Output latch
CMP/MCMP/TEST,
P20, P21,
Figure Port
Port Input/Output Registers
P2DR (00002H) INT4
PWM4 PDO4
INT5 STOP
Read/Write (Initial value: **** *111)
Note When read instruction executed port, indeterminate values read from bits Note Port used STOP pin. Therefore, when stop mode started, SYSCR1<OUTEN> does affect P20, becomes High-Z mode. Note Don't care
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Input/Output Ports
TMP88FW44FG
Port (P37 P30)
Port 8-bit input/output port. This port switched between input output modes using port Input/ output Control Register (P3CR). When reset, P3CR Register initialized with port input mode. Also, Output Latch (P3DR) initialized when reset. port contains bitwise programmable open-drain control. Port Open-drain Control Register (P3ODE) used select open-drain tri-state mode port. When reset, P3ODE Register initialized with tri-state mode selected port.
P3CRi Data input Data output Control output Control input Output latch
External input Control input values Note:
Figure Port
Port Input/Output Registers
P3DR (00003H) P3CR (01F89H)
EMG1
(Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
P3CR
port input/output control (Specify bitwise)
Input mode Output mode
P3ODE (01F83H)
(Initial value: 0000 0000)
P3ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out. Note circuit output, P3DR output latch Note When using port input/output port, disable EMG1 circuit.
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TMP88FW44FG
Port (P47 P40)
Port 8-bit input/output port shared with serial interface input/output serial PROM mode control input. This port switched between input output modes using port input/output control register (P4CR). When reset, P4CR register initialized with port input mode. Also, output latch (P4DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P4ODE) used select open-drain tri-state mode port. When reset, P4ODE register initialized with tristate mode selected port.
P4CRi Data input Data output Control output Control input Output latch
External input Control input values Note:
Figure Port
Port Input/Output Registers
P4DR (00004H)
PPG2
TXD1
RXD1 BOOT
PDU1
PDV1
PDW1
(Initial value: 0000 0000)
P4CR (01F8AH)
(Initial value: 0000 0000)
P4CR
port input/output control (Specify bitwise)
Input mode Output mode
P4ODE (01F84H)
(Initial value: 0000 0000)
P4ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out. Note When using 16-bit timer (CTC) ordinary timer, (CTC) output mode.
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Input/Output Ports
TMP88FW44FG
Port (P57 P50)
Port 8-bit input/output port. This port switched between input output modes using port input/ output control register (P5CR). When reset, P5CR register initialized with port input mode. Also, output latch (P5DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P5ODE) used select open-drain tri-state mode port. When reset, P5ODE register initialized with tristate mode selected port.
P5CRi Data input Data output Control output Control input Output latch
External input Control input value Note:
Figure Port
Port Input/Output Registers
P5DR (00005H) P5CR (01F8BH)
EMG2
Read/Write (Initial value: 0000 0000)
(Initial value: 0000 0000)
P5CR
port input/output control (Specify bitwise)
Input mode Output mode
P5ODE (01F85H)
(Initial value: 0000 0000)
P5ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out. Note circuit output, P5DR output latch Note When using port input/output port, disable EMG2 circuit.
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TMP88FW44FG
Port (P67 P60)
Port 8-bit input/output port shared with converter analog input. This port switched between input output modes using port input/output control register (P6CR), port output latch (P6DR), ADCCRA<AINDS>. When reset, P6CR Register P6DR output latch initialized while ADCCRA<AINDS> that have their inputs fixed When using port input port, corresponding bits input mode (P6CR P6DR reason output latch because necessary prevent current from flowing into shared data input circuit. When using port output port, P6CR Register's corresponding bits When using port analog input, corresponding bits analog input (P6CR P6DR Then ADCCRA<AINDS> conversion will start. ports used analog input must have their output latches beforehand. actual input channels conversion selected using ADCCRA<SAIN>. Although bits port used analog input used input/output ports, execute output instructions these ports during conversion. This necessary maintain accuracy conversion. Also, apply rapidly changing signals ports adjacent analog input during conversion. input instruction executed while P6DR output latch cleared data read from said bits.
Analog input AINDS SAIN P6CRi P6CRi input Data input (P6) Data output (P6) STOP Note Note STOP exists SYSCR1 register Note SAIN selects input channels.
Figure Port
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Input/Output Ports
TMP88FW44FG
Port Input/Output Registers
P6DR (00006H) AIN7 DBOUT1 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
P6CR (01F8CH)
AINDS (when using port input/output control (Specify bitwise) P6DR Inputs fixed P6DR Input mode
AINDS (when using P6DR Analog Input mode (Note2) P6DR Input mode
P6CR
Output mode
Note pins used analog input cannot output mode (P6CR because they become shorted with external signals. Note When read instruction executed bits this port which analog input mode, data read Note DBOUT1 output, P6DR (P67) output latch Note When using this port input mode (including analog input), manipulating other read-modify-write instructions. When read instruction executed bits this port that input, contents pins read that read-modify-write instruction executed, their output latches rewritten, making pins unable accept input. read-modify-write instruction first reads data from eight bits after modifying them (bit manipulation), writes data eight bits output latches.)
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TMP88FW44FG
Port (P77 P70)
Port 8-bit input/output port shared with converter analog input. This port switched between input output modes using port input/output control register (P7CR), port output latch (P7DR), ADCCRA<AINDS>. When reset, P7CR register P7DR output latch initialized while ADCCRA<AINDS> that have their inputs fixed When using port input port, corresponding bits input mode (P7CR P7DR reason output latch because necessary prevent current from flowing into shared data input circuit. When using port output port, P7CR Register's corresponding bits When using port analog input, corresponding bits analog input (P7CR P7DR Then ADCCRA<AINDS> conversion will start. ports used analog input must have their output latches beforehand. actual input channels conversion selected using ADCCRA<SAIN>. Although bits port used analog input used input/output ports, execute output instructions these ports during conversion. This necessary maintain accuracy conversion. Also, apply rapidly changing signals ports adjacent analog input during conversion. input instruction executed while P7DR output latch cleared data read from said bits.
Analog input AINDS SAIN P7CRi P7CRi input Data input (P7) Data output (P7) STOP Note Note STOP exists SYSCR1 register Note SAIN selects input channels.
Figure Port
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Input/Output Ports
TMP88FW44FG
Port Input/Output Registers
P7DR (00007H) AIN15 DBOUT2 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
P7CR (01F8DH)
AINDS (when using port input/output control (Specify bitwise) P7DR Inputs fixed P7DR Input mode
AINDS (when using P7DR Analog Input mode (Note2) P7DR Input mode
P7CR
Output mode
Note pins used analog input cannot output mode (P7CR because they become shorted with external signals. Note When read instruction executed bits this port which analog input mode, data read Note DBOUT2 output, P7DR (P77) output latch Note When using this port input mode (including analog input), manipulating other read-modify-write instructions. When read instruction executed bits this port that input, contents pins read that read-modify-write instruction executed, their output latches rewritten, making pins unable accept input. read-modify-write instruction first reads data from eight bits after modifying them (bit manipulation), writes data bits output latches.)
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TMP88FW44FG
Port (P87 P80)
Port 8-bit input/output port. This port switched between input output modes using port input/ output control register (P8CR). When reset, P8CR register initialized with port input mode. Also, output latch (P8DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P8ODE) used select open-drain tri-state mode port. When reset, P8ODE register initialized with tristate mode selected port.
P8CRj Data input Data output Control output Control input P8CRi Data input P80, Note: External input
Output latch
Control input value
Data output
Output latch
Note:
Figure 5-10 Port
Port Input/Output Registers
P8DR (00008H) P8CR (01F8EH) TXD3 RXD3 (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
P8CR
port input/output control (Specify bitwise)
Input mode Output mode
P8ODE (01F86H)
(Initial value: 0000 0000)
P8ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
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Input/Output Ports
TMP88FW44FG
5.10 Port (P97 P90)
Port 8-bit input/output port. This port switched between input output modes using port input/ output control register (P9CR). When reset, P9CR register initialized with port input mode. Also, output latch (P9DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P9ODE) used select open-drain tri-state mode port. When reset, P9ODE register initialized with tristate mode selected port.
P9CRi Data input Data output Output latch
Figure 5-11 Port
Note:
Port Input/Output Registers
P9DR (00009H) P9CR (01F8FH) (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
P9CR
port input/output control (Specify bitwise)
Input mode Output mode
P9ODE (01F87H)
(Initial value: 0000 0000)
P9ODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
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TMP88FW44FG
5.11 Port (PA7 PA0)
Port 8-bit input/output port. This port switched between input output modes using port input/output control register (PACR). When reset, PACR register initialized with port input mode. Also, output latch (PADR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (PAODE) used select open-drain tri-state mode port. When reset, PAODE register initialized with tristate mode selected port.
PACRi Data input
Data output
Output latch
Note:
Figure 5-12 Port
Port Input/Output Registers
PADR (01F73H) PACR (01F74H) (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
PACR
port input/output control (Specify bitwise)
Input mode Output mode
PAODE (01F75H)
(Initial value: 0000 0000)
PAODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
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Input/Output Ports
TMP88FW44FG
5.12 Port (PB7 PB0)
Port 8-bit input/output port. This port switched between input output modes using port input/output control register (PBCR). When reset, PBCR register initialized with port input mode. Also, output latch (PBDR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (PBODE) used select open-drain tri-state mode port. When reset, PBODE register initialized with tristate mode selected port.
PBCRi Data input
Data output
Output latch
Note:
Figure 5-13 Port
Port Input/Output Registers
PBDR (01F76H) PBCR (01F77H) (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000)
PBCR
port input/output control (Specify bitwise)
Input mode Output mode
PBODE (01F78H)
(Initial value: 0000 0000)
PBODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
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TMP88FW44FG
5.13 Port (PC3 PC0)
Port 4-bit input/output port. This port switched between input output modes using port input/output control register (PCCR). When reset, PCCR register initialized with port input mode. Also, output latch (PCDR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (PCODE) used select open-drain tri-state mode port. When reset, PCODE register initialized with tristate mode selected port.
PCCRi Data input
Data output
Output latch
Note:
Figure 5-14 Port
Port Input/Output Registers
PCDR (01F79H) PCCR (01F7AH) (Initial value: **** 0000) Read/Write (Initial value: **** 0000)
PCCR
port input/output control (Specify bitwise)
Input mode Output mode
PCODE (01F7BH)
(Initial value: **** 0000)
PCODE
port open-drain control (Specify bitwise)
Tri-state Open-drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
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Input/Output Ports
TMP88FW44FG
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TMP88FW44FG
Time Base Timer (TBT) Divider Output (DVO)
Time Base Timer
time base timer generates time base scanning, dynamic displaying, etc. also provides time base timer interrupt (INTTBT). INTTBT Time Base Timer Interrupt generated first falling edge source clock divider output timing generator which selected TBTCK. after time base timer been enabled. divider cleared program; therefore, only first interrupt generated ahead interrupt period Figure interrupt frequency (TBTCK) must selected with time base timer disabled (TBTEN="0"). (The interrupt frequency must changed with disble from enable state.) Both frequency selection enabling performed simultaneously.
fc/223,fc/224 fc/221,fc/222 fc/216,fc/217 fc/214,fc/215 fc/213,fc/214 fc/212,fc/213 fc/211,fc/212 fc/29,fc/210
Source clock
Falling edge detector INTTBT interrupt request
TBTCK TBTCR Time base timer control register TBTEN
Figure Time Base Timer configuration
Source clock
TBTCR<TBTEN>
INTTBT interrupt request Interrupt period Enable
Figure Time Base Timer Interrupt
Example :Set time base timer frequency fc/216 [Hz] enable INTTBT interrupt.
(EIRL) (TBTCR) 00000010B (TBTCR) 00001010B TBTCK (Freq. set) TBTEN (TBT enable)
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Time Base Timer (TBT) Divider Output (DVO)
Time Base Timer TMP88FW44FG
Time Base Timer controled Time Base Timer control register (TBTCR). Time Base Timer Control Register
TBTCR (00036H) (DVOEN) (DVOCK) TBTEN TBTCK (Initial Value: 0000 0000)
TBTEN
Time Base Timer Enable Disable
Disable Enable NORMAL, IDLE Mode DV1CK=0 fc/2
DV1CK=1 fc/224 fc/222 fc/217 fc/215 fc/214 fc/213 fc/212 fc/210
fc/221 fc/216 fc/214 fc/213 fc/212 fc/211 fc/29
TBTCK
Time Base Timer interrupt Frequency select [Hz]
Note High-frequency clock [Hz], Don't care Note Always bit4 TBTCR register.
Table Time Base Timer Interrupt Frequency Example 20.0
Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL, IDLE Mode DV1CK 2.38 9.53 305.18 1220.70 2441.40 4882.83 9765.63 39063.00 DV1CK 1.20 4.78 153.50 610.35 1220.70 2441.40 4882.83 19531.25
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TMP88FW44FG
Divider Output (DVO)
Approximately duty pulse output using divider output circuit, which useful piezoelectric buzzer drive. Divider output from pin.
Output latch Data output
fc/213,fc/214 fc/212,fc/213 fc/211,fc/212 fc/210,fc/211
DVOCK TBTCR Divider output control register configuration DVOEN
Port output latch TBTCR<DVOEN>
output Timing chart
Figure Divider Output
Divider Output controlled Time Base Timer Control Register (TBTCR). Time Base Timer Control Register
TBTCR (00036H) DVOEN DVOCK (TBTEN) (TBTCK) (Initial value: 0000 0000)
DVOEN
Divider output enable disable
Disable Enable NORMAL, IDLE Mode DV1CK=0 DV1CK=1 fc/214 fc/213 fc/212 fc/211
DVOCK
Divider Output (DVO) frequency selection: [Hz]
fc/2
fc/212 fc/211 fc/210
Note Selection divider output frequency (DVOCK) must made while divider output disabled (DVOEN="0"). Also, other words, when changing state divider output frequency from enabled (DVOEN="1") disable(DVOEN="0"), change setting divider output frequency. Note case using output, output mode P1CR register after setting related port output latch P1DR register. Note High-frequency clock [Hz], Don't care Note sure write TBTCR Register
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Time Base Timer (TBT) Divider Output (DVO)
Divider Output (DVO) TMP88FW44FG
Example 2.44 pulse output 20.0 MHz)
Port setting
(TBTCR) 00000000B (TBTCR) 10000000B
DVOCK "00" DVOEN
Table Divider Output Frequency Example 20.0
Divider Output Frequency [Hz] DVOCK NORMAL, IDLE Mode DV1CK=0 2.4415 4.8825 9.765 19.5325 DV1CK=1 1.22075 2.4415 4.8825 9.765
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TMP88FW44FG
Watchdog Timer (WDT)
watchdog timer fail-safe system detect rapidly malfunctions such endless loops spurious noises deadlock conditions, return system recovery routine. watchdog timer signal detecting malfunctions programmed only once "reset request" "pseudo nonmaskable interrupt request". Upon reset release, this signal initialized "reset request". When watchdog timer used detect malfunctions, used timer provide periodic interrupt.
Note: Care must taken system design since watchdog timer functions operated completely effect disturbing noise.
Watchdog Timer Configuration
Reset release
fc/2 ,fc/2 fc/221,fc/222 fc/219,fc/220 fc/217,fc/218
Selector
Binary counters Clock Clear Overflow output
Reset request INTWDT interrupt request
Interrupt request
Internal reset
WDTEN WDTT
Writing disable code
Writing clear code
WDTOUT
Controller
0034H WDTCR1
0035H WDTCR2
Watchdog timer control registers
Figure Watchdog Timer Configuration
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Watchdog Timer (WDT)
Watchdog Timer Control TMP88FW44FG
Watchdog Timer Control
watchdog timer controlled watchdog timer control registers (WDTCR1 WDTCR2). watchdog timer automatically enabled after reset release.
7.2.1
Malfunction Detection Methods Using Watchdog Timer
malfunction detected, shown below. detection time, select output, clear binary counter. Clear binary counter repeatedly within specified detection time. malfunctions such endless loops deadlock conditions occur some reason, watchdog timer output activated binary-counter overflow unless binary counters cleared. When WDTCR1<WDTOUT> this time, reset request generated then internal hardware initialized. When WDTCR1<WDTOUT> "0", watchdog timer interrupt (INTWDT) generated. watchdog timer temporarily stops counting STOP mode including warm-up IDLE mode, automatically restarts (continues counting) when STOP/IDLE mode inactivated.
Note:The watchdog timer consists internal divider two-stage binary counter. When clear code written, only binary counter cleared, internal divider. minimum binary-counter overflow time, that depends timing which clear code (4EH) written WDTCR2 register, time WDTCR1<WDTT>. Therefore, write clear code using cycle shorter than time WDTCR1<WDTT>.
Example :Setting watchdog timer detection time 221/fc [s], resetting malfunction detection
(WDTCR2), (WDTCR1), 00001101B (WDTCR2), Clears binary counters. WDTT WDTOUT Clears binary counters (always clears immediately before after changing WDTT).
Within detection time
(WDTCR2),
Clears binary counters.
Within detection time
(WDTCR2), Clears binary counters.
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TMP88FW44FG
Watchdog Timer Control Register
WDTCR1 (0034H) WDTEN WDTT WDTOUT (Initial value: **** 1001)
WDTEN
Watchdog timer enable/disable
Disable (Writing disable code WDTCR2 required.) Enable NORMAL mode DV1CK DV1CK 226/fc 224/fc 222fc 220/fc
Write only
WDTT
Watchdog timer detection time
225/fc 223/fc 221fc 219/fc
Write only
WDTOUT
Watchdog timer output select
Interrupt request Reset request
Write only
Note After clearing WDTCR1<WDTOUT> "0", program cannot "1". Note High-frequency clock [Hz], Don't care Note WDTCR1 write-only register must used with read-modify-write instructions. WDTCR1 read, unknown data read. Note activate STOP mode, disable watchdog timer clear counter immediately before entering STOP mode. After clearing counter, clear counter again immediately after STOP mode inactivated. Note clear WDTCR1<WDTEN>, register accordance with procedures shown "7.2.3 Watchdog Timer Disable". Note watchdog timer disabled during watchdog timer interrupt processing, watchdog timer interrupt will never cleared. Therefore, clear watchdog timer clear code (4EH) WDTCR2 before disabling disable watchdog timer sufficient time before overflows. Note watchdog timer consists internal divider two-stage binary counter. When clear code (4EH) written, only binary counter cleared, internal divider. Depending timing which clear code (4EH) written WDTCR2 register, overflow time binary counter minimum time WDTCR1<WDTT>. Thus, write clear code using shorter cycle than time WDTCR1<WDTT>.
Watchdog Timer Control Register
WDTCR2 (0035H) (Initial value: **** ****)
WDTCR2
Write Watchdog timer control code
4EH: Clear watchdog timer binary counter (Clear code) B1H: Disable watchdog timer (Disable code) Others: Invalid
Write only
Note disable code valid only when WDTCR1<WDTEN> Note Don't care Note binary counter watchdog timer must cleared interrupt task. Note Write clear code (4EH) using cycle shorter than time WDTCR1<WDTT>. Note WDTCR2 write-only register must used with read-modify-write instructions. WDTCR2 read, unknown data read.
7.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> enables watchdog timer. Since WDTCR1<WDTEN> initialized during reset, watchdog timer enabled automatically after reset release.
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Watchdog Timer (WDT)
Watchdog Timer Control TMP88FW44FG
7.2.3
Watchdog Timer Disable
disable watchdog timer, register accordance with following procedures. Setting register other procedures causes malfunction microcontroller. interrupt master flag (IMF) "0". WDTCR2 clear code (4EH). WDTCR1<WDTEN> "0". WDTCR2 disable code (B1H).
Note:While watchdog timer disabled, binary counters watchdog timer cleared.
Example :Disabling watchdog timer
(WDTCR2), 04EH (WDTCR1), 0B101H Clears binary coutner WDTEN WDTCR2 Disable code
Table Watchdog Timer Detection Time (Example: MHz) Watchdog Timer Detection Time[s]
WDTT DV1CK 1.678 419.430 104.858 26.214 NORMAL Mode DV1CK 3.355 838.861 209.715 52.429
Note: watchdog timer disabled during watchdog timer interrupt processing, watchdog timer interrupt will never cleared. Therefore, clear watchdog timer clear code (4EH) WDTCR2 before disabling disable watchdog timer sufficient time before overflows.
7.2.4
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> cleared "0", watchdog timer interrupt request (INTWDT) generated binary-counter overflow. watchdog timer interrupt non-maskable interrupt which accepted regardless interrupt master flag (IMF). When watchdog timer interrupt generated while other interrupt including watchdog timer interrupt already accepted, watchdog timer interrupt processed immediately previous interrupt held pending. Therefore, watchdog timer interrupts generated continuously without execution RETN instruction, many levels nesting cause malfunction microcontroller. generate watchdog timer interrupt, stack pointer before setting WDTCR1<WDTOUT>.
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TMP88FW44FG
Example :Setting watchdog timer interrupt
010BFH (WDTCR1), 00001000B Sets stack pointer WDTOUT
7.2.5
Watchdog Timer Reset
When binary-counter overflow occurs while WDTCR1<WDTOUT> "1", watchdog timer reset request generated. When watchdog timer reset request generated, internal hardware reset. reset time maximum 24/fc max. MHz).
219/fc 217/fc
Clock Binary counter Overflow INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
(WDTT=11B)
Internal reset
(WDTCR1<WDTOUT>= "1")
reset occurs Write WDTCR2
Figure Watchdog timer Interrupt Reset
Page
Watchdog Timer (WDT)
Watchdog Timer Control TMP88FW44FG
Page
MCAP1
INTTC1 interript
TC1S
Configuration
Start MPPG1 TC1S clear Clear output mode
Decoder
Command start
Pulse width measurement mode
External trigger
External trigger start
Rising
Falling
Edge detector
METT1
Clear Match Source clock 16-bit up-counter Pulse width measurement mode
Port (Note)
16-Bit TimerCounter (TC1)
Figure TimerCounter (TC1)
Toggle Clear Selector Capture TC1DRB TC1DRA 16-bit timer register Toggle Enable Clear output mode Internal reset Write TC1CR TFF1
Page
fc/2 fc/2
fc/27, fc/28
fc/23, fc/24
Window mode Port (Note)
ACAP1
TC1CK
TC1CR
control register
TMP88FW44FG
Note: Function operate depending port setting. more details, chapter "I/O Port".
16-Bit TimerCounter (TC1)
TimerCounter Control TMP88FW44FG
TimerCounter Control
TimerCounter controlled TimerCounter control register (TC1CR) 16-bit timer registers (TC1DRA TC1DRB). Timer Register
TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TC1DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0010H) Read/Write TC1DRBL (0012H) Read/Write (Write enabled only output mode)
TimerCounter Control Register
TC1CR (000FH) ACAP1 MCAP1 METT1 MPPG1 Read/Write (Initial value: 0000 0000)
TFF1
TC1S
TC1CK
TC1M
TFF1 ACAP1 MCAP1 METT1 MPPG1
Timer F/F1 control Auto capture control Pulse width measurement mode control External trigger timer mode control output control
Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer Stop counter clear Command start Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window)
1:Auto-capture enable 1:Single edge capture
1:Trigger start stop 1:One-shot Extrigger Event Window Pulse
TC1S
start control
NORMAL, IDLE mode DV1CK TC1CK source clock select [Hz] operating mode select fc/2
DV1CK fc/212 fc/28 fc/24 External clock (TC1 input)
fc/27 fc/23
TC1M
Timer/external trigger timer/event counter mode Window mode Pulse width measurement mode (Programmable pulse generate) output mode
Note High-frequency clock [Hz] Note timer register consists shift registers. value timer register becomes valid rising edge first source clock pulse that occurs after upper byte (TC1DRAH TC1DRBH) written. Therefore, write lower byte upper byte this order recommended write register with 16-bit access instruction). Writing only lower byte (TC1DRAL TC1DRBL) does enable setting timer register. Note mode, source clock, output control timer control, write TC1CR during TC1CR<TC1S>=00. timer F/F1 control until first timer start after setting mode. Note Auto-capture used only timer, event counter, window modes.
Page
TMP88FW44FG
Note timer registers, following relationship must satisfied. TC1DRA TC1DRB (PPG output mode), TC1DRA (other modes) Note TC1CR<TFF1> mode except output mode. Note TC1DRB after setting TC1CR<TC1M> output mode. Note When STOP mode entered, start control (TC1CR<TC1S>) cleared "00" automatically, timer stops. After STOP mode exited, TC1CR<TC1S> timer counter again. Note auto-capture function operative condition TC1. captured value fixed it's read after execution timer stop auto-capture disable. Read capture value capture enabled condition. Note 10:Since up-counter value captured into TC1DRB source clock up-counter after setting TC1CR<ACAP1> "1". Therefore, read captured value, wait least cycle internal source clock before reading TC1DRB first time.
Page
16-Bit TimerCounter (TC1)
Function TMP88FW44FG
Function
TimerCounter types operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes.
8.3.1
Timer mode
timer mode, up-counter counts using internal clock. When match between up-counter timer register (TC1DRA) value detected, INTTC1 interrupt generated up-counter cleared. After being cleared, up-counter restarts counting. Setting TC1CR<ACAP1> captures upcounter value into timer register (TC1DRB) with auto-capture function. auto-capture function operative condition TC1. captured value fixed it's read after execution timer stop auto-capture disable. Read capture value capture enabled condition. Since upcounter value captured into TC1DRB source clock up-counter after setting TC1CR<ACAP1> "1". Therefore, read captured value, wait least cycle internal source clock before reading TC1DRB first time. Table
TC1CK DV1CK Resolution [µs] 102.4 Maximum Time Setting 6.7108 0.4194 26.214
Source Clock TimerCounter (Example: MHz)
NORMAL, IDLE Mode DV1CK Resolution [µs] 204.8 12.8 Maximum Time Setting 13.4216 0.8388 52.428
Example :Setting timer mode with source clock fc/211 [Hz] generating interrupt second later MHz, CGCR<DV1CK> "0")
(TC1CR), 00000000B (TC1CR), 00010000B (EIRD). (TC1DRA), 2625H Sets timer register 211/fc 2625H) IMF= Enables INTTC1 IMF= Selects source clock mode Starts
Example :Auto-capture
(TC1CR), 01010000B (TC1DRB) ACAP1 Wait least cycle internal source clock Reads capture value
Page
TMP88FW44FG
Timer start Source clock Counter TC1DRA
INTTC1 interruput request
Match detect Timer mode
Counter clear
Source clock
Counter
Capture
Capture
TC1DRB
ACAP1 Auto-capture
Figure Timer Mode Timing Chart
Page
16-Bit TimerCounter (TC1)
Function TMP88FW44FG
8.3.2
External Trigger Timer Mode
external trigger timer mode, up-counter starts counting input pulse triggering pin, counts edge internal clock. trigger edge used start counting, either rising falling edge defined TC1CR<TC1S>. When TC1CR<METT1> (trigger start stop) When match between up-counter TC1DRA value detected after timer starts, up-counter cleared halted INTTC1 interrupt request generated. edge opposite trigger edge detected before detecting match between up-counter TC1DRA, up-counter cleared halted without generating interrupt request. Therefore, this mode used detect exceeding specified pulse interrupt. After being halted, up-counter restarts counting when trigger edge detected. When TC1CR<METT1> (trigger start) When match between up-counter TC1DRA value detected after timer starts, up-counter cleared halted INTTC1 interrupt request generated. edge opposite trigger edge effect count trigger edge next counting ignored detecting before detecting match between up-counter TC1DRA.
Since input noise rejection, pulses 4/fc less rejected noise. pulse width 12/fc more required ensure edge detection. Example :Generating interrupt after rising edge input pulse MHz, CGCR<DV1CK> "1")
(TC1CR), 00001000B (TC1CR), 00111000B (EIRD). (TC1DRA), 007DH 27/fc IMF= Enables INTTC1 interrupt IMF= Selects source clock mode Starts external trigger, METT1
Example :Generating interrupt when low-level pulse with more width input MHz, CGCR<DV1CK> "1")
(TC1CR), 00000100B (TC1CR), 01110100B (EIRD). (TC1DRA), 0138H 28/fc 0138H IMF= Enables INTTC1 interrupt IMF= Selects source clock mode Starts external trigger, METT1
Page
TMP88FW44FG
Count start input
Count start
rising edge (TC1S
Source clock
Up-counter
TC1DRA
Match detect
Count clear
INTTC1 interrupt request
Trigger start (METT1
rising edge (TC1S
Count start
Count clear
Count start
input
Source clock
Up-counter
TC1DRA
Match detect
Count clear
INTTC1 interrupt request
Note:
Trigger start stop (METT1
Figure External Trigger Timer Mode Timing Chart
Page
16-Bit TimerCounter (TC1)
Function TMP88FW44FG
8.3.3
Event Counter Mode
event counter mode, up-counter counts edge input pulse pin. Either rising falling edge input pulse selected count edge TC1CR<TC1S>. When match between up-counter TC1DRA value detected, INTTC1 interrupt generated up-counter cleared. After being cleared, up-counter restarts counting each edge input pulse pin. Since match between up-counter value TC1DRA detected edge opposite selected edge, INTTC1 interrupt request generated after match value edge opposite selected edge. more machine cycles required low-or high-level pulse input pin. Setting TC1CR<ACAP1> captures up-counter value into TC1DRB with auto capture function. auto-capture function operative condition TC1. captured value fixed it's read after execution timer stop auto-capture disable. Read capture value capture enabled condition. Since up-counter value captured into TC1DRB source clock up-counter after setting TC1CR<ACAP1> "1". Therefore, read captured value, wait least cycle internal source clock before reading TC1DRB first time.
Timer start
Input Up-counter TC1DRA INTTC1 interrput request
rising edge (TC1S
Match detect
Counter clear
Figure Event Counter Mode Timing Chart
Table Input Pulth Width
Minimum Pulse Width NORMAL, IDLE Mode High-going Low-going 23/fc 23/fc
Page
TMP88FW44FG
8.3.4
Window Mode
window mode, up-counter counts rising edge pulse that logical ANDed product input pulse (window pulse) internal source clock. Either positive logic (count during high-going pulse) negative logic (count during low-going pulse) selected. When match between up-counter TC1DRA value detected, INTTC1 interrupt generated up-counter cleared. Define window pulse frequency which sufficiently lower than internal source clock programmed with TC1CR<TC1CK>.
Count start Timer start Count stop Count start
input Internal clock Counter TC1DRA INTTC1 interrput request Match detect Positive logic (TC1S
Timer start Count start Count stop Count start
Counter clear
input Internal clock Counter TC1DRA INTTC1 interrput request Negative logic (TC1S Match detect Counter clear
Figure Window Mode Timing Chart
Page
16-Bit TimerCounter (TC1)
Function TMP88FW44FG
8.3.5
Pulse Width Measurement Mode
pulse width measurement mode, up-counter starts counting input pulse triggering pin, counts edge internal clock. Either rising
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