Serial Peripheral Interface -Slave 1.01 DSPIS fully configurable

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Serial Peripheral Interface -Slave 1.01 DSPIS fully configurable

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DSPIS
Serial Peripheral Interface -Slave 1.01
DSPIS fully configurable slave device, designated operate with passive devices like memories, drivers etc. DSPIS allows user configure polarity phase serial clock signal SCK. serial clock line (SCK) synchronizes shifting sampling information independent serial data lines. DSPIS data simultaneously transmitted received. DSPIS system flexible enough interface directly with numerous standard product peripherals from several manufacturers. Data rates high CLK/4. Clock control logic allows selection clock polarity choice fundamentally different clocking protocols accommodate most available synchronous serial peripheral devices. DSPIS allows Master communicate with passive devices. When transmission starts Line goes low) first portion data copied address register then ADDRESS output, after transmission address DSPIS generates read signal (RD) copy DATAI contents transmitter shift register, prepare data exchanged with Master. During next data portion transmission DSPIS simultaneously transmits data When first data portion received DSPIS asserts DATAO generates write signal (WE), then increments ADDRESS performs read operation prepare another data portion exchanged with
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master. Transmission ended when line goes high. DSPIS technology independent design that implemented variety process technologies. DSPIS fully customizable, which means delivered exact configuration meet users' requirements. There need extra used features wasted silicon. includes fully automated testbench with complete tests allowing easy package validation each stage design flow.
APPLICATIONS
Embedded microprocessor boards Consumer professional audio/video Home automotive radio Digital multimeters
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FEATURES
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
Slave
Slave operation Automatic read write operations Automatic address incrementation after data portion transfer Configurable address data length. Configurable phase polarity. Supports speeds system clock Simple interface allows easy connection passive devices, Master
Fully synthesizable, static synchronous design with internal tri-states
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
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SYMBOL
datai(D:0) cpha cpol datao(D:0) address(A:0)
ments. flexibility system DSPIS allows direct interface almost existing synchronous serial peripheral. Shift register- central element system. When transfer occurs, 8-bit character shifted data while different 8-bit character simultaneously shifted second data pin. Another view this transfer that 8-bit shift register master another 8-bit shift register slave connected circular 16-bit shift register. When transfer occurs, this distributed shift register shifted eight positions; thus, characters master slave effectively exchanged.
cpha cpol
PINS DESCRIPTION
datai(D:0) cpha cpol datao(D:0) addres(A:0)
TYPE
input input input input input input input input output output output output output
DESCRIPTION
Global clock Global reset Data input clock phase clock polarity serial clock serial data input Slave select Data output Address output Read output Write enable Slave serial data output
Clock Logic
Shift Reg.
datai
Data reg. Adr. reg.
Controller
datao address
Data Register holds data read from passive device sent serially Master. Address Register holds address presented Address bus. it's contents incremented every single data portion sent/received serially through bus. Controller detects begin transfer. Manages data exchange between DSPIS passive device controlled DSPIS, increment Address Register (SPAD) after successful transfer.
BLOCK DIAGRAM
Clock logic controls phase polarity clock line, detects correct sample shift edge Shift register. clock Logic allow user select four combinations serial clock (SCK) phase polarity using pins CPHA CPOL. clock polarity specified CPOL, which selects active high active clock significant effect transfer format. clock phase CPHA selects fundamentally different transfer formats. clock phase polarity should identical master device communicating slave device. some cases, phase polarity changed between transfers allow master device communicate with peripheral slaves having different requireAll trademarks mentioned this document trademarks their respective owners.
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PERFORMANCE
following table gives survey about Core performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade CYCLONE CYCLONE2 STRATIX STRATIX2 STRATIXGX MERCURY EXCALIBUR APEX2A APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE MAX2 MAX3K MAX7K Core performance ALTERA® devices Device
Transfer Formats
Software select four combinations serial clock (SCK) phase polarity using bits control register (SPCR). clock polarity specified CPOL control bit, which selects active high active clock significant effect transfer format. clock phase (CPHA) control selects fundamentally different transfer formats. clock phase polarity should identical master device communicating slave device. some cases, phase polarity changed between transfers allow master device communicate with peripheral slaves having different requirements. flexibility system DSPI allows direct interface almost existing synchronous serial peripheral.
L=0) L=1)
(CPO L=0) L=1)
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CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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Serial Peripheral Interface -Slave 1.01 DSPIS fully configurable

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