Serial Peripheral Interface Master/Slave with FIFO 1.07 DSPI_FIFO

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Serial Peripheral Interface Master/Slave with FIFO 1.07 DSPI_FIFO

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DSPI_FIFO
Serial Peripheral Interface Master/Slave with FIFO 1.07
DSPI_FIFO fully configurable master/slave device, which allows user configure polarity phase serial clock signal SCK. DSPI_FIFO allows microcontroller communicate with serial peripheral devices. also capable interprocessor communications multi-master system. serial clock line (SCK) synchronizes shifting sampling information independent serial data lines. DSPI_FIFO data simultaneously transmitted received. DSPI_FIFO technology independent design that implemented variety process technologies. DSPI_FIFO system flexible enough interface directly with numerous standard product peripherals from several manufacturers. system configured master slave device. Data rates high CLK/8. Clock control logic allows selection clock polarity choice fundamentally different clocking protocols accommodate most available synchronous serial peripheral devices. When configured master, software selects eight different rates serial clock. DSPI_FIFO automatically drive selected SSCR (Slave Select Control Register) slave select outputs (SS7O SS0O), address slave device exchange serially shifted data. Error-detection logic included
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support interprocessor communications. write-collision detector indicates when attempt made write data serial shift register while transfer progress. multiple-master mode-fault detector automatically disables DSPI_FIFO output drivers more than devices simultaneously attempts become master.
DSPI_FIFO supports modes: single transfer multi-transfer. These modes allow DSPI_FIFO interface higher performance units, which interleave their transfers between cycles execute multiple byte transfers.
DSPI_FIFO fully customizable, which means delivered exact configuration meet users' requirements. There need extra used features wasted silicon. includes fully automated testbench with complete tests allowing easy package validation each stage design flow.
APPLICATIONS
Embedded microprocessor boards Consumer professional audio/video Home automotive radio Digital multimeters
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FEATURES
CONFIGURATION
following parameters DSPI_FIFO core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
FIFO Control logic FIFO size SLAVE SELECT enable disable standard 16/64 large Number periods before starts transmission Number periods High between consecutive master transmissions. Number periods after master transmission
Master
Master Multi-master operations modes operation: mode FIFO mode slave select lines System error detection
Mode fault error Write collision error
Interrupt generation Supports speeds system clock rates generated 1/1024 system clock. Four transfer formats supported Simple interface allows easy connection microcontrollers
SETUP TIME
Slave
Slave operation modes operation: mode FIFO mode System error detection Interrupt generation Supports speeds system clock Simple interface allows easy connection microcontrollers Four transfer formats supported
SLAVE SELECT HIGH TIME SLAVE SELECT
HOLD TIME
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
Modes allows single multitransfer FIFO mode transmitter receiver each buffered with 16/64 byte FIFO's reduce number interrupts presented Optional FIFO size extension 128, Bytes Fully synthesizable, static synchronous design with internal tri-states
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LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
SYMBOL
datai(7:0) addr(7:0)
datao(7:0) rxrdy txrdy scko scken soen ss7o ss6o ss5o ss4o ss3o ss2o ss1o ss0o
scki
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
PINS DESCRIPTION
TYPE
input input input input input input input input input input input output output output output output output output output output output
DESCRIPTION
Global clock Global reset Data input Processor address lines Chip select Processor read strobe Processor write strobe clock input Master serial data input Slave serial data input Slave select Data output Interrupt request Transmitter ready output Receiver ready output clock output clock output enable Master serial data output Slave serial data output Slave output enable Slave select outputs
Upgrade from
Source Netlist Single Design Unlimited Designs
datai(7:0) addr(1:0) scki datao(7:0) txrdy rxrdy scko scken soen ss7o-ss0o
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BLOCK DIAGRAM
Shift register Read Data Buffer central element system. system single buffered transmit direction double buffered receive direction. This fact means data transmission cannot written shifter until previous transaction complete; however, received data transferred into parallel read data buffer shifter free accept second serial character. long first character read read data buffer before next serial character ready transferred, overrun condition will occur. When transfer occurs, 8-bit character shifted data while different 8-bit character simultaneously shifted second data pin. Another view this transfer that 8-bit shift register master another 8-bit shift register slave connected circular 16-bit shift register. When transfer occurs, this distributed shift register shifted eight positions; thus, characters master slave effectively exchanged.
issue interrupt CPU. FIFO will continue store bytes until full, will accept next byte. more data entering shift register will Overrun Error flag. Transmitter FIFO portion DSPI_FIFO transmits data through SO/MO soon loads byte into FIFO Master mode. Slave mode transmission started after correct edge signal. DSPI_FIFO will prevent loads FIFO currently holds (128, 256, 512) characters (depending SFCR(5) value selected FIFO size). Loading FIFO again will enabled soon next character transferred shift register. These capabilities account largely autonomous operation Control Register read written time, used configure DSPI_FIFO System. This register controls mode transmission (Master, Slave), polarity phase Clock transmission speed. Status Register (SPSR) read only register contains flags indicating completion transfer occurrence system errors. flags automatically when corresponding event occur cleared software sequence. Slave Select Control Register configures which slave select output should driven while master transfer. Contents SSCR register automatically assigned SS7OSS0O pins when DSPI_FIFO master transmission starts. Clock Logic Software select four combinations serial clock (SCK) phase polarity using bits control register (SPCR). clock polarity specified CPOL control bit, which selects active high active clock significant effect transfer format. clock phase (CPHA) control selects fundamentally different transfer formats. clock phase polarity should identical master device communicating slave device. some cases, phase polarity changed between transfers allow master device communicate with peripheral slaves having different requirements. flexibility system
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8-Bit Shift Register
TX-FIFO
RX-FIFO
addr(2:0)
Divider ÷1024
CPHA CPOL
Clock Logic
scko scki
Ctrl. Reg.
scken soen
Status Reg.
datao(7:0)
Controller
Ctrl. Reg.
datai(7:0)
Read buffer FIFO Ctrl. Reg.
ss7o ss6o ss5o ss4o ss3o ss2o ss1o ss0o
Receiver FIFO FIFO (128, 256, 512) levels deep, receives data until number bytes FIFO equals selected interrupt trigger level. that time interrupt enabled, DSPI_FIFO will
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DSPI_FIFO allows direct interface almost existing synchronous serial peripheral. Controller manages Master/Slave operation controls transmission. Controller manages transmission speed format (Phase polarity). Controller also responsible generating interrupt request detection transmission errors.
PERFORMANCE
following table gives survey about Core performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade CYCLONE CYCLONE2 STRATIX STRATIX2 STRATIXGX APEX2A APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE Core performance ALTERA® devices Device
Transfer Formats
Software select four combinations serial clock (SCK) phase polarity using bits control register (SPCR). clock polarity specified CPOL control bit, which selects active high active clock significant effect transfer format. clock phase (CPHA) control selects fundamentally different transfer formats. clock phase polarity should identical master device communicating slave device. some cases, phase polarity changed between transfers allow master device communicate with peripheral slaves having different requirements. flexibility system DSPI_FIFO allows direct interface almost existing synchronous serial peripheral.
L=0) L=1)
L=0) L=1)
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Distributors: Please check
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Copyright 1999-2007 Digital Core Design. Rights Reserved.

Serial Peripheral Interface Master/Slave with FIFO 1.07 DSPI_FIFO

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