High Performance Configurable 8-bit RISC Microcontroller 2.15 DRP

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High Performance Configurable 8-bit RISC Microcontroller 2.15 DRP

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DRPIC166X
High Performance Configurable 8-bit RISC Microcontroller 2.15
DRPIC166X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast (typically onchip) dual ported memory. core been designed with special concern about power consumption. DRPIC166X soft core softwarecompatible with industry standard PIC16C6X. implements enhanced Harvard architecture (i.e. separate instruction data memories) with independent address data buses. program memory 8-bit dual port data memory allow instruction fetch data operations occur simultaneously. advantage this architecture that instruction fetch memory transfers overlapped multi stage pipeline, that next instruction fetched from program memory while current instruction executed with data from data memory. DRPIC166X architecture times faster compared standard architecture. most instructions executed within system clock period, except instructions which directly operates program counter (GOTO, CALL, RETURN), this situation require pipeline cleared subsequently refilled. This operation takes additional clock cycle. DRPIC166X Microcontroller fits perfectly applications ranging from highAll trademarks mentioned this document trademarks their respective owners.
speed automotive appliance motor control low-power remote transmitters/receivers, pointing devices telecom processors. Built-in power save mode make this perfect applications where power consumption critical. DRPIC166X delivered with fully automated testbench complete tests allowing easy package validation each stage design flow
FEATURES
Software compatible with industry standard PIC16C6X Pipelined Harvard architecture times faster compared original implementation wide instructions bytes internal Data Memory bytes Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with internal tri-states Technology Code independent Source
virtual clock frequency 0.18u technological process
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PERIPHERALS
Four ports
Four 8-bit corresponding TRIS registers Interrupt feature PORTB(7:4) change
Program Counter (PC) Program Memory Data Memory Special Function Registers (SFRs) Hardware Stack Stack Pointer Hardware execution breakpoints Program Memory Data Memory Special Function Registers (SFRs) Hardware breakpoints activated certain Program address (PC) Address write into memory Address read from memory Address write into memory required data Address read from memory required data Three wire communication interface
Timer
8-bit timer/counter Readable Writable 8-bit software programmable prescaler Internal external clock select Interrupt generation timer overflow Edge select external clock
Timer
16-bit timer/counter 3-bit prescaler Internal external clock select Interrupt generation timer overflow
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL,
Timer
8-bit timer with prescaler
Compare-Capture-PWM
Compare/Capture operations 10-bit resolution output
USART
Asynchronous full duplex Synchronous half duplex Master/Slave
Watchdog Timer
Configurable Time period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input
Interrupt Controller
Seven individually maskable Interrupt sources external interrupts Port B[7:4] change Five internal interrupts TIMERS USART
Verilog source code called
Source
Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
DoCDdebug unit
Processor execution control Halt Step into instruction Skip instruction Read-write processor contents
Unlimited Designs license
Source Netlist
Upgrade from
Single Design Unlimited Designs Source Netlist http://www.dcd.pl
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
SYMBOL
clkwdt mclr prgdata(13:0) ramdatai(7:0) prgaddr(15:0) ramdatao(7:0) rdaddr(8:0) wraddr(8:0) ramwe ramoe sleep
t0cki t1cki ccp1i rxdi txcki portai(7:0) portbi(7:0) portci(7:0) portdi(7:0)
ccp1o rxdo txcko portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) trisa(7:0) trisb(7:0) trisc(7:0) trisd(7:0)
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
CONFIGURATION
following parameters DRPIC166X core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
Number hardware stack levels 1-16 default synchronous asynchronous used unused used width unused used unused used unused used unused used unused used unused
clkwdt mclr prgdata[13:0] ramdati[7:0] t0cki t1cki ccp1i rxdti txcki portxi[7:0] docddatai
docddatai
docddatao docdclk prgdatao(13:0) DoCD Interface prgwe
PINS DESCRIPTION
TYPE
input input input input input input input input input input input input input input
Memories type SLEEP mode WATCHDOG Timer Timer system Compare Capture USART PORTS A,B,C,D DoCD
DESCRIPTION
Global clock Watchdog clock Global reset Power Reset User reset Data from program memory Data from int. data memory External interrupt Timer input Timer input Compare Capture channel input USART serial data input USART serial clock input Port input DoCDDebugger input
Debug Unit
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prgaddr[15:0] ramdatao[7:0] rdaddr[8:0] wraddr[8:0] ramwe ramoe sleep ccp1o txcko rxdto portxo[7:0] trisx[7:0] docddatao docdclk prgdatao[13:0] prgwe
output Program memory address output Data internal data memory output read address output write address output Data memory write output Data memory output enable Output Sleep signal Output Compare Capture channel output Output USART serial clock output Output USART serial data output Output Port outputs Output Ports data direction pins Output DoCDDebugger data output Output DoCD
Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed file select register FSR. Reading INDF register indirectly will produce 00h. Writing INDF register indirectly results nooperation. effective 9-bit address obtained concatenating (STATUS) 8-bit register.
Hardware Stack
Clock line
Output Program Memory data output Output Program Memory write enable
mclr sleep prgdata prgaddr
Control Unit
Controller
ramdatai ramdatao rdaddr wraddr ramwe ramoe portai portbi portci portdi portao portbo portco portdo trisa trisb trisc trisd ccp1i ccp1o rxdi txcki rxdo txcko docddatai docddatao docdclk prgdatao prgwe
BLOCK DIAGRAM
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. This module contains work register Status register. Control Unit performs core synchronization data flow control. This module manages execution instructions. Performs decode control functions other blocks. contains program counter (PC) hardware stack. Hardware Stack it's configurable hardware stack. stack space part either program data space stack pointer readable writable. pushed onto stack when CALL instruction executed interrupt causes branch. stack popped while RETURN, RETFIE RETLW instruction execution. stack operates circular buffer. This means that after stack been pushed eight times, ninth push overwrites value that stored from first push. Controller performs interface functions between Data memory DRPIC166X internal logic. assures correct Data Memory addressing data transfers. DRPIC166X supports addressing modes: direct indirect. Direct Addressing 9-bit direct address computed from RP(1:0) bits (STATUS) least significant bits instruction word.
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Interrupt Controller
t0cki
Timer
Ports
t1cki
Timer
Timer
Compare/ Capture/
clkwdt
Watchdog Timer
USART
DoCDDebugger
Timer Main system's timer prescaler. This timer operates modes: 8-bit timer 8-bit counter. "timer mode", timer registers incremented every periods. When prescaler assigned into TIMER prescale ration divided 256. "counter mode" timer register incremented every falling rising edge T0CKI pin, dependent T0SE OPTION register.
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Timer Timer 16-bit timer consisted 8-bit registers (TMR1H TMR1L). Timer operate either timer incremented every clock period Counter incremented rising edge T1CKI input pin. Timer1 interrupt generated timer overflow. Timer 8-bit Timer with prescaler postscaler. Timer2 suitable time-base. Timer2 module 8-bit period register, PR2. Timer2 incremented until matches then resets next increment cycle. match output TMR2 register goes through 4-bit postscaler generate TMR2 interrupt. Interrupt Controller Interrupt Controller module responsible interrupt manage system external internal interrupt sources. contains interrupt related registers called INTCON, PIE1, PIR1. There seven individually maskable interrupt sources:
configured input (output drivers into High Impedance). CCP/PWM module contains 16bit register which operate 16-bit capture register, 16-bit compare register, master/slave duty cycle register. Watchdog Timer- it's free running timer. clock input separate from system clock. means that will even system clock stopped execution SLEEP instruction. During normal operation, time-out generates Watchdog reset. device SLEEP mode time-out causes device wake-up continue with normal operation. USART Universal Synchronous Asynchronous Receiver Transmitter module also known Serial Communication Interface (SCI). USART configured full duplex asynchronous system that communicate with peripheral devices configured half duplex synchronous system (Master Slave). DoCDDebug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other on-chip debuggers DoCDprovides non-intrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
external interrupts pin, PORTB change (pins B7:B4) Five internal interrupts Timers USART, CCP1
interrupt control register INTCON PIR1 records individual interrupt requests flag bits. global interrupt enable bit, Peripheral interrupts enable bit, enables unmasked interrupts. Each interrupt source individual enable bit, which enable disable corresponding interrupt. When interrupt responded cleared disable further interrupt, return address pushed into stack loaded with 0004h. interrupt flag bits must cleared software before re-enabling interrupts. Ports Block contains DRPIC166X's general purpose ports data direction registers (TRIS). DRPIC166X four 8bit full bi-directional ports PORT PORT PORT PORT Each port's individually accessed addressable instructions. Read write accesses port performed their corresponding SFR's PORTA, PORTB, PORTC, PORTD. reading instruction always reads status Port pins. Writing instructions always write into Port latches. Each port's corresponding TRISA, registers. When TRIS register this means that corresponding port
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OPTIONAL PERIPHERALS
There also available optional peripherals, included presented DRPIC166X Microcontroller Core. optional peripherals, implemented microcontroller core upon customer request. Master Slave Serial Peripheral Interface
Supports speeds system clock Mode fault error Write collision error Software selectable polarity phase
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE 1654 CYCLONE 1654 STRATIX 1655 STRATIX 1401 STRATIX 1655 APEX 1695 APEX20KC 1695 APEX20KE 1695 APEX20K 1695 ACEX1K 1695 FLEX10KE 1695 Core performance ALTERA® devices Device
serial clock
System errors detection Allows operation from wide range system
clock frequencies (build-in 5-bit timer)
Interrupt generation
Area utilized each unit DRPIC166X core vendor specific technologies summarized table below.
Component
[LC]
controller Master
7-bit 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration synchronization User defined timings lines Wide range system clock frequencies Interrupt generation
Area
[FFs]
CPU* Timer Timer Timer USART CCP1 Watchdog Timer Ports Total area
*CPU consisted ALU, Control Unit, Controller, Hardware Stack, External Interrupt Controller, Extended interrupt controller,(512 Bytes program memory)
controller Slave
NORMAL speed FAST speed HIGH speed 3400 Wide range system clock frequencies User defined data setup time lines Interrupt generation
Core components area utilization
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IMPROVEMENT
Most instruction DRPIC166X executed within period, except program branches that require periods. table below shows sample instructions execution times:
Mnemonic DRPIC166X operands (CLK cycles) ADDWF ANDWF DECFSZ 1(2)1 INCFSZ 1(2)1 BTFSC 1(2)1 BTFSS 1(2)1 CALL GOTO RETFIE RETLW RETURN
PIC16C6X
(CLK cycles)
Impr.
4(8)1 4(8)1 4(8)1 4(8)1
number clock case that result operation
DFPIC&DRPIC FAMILY family DFPICXX DRPICXX Cores combine high-performance, cost, small compact size, offering best price/performance ratio Market. DCD's Cores dedicated cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security telecommunication applications. DCD's DFPICXX DRPICXX Cores family contains four 8-bit microcontroller Cores best meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, DRPIC1655X DRPIC166X single cycle microcontrollers with 14-bit program word. three microcontroller cores binary compatible with widely accepted PIC16C5X PIC16CXXX. They employ modified RISC architecture four times faster than original ones. DFPICXXX DRPICXX Cores written pure VHDL/VERILOG languages which make them technologically independent. DFPICXX DRPICXX family members supports power saving SLEEP mode allows user configure watchdog time-out period number hardware stack levels. DFPICXX DRPICXX fully customized according customer needs.
Program Memory space Data Memory space Program word length Number instructions External interrupts Internal Interrupts Levels hardware stack Wake port change Watchdog Timer
Sleep Mode
Speed rate
Ports
Design
DFPIC165X DFPIC1655X DRPIC1655X DRPIC166X
Optional DFPIC DRPIC family High Performance Microcontroller Cores
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Size (gate)
DoCDDebugger
Timer
Timer
Timer
USART
CCP1
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinfo@dcd.pl tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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High Performance Configurable 8-bit RISC Microcontroller 2.15 DRP

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