Pipelined High Performance 8-bit Microcontroller 4.02 DP80390CPU

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Pipelined High Performance 8-bit Microcontroller 4.02 DP80390CPU

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DP80390CPU
Pipelined High Performance 8-bit Microcontroller 4.02
DP80390CPU ultra high performance, speed optimized soft core singlechip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. supports linear code linear data spaces. core been designed with special concern about performance power consumption ratio. This ratio extended advanced power management unit PMU. DP80390CPU soft core 100% binarycompatible with industry standard 80390 8051 8-bit microcontroller. There configurations DP80390CPU: Harward where internal data program buses separated, Neumann with common program external data bus. DP80390CPU Pipelined RISC architecture times faster compared standard architecture executes 85-200 million instructions second. This performance also exploited great advantage power applications where core clocked over times more slowly than original implementation performance penalty. DP80390CPU delivered with fully automated testbench complete tests allowing easy package validation each stage design flow.
FEATURES
100% software compatible with industry standard 80390 8051
LARGE mode 8051 instruction FLAT mode 80390 instruction
Pipelined RISC architecture enables execute instructions times faster compared standard 8051 times faster multiplication times faster addition bytes internal (on-chip) Data Memory bytes linear Program Memory
internal (on-chip) Program Memory external (off-chip) Program Memory
bytes external (off-chip) Data Memory User programmable Program Memory Wait States solution wide range memories speed User programmable External Data Memory Wait States solution wide range memories speed De-multiplexed Address/Data allow easy connection memory Dedicated signal Program Memory writes.
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Interface additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking internal tri-states Scan test ready virtual clock frequency 0.25u technological process
CONFIGURATION
following parameters DP80390CPU core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
Internal Program Memory type Internal Program Memory size Internal Program Memory size Internal Program Memory fixed size synchronous asynchronous 64kB 64kB true false subroutines location
PERIPHERALS
DoCDdebug unit
Processor execution control Halt Step into instruction Skip instruction Read-write processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Code execution breakpoints real-time breakpoint unlimited number real-time OPCODE breakpoints Hardware execution watch-point Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware watch-points activated certain address write into memory address read from memory address write into memory required data address read from memory required data Unlimited number software watch-points Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Unlimited number software breakpoints Program Memory(PC) Automatic adjustment debug data transfer
Interrupts Power Management Mode Stop mode DoCDdebug unit
used unused used unused used unused
Besides mentioned above parameters available peripherals external interrupts excluded from core changing appropriate constants package file.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
speed rate between Silicon
JTAG Communication interface
Power Management Unit
Power management mode Switchback feature Stop mode
Interrupt Controller
priority levels external interrupt sources
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
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LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows using Core single FPGA bitstream ASIC implementation. also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time limitations. Single Design license
VHDL, Verilog source code called Sour-
DESIGN FEATURES
PROGRAM MEMORY: DP80390 soft core dedicated operation with Internal External Program Memory. maximal linear size equal Internal Program Memory implemented
located address range between
0x0000 (ROMsize-1)
located address range between
External Program Memory implemented located address range between ROMsize excluding area occupied RAMsize. INTERNAL DATA MEMORY: DP80390CPU address Internal Data Memory bytes Internal Data Memory implemented Single-Port synchronous RAM. EXTERNAL DATA MEMORY: DP80390CPU soft core address External Data Memory. Extra (Data Pointer eXtended) register used segments swapping. USER SPECIAL FUNCTION REGISTERS: External (user) Special Function Registers (ESFRs) added DP80390CPU design. ESFRs memory mapped into Direct Memory between addresses 0x80 0xFF same manner core SFRs occupy address that occupied core SFR. WAIT STATES SUPPORT: DP80390CPU soft core dedicated operation with wide range Program Data memories. Slow Program External Data memory assert memory Wait signal hold activity.
(64kB-RAMsize) 0xFFFF
Encrypted, plain text EDIF called Netlist
Unlimited Designs license
Source Netlist
Upgrade from
Netlist Source Single Design Unlimited Designs
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SYMBOL
prgromdata(7:0) prgramdata(7:0) prgaddr(15:0) prgdatao(7:0) prgramwr xaddr(23:0) xdatao(7:0) xdataz xprgrd xprgwr xdatard xdatawr
sxdmadd(15:0) sxdmdatao(7:0) sxdmwe sxdmoe
BLOCK DIAGRAM
Opcode decoder prgramdata(7:0) prgromdata(7:0) prgaddr(15:0) prgdatao(7:0) prgramwr xaddr(23:0) xdatao(7:0) xdatai(7:0) xdataz ready xprgrd xprgwr xdatard xdatawr
xdatai(7:0) ready iprgromsize(2:0) iprgramsize(2:0)
Program memory interface SXDM interface External memory
interface
sxdmaddr sxdmdatao sxdmdatai sxdmoe sxdmwe int0 int1
sxdmxdatai(7:0)
Interrupt controller
ramdatai(7:0)
iprgromsize(2:0) iprgramsize(2:0) ramaddr(7:0) ramdatao(7:0) ramdatai(7:0) ramwe ramoe sfraddr(6:0) sfrdatao(7:0) sfrdatao(7:0) sfroe sfrwe reset
Control Unit
Power Management Unit
stop rtck coderun debugacs
ramaddr(7:0) ramdatao(7:0) ramwe ramoe sfrdatai(7:0) sfraddr(6:0) sfrdatao(7:0) sfroe sfrwe stop reset rtck coderun debugacs rsto
Internal data memory interface
DoCDDebug Unit
User SFR's interface
int0 int1
PINS DESCRIPTION
reset port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] iprgramsize[2:0] iprgromsize[2:0] prgramdata[7:0] prgromdata[7:0] sxdmdatai[7:0] ready ramdatai[7:0] sfrdatai[7:0] int0 int1
TYPE
input input input input input input input input input input input input input input input input input input input
DESCRIPTION
Global clock Global reset Port input Port input Port input Port input Size on-chip CODE Size on-chip CODE Data from int. prog. memory Data from int. prog. memory Data from sync external data memory (SXDM) External memory data ready Data from internal data memory Data from user SFR's External interrupt External interrupt DoCDTAP data input DoCDTAP clock input DoCDTAP mode select input
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rsto port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] prgaddr[15:0] prgdatao[7:0] prgramwr sxdmaddr[15:0] sxdmdatao[7:0] sxdmoe sxdmwe xaddr[23:0] xdatao[7:0] xdataz xprgrd xprgwr xdatard xdatawr ramaddr[7:0] ramdatao[7:0] ramoe ramwe sfraddr[6:0] sfrdatao[7:0] sfroe sfrwe rtck debugacs coderun stop
TYPE
DESCRIPTION
output Reset output output Port output output Port output output Port output output Port output output Internal program memory address output Data internal program memory output Internal program memory write output Sync XDATA memory address (SXDM) output Data Sync XDATA memory (SXDM) output Sync XDATA memory read (SXDM) output Sync XDATA memory write (SXDM) output Address external memories output Data external memories output Turn xdata into state output External program memory read output External program memory write output External data memory read output External data memory write output Internal Data Memory address output Data internal data memory output Internal data memory output enable output Internal data memory write enable output Address user SFR's output Data user SFR's output User SFR's read enable output User SFR's write enable output DoCDTAP data output output DoCDreturn clock line output DoCDaccessing data output executing instruction output Power management mode indicator output Stop mode indicator
Program Memory Interface Contains Program Counter (PC) related logic. performs instructions code fetching. Program Memory also written. This feature allows usage small boot loader loading program into RAM, EPROM FLASH EEPROM storage UART, SPI, DoCDmodule. External Memory Interface Contains memory access related registers such Data Page High (DPH), Data Page (DPL) Data Pointer eXtended (DPX) registers. performs external Program Data Memory addressing data transfers. Program fetch cycle length programmed user. This feature called Program Memory Wait States, allows core work with different speed program memories. Synchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic allowing fast access synchronous memory devices. performs external Data Memory addressing data transfers. This memory used store large variables frequently accessed CPU, improving overall performance application. Internal Data Memory Interface Internal Data Memory interface controls access into internal bytes memory. contains 8-bit Stack Pointer (SP) register related logic. User SFRs Interface Special Function Registers interface controls access special registers. contains standard used defined registers related logic. User defined external devices quickly accessed (read, written, modified) using direct addressing mode instructions. Interrupt Controller Interrupt control module responsible interrupt manage system external internal interrupt sources. contains interrupt related registers such Interrupt Enable (IE), Interrupt Priority (IP) (TCON) registers. Power Management Unit Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic stop clocking (Stop mode) core lower clock frequency (Power Management Mode) significantly reduce power consumption. Switchback feature allows UARTs, interrupts processed full speed mode enabled. very desired when
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UNITS SUMMARY
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. contains accumulator (ACC), Program Status Word (PSW), registers related logic such arithmetic unit, logic unit, multiplier divider. Opcode Decoder Performs instruction opcode decoding control functions other blocks. Control Unit Performs core synchronization data flow control. This module directly connected Opcode Decoder manages execution microcontroller tasks.
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microcontroller planned portable power critical applications. DoCDDebug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other onchip debuggers DoCDprovides non-intrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. additional pins CODERUN, DEBUGACS indicate sate debugger CPU. CODERUN active when executing instruction. DEBUGACS active when access performed DoCDdebugger. DoCDsystem includes JTAG interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
tions second (many instructions executed clock cycle). Off-chip Program Memory located address space between 60kB, above typically used main code constants. This part code usually implemented ROM, SRAM FLASH device. Because relatively long access time program code executed from mentioned above devices must fetched with additional Wait-States. Number required Wait-States depends memory access time DP80390CPU clock frequency. most cases proper number WaitStates cycles between 2-5. READY also dynamically modulated e.g. SDRAM controller.
0x7FFFFF
chip Memory
(implemented ROM, SRAM FLASH)
0x00FFFF 0x00F000
chip Memory
(implemented RAM)
chip Memory
(implemented ROM, SRAM FLASH)
0x000400 0x000000
On-chip Memory
(implemented ROM)
PROGRAM CODE SPACE IMPLEMENTATION
figure below shows example Program Memory space implementation systems with DP80390CPU Microcontroller core. On-chip Program Memory located address space between typically used BOOT code with system initialization functions. This part code typically implemented ROM. On-chip Program Memory located address space between 60kB 64kB typically used timing critical part code e.g. interrupt subroutines, arithmetic functions etc. This part code typically implemented loaded BOOT code during initialization phase from Off-chip memory through RS232 interface from external device. From mentioned above spaces program code executed without wait-states achieve performance million instrucAll trademarks mentioned this document trademarks their respective owners.
figure below shows typical Program Memories connections system with DP80390CPU Microcontroller core.
prgramdatai prgdatao prgramwr prgaddr prgromdata ASIC FPGA chip Off-chip Memory
(implemented FLASH, SRAM) Wait-State access
On-chip Memory
(implemented RAM) Wait-State access
On-chip Memory
(implemented ROM) Wait-State access
DP80390CPU
xdatai xdatao xaddr xprgrd xprgwr
ready
Wait-States manager
described above implementation should treated example. Program Memory
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spaces fully configurable. timing-critical applications whole program code implemented on-chip (or) executed without Wait-States, some other applications whole program code implemented off-chip FLASH executed with required number Wait-State cycles.
PERFORMANCE
following tables give survey about Core area performance Programmable Logic Devices after Place Route (CPU features peripherals have been included):
Device FLEX10KE ACEX1K APEX20K APEX20KE APEX20KC APEX-II MERCURY CYCLONE CYCLONE-II STRATIX STRATIX-II Speed grade Fmax
Core performance ALTERA® devices
user most important application speed improvement. most commonly used arithmetic functions theirs improvement shown table below. Improvement computed {80C51 clock periods} divided {DP80390CPU clock periods} required execute identical function. More details available core documentation.
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 9,00 9,00 9,00 12,00 9,00 9,00 9,00 12,00 16,00 9,60 12,00 12,00 13,60 12,00 12,00 12,60 11,12
Dhrystone Benchmark Version used measure Core performance. following table gives survey about DP80390CPU performance terms Dhrystone/sec MIPS rating.
Clock frequency 80C51 80C310 DP80390CPU STRATIX-II Device Target Dhry/sec (VAX MIPS) (0.153) 1550 (0.882) 26220 (14.924)
Core performance terms Dhrystones
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27000 24000 21000 18000 15000 12000 9000 6000 3000
80C51 (12MHz)
26220
1550
80C310 (33MHz)
DP80390CPU (150MHz)
Area utilized each unit DP80390CPU core vendor specific technologies summarized table below.
Component CPU* Interrupt Controller Power Management Unit Total area Area
[LC] [FFs]
1790 1900
*CPU consisted ALU, Opcode Decoder, Control Unit, Program Internal External Memory Interfaces, User SFRs Interface
Core components area utilization technologies except STRATIX-II
Component CPU* Interrupt Controller Power Management Unit Total area
Area
[LC] [FFs]
1380 1465
*CPU consisted ALU, Opcode Decoder, Control Unit, Program Internal External Memory Interfaces, User SFRs Interface
Core components area utilization STRATIX-II
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main features each DP80390 family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Architecture speed grade Program Memory space Stack space size on-chip on-chip Power Management Unit
Internal Data Memory space External Data Memory space External Data Program Memory Wait States
Compare/Capture
Interrupt sources
Interface additional SFRs
Timer/Counters
Interrupt levels
Master Controller Slave Controller
Data Pointers
Design
DP80390CPU DP80390 DP80390XP
DP80390 family High Performance Microcontroller Cores
main features each DP8051 family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Architecture speed grade Program Memory space Stack space size on-chip on-chip Power Management Unit
Internal Data Memory space External Data Memory space External Data Program Memory Wait States
Compare/Capture
Interrupt sources
Interface additional SFRs
Timer/Counters
Interrupt levels
Master Controller Slave Controller
Data Pointers
Design
off-chip
DP8051CPU DP8051 DP8051XP
DP8051 family High Performance Microcontroller Cores
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Fixed Point Coprocessor Floating Point Coprocessor
Watchdog
Ports
UART
Fixed Point Coprocessor Floating Point Coprocessor
Watchdog
Ports
off-chip
UART
CONTACTS
modification special request contact DCD. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
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Pipelined High Performance 8-bit Microcontroller 4.02 DP80390CPU

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