DMAC hardware implementation media access control protocol defined IEE

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DMAC hardware implementation media access control protocol defined IEE

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Media Access Controller 2.07
DMAC hardware implementation media access control protocol defined IEEE standard. DMAC cooperation with external device enables network functionality design. capable transmitting receiving Ethernet frames from network. Half full duplex modes supported, well Mbit/s speed. core able work with wide range processors: data bus, with little endian byte order format. Design technology independent thus implemented variety process technologies. This core strictly conforms IEEE 802.3 standard. Supports full half duplex operation Mbps Mbps CRC-32 algorithm calculates nibble time, automatic generation checking, able capture frames with errors required Lite design, small gate count fast operation Programmable fixed address Promiscuous mode support Dynamic configuration management interface Receive FIFO able store many messages time Allows operation from wide range input clock frequencies Fully synthesizable Static synchronous design with positive edge clocking synchronous reset internal tri-states Scan test ready
FEATURES
Conforms IEEE 802.3-2002 specification 8/16/32-bit slave interface with little endianess Simple interface allows easy connection Narrow address with indirect interface transmit receive data dual port memories Supports 10BASE-T 100BASETX/FX IEEE 802.3 compliant PHYs Media Independent Interface (MII) connection external 10/100 Mbps transceivers
APPLICATIONS
Embedded microprocessor boards Networking devices (Network Interface Cards, routers, switches) Communications systems
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
rdcs wrcs
PINS DESCRIPTION
TYPE
input input input input input input input input input
DESCRIPTION
Global clock Global reset Read chip select Write chip select Read data strobe Write data strobe Host read address Host write address Host byte enable Host output data DPRAM data output DPRAM data output Ethernet receive data Ethernet receive data valid Ethernet receive error Ethernet receive clock Ethernet transmit clock Ethernet carrier sense Ethernet collision detection Management data input DoCD debugger input
rdaddr(4:0) wraddr(4:0) be(3:0)
datai(31:0) qmr(31:0) qmt(31:0)
input input input input input input input input input input input input
rxdata(3:0) rxdv rxer rxclk txclk docdbusctrl datao(31:0) dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt txer txen txdata(3:0) mdoe rdcs wrcs
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
SYMBOL
rdcs wrcs qmt(31:0) be(3:0)2 datai(31:0)1 rdaddr(4:0) wraddr(4:0) qmr(31:0) rxdata(3:0) rxdv rxer rxclk txclk docdbusctrl dmt(31:0) waddrmt(8:0) raddrmt(8:0) enrmt enwmt
output Host input data output Interrupt signal output DPRAM data input output DPRAM write address output DPRAM read address output DPRAM read enable output DPRAM write enable output DPRAM data input output DPRAM write address output DPRAM read address output DPRAM read enable output DPRAM write enable output Ethernet transmit error output Ethernet transmit enable output Ethernet transmit data output Management clock output Management data output output Management data output enable input input input input Global clock Global reset Read chip select Write chip select
datao(31:0)1 dmr(31:0) waddrmr(8:0) raddrmr(8:0) enrmr enwmr txdata(3:0) txen txer mdoe
data configured depends processor's size byte enable (be) size accordingly data size
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
BLOCK DIAGRAM
Figure below shows DMAC Core block diagram.
pins txclk txen txer txdata(3:0) mdoe rxclk rxdv rxer rxdata(3:0)
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Device STRATIX CYCLONE STRATIX STRATIX CYCLONE APEX APEX20KC APEX20KE APEX20K Speed grade Logic Cells 1222 1255 1255 1254 1622 1622 1622 1622 Fmax [MHz] rxclk txclk
Transmit module
interface
Synchronization logic
Control logic
Receive module
FIFO
docdbusctrl rdcs wrcs be(3:0) rdaddr(4:0) wraddr(4:0) datai(31:0) datao(31:0)
pins
Transmit module Performs transmit management functions, sends frames Ethernet medium. Receive module responsible receiving frames from Ethernet. Provides necessary functions frame decapsulation, checking, address recognizing error detection. Synchronization logic There clock domains DMAC core. This module performs synchronization between these. FIFO interfaces Interfaces external dual port memories used DMAC core store received transmitted frames. Control logic This module provides interface CPU/BUS. exchanges data control logic with transmit receive modules, thus controls these perform transmit receive operations. Station Management entity provides capability communicate with simple serial management interface.
Core performance ALTERA® devices
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

DMAC hardware implementation media access control protocol defined IEE

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