Interface Slave Base version 1.15 two-wire, bi-directional serial

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Interface Slave Base version 1.15 two-wire, bi-directional serial

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DI2CSB
Interface Slave Base version 1.15
two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CSB provides interface between passive target device e.g. memory, display, pressure sensors etc. bus. works slave receiver transmitter depending working mode determined master device. Very simple interface, composed with read, write data signals, allows easy connection target devices. core doesn't required programming ready work after power up/reset. read, write, burst read, burst write repeated start transmissions automatically recognized core. core incorporates features required specification. DI2CSB supports following transmission modes: Standard, Fast High Speed. Support reads, writes, burst reads, burst writes, repeated start 7-bit addressing programming required Simple interface allows easy connection target device e.g. memory, display, pressure sensors etc. Fully synthesizable Static synchronous design with positive edge clocking synchronous reset internal tri-states Scan test ready
APPLICATIONS
Embedded microprocessor boards Consumer professional audio/video Home automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems
FEATURES
Conforms v.2.1 specification Slave operation
Slave transmitter Slave receiver
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros
http://www.dcd.pl
Supports transmission speed modes
Standard kb/s) Fast kb/s) High Speed Mb/s)
Allows operation from wide range input clock frequencies
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
SYMBOL
datai(7:0) datao(7:0) scli sdai sdao
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
PINS DESCRIPTION
datai(7:0) scli sdai datao(7:0) sdao
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
TYPE
input input input input input output output output output
DESCRIPTION
Global clock Global reset Data from target device clock line (input) data line (input) Data target device Write strobe target device Read strobe target device data line (output)
BLOCK DIAGRAM
Figure below shows DI2CSB Core block diagram. Target device Interface Performs interface functions between DI2CSB internal blocks target device. Allows easy connection core passive devices e.g. memory, display, pressure sensors, devices etc.
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
datai(7:0) datao(7:0)
Receive Data Target device Interface Send Data Shift Register
Input Filter Output Register address detection
sdai
sdao
Upgrade from
Source Netlist Single Design Unlimited Designs
Control Logic
Synchronization Logic
Input Filter
scli
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Control Logic Manages execution commands sent interface. Synchronizes internal data flow. Shift Register Controls line, performs data address shifts during data transmission reception. Input Filter Performs spike filtering. Synchronization Logic Synchronizes data address shifts during data transmission reception. SCLI spikes filtered this unit.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade MERCURY STRATIX CYCLONE APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE 7000AE 3000A Core performance ALTERA® devices Device
main features each Digital Core Design compliant cores have been summarized table below. gives briefly member characterization helping user select most suitable Core application.
High-speed mode 10-bit addressing User defined timing Master operation Interrupt generation Clock synchronization specification version 7-bit addressing Slave operation Standard mode
Passive device interface
interface
DI2CM DI2CS DI2CSB
Arbitration
Design
cores summary table
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Spike filtering
Fast mode
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

Interface Slave Base version 1.15 two-wire, bi-directional serial

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