Interface Master/Slave 1.01 two-wire, bi-directional serial that

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DI2CMS
Interface Master/Slave 1.01
two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CMS core provides interface between microprocessor microcontroller bus. work master slave transmitter/receiver depending working mode determined microprocessor/microcontroller. DI2CMS core incorporates features required latest specification including clock synchronization, arbitration, multi-master systems High-speed transmission mode. DI2CMS supports transmission speed modes. Built-in timer allows operation from wide range frequencies. DI2CMS technology independent VHDL VERILOG design that implemented variety process technologies fully customized accordingly customer needs. DI2CMS delivered with fully automated testbench complete tests allowing easy package validation each stage design flow.
Support transmission speeds
Standard kb/s) Fast kb/s) High Speed Mb/s)
Arbitration clock synchronization Support multi-master systems Support both 7-bit 10-bit addressing formats Build-in 8-bit timer data transfers speed adjusting User-defined timing (data setup, start setup, start hold, etc.)
Slave mode
Slave operation
Slave transmitter Slave receiver
Supports transmission speed modes
Standard kb/s) Fast kb/s) High Speed Mb/s)
Allows operation from wide range input clock frequencies User-defined data setup time
FEATURES
Conforms v.2.1 specification Master mode
Master operation
Master transmitter Master receiver
Simple interface allows easy connection microprocessor/microcontroller devices Interrupt generation Fully synthesizable Static synchronous design with positive edge clocking synchronous reset
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
internal tri-states Scan test ready
tion except Year license where time limited months.
APPLICATIONS
Embedded microprocessor boards Consumer professional audio/video Home automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
Upgrade from
Source Netlist Single Design Unlimited Designs
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restricAll trademarks mentioned this document trademarks their respective owners. http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
SYMBOL
datai(7:0) address(2:0) sclhs sclo sdao datao(7:0)
BLOCK DIAGRAM
Figure below shows DI2CMS Core block diagram.
address(2:0) datai(7:0) datao(7:0)
Slave Address Shift Register Send Data Receive Data
Input Filter Output Register
sdai
scli sdai
Interface
sdao
Control Register Status Register
Control Logic
Arbitration Logic
PINS DESCRIPTION
address(1:0) scli sdai datai(7:0) datao(7:0) sclo sclhs sdao
Timer
Clock Control Logic
Input Filter Output Register Output Register
scli sclo
TYPE
input input input input input input input input input output output output output output
DESCRIPTION
Global clock Global reset Processor address lines Chip select Processor write strobe Processor read strobe clock line (input) data line (input) Processor data (input) Processor data (output) clock line (output) High-speed clock line (output) data line (output) Processor interrupt line
sclhs
Interface Performs interface functions between DI2CMS internal blocks microprocessor. Allows easy connection core microprocessor/microcontroller system. Control Logic Manages execution commands sent interface. Synchronizes internal data flow. Shift Register Controls line, performs data address shifts during data transmission reception. Control Register Contains five control bits used performing types transmissions. Status Register Contains seven status bits that indicates state DI2CMS core. Input Filter Performs spike filtering. Clock Control Logic Performs clock synchronization, clock generation master mode, clock stretching slave mode. Arbitration Logic Performs arbitration during operations multi-master systems. Timer Allows operation from wide range input frequencies. programmed user before transmission reprogrammed change frequency.
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
IMPLEMENTATION
Figures below show typical DI2CMS implementations system with Standard/Fast High-speed devices.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade STRATIX-II CYCOLNE-II MERCURY STRATIX CYCLONE APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE 7000AE 3000A Core performance ALTERA® devices Device
sdai sdao
open drain
DI2CMS
Master /Slave device
scli sclo
open drain
sclhs
DI2CMS implementation I2C-bus system with Standard/Fast devices only
sdai sdao
open drain
DI2CMS
Master /Slave device
scli sclo
open drain
sclhs
current-source pull-up
DI2CMS implementation I2C-bus system with High-speed devices
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
main features each Digital Core Design compliant cores have been summarized table below. gives briefly member characterization helping user select most suitable Core application.
High-speed mode 10-bit addressing User defined timing Master operation Interrupt generation Clock synchronization specification version 7-bit addressing Slave operation Standard mode
Passive device interface
interface
DI2CM DI2CS DI2CSB DI2CMS
Arbitration
Design
cores summary table
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Spike filtering
Fast mode
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

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