High Performance Configurable 8-bit RISC Microcontroller 2.02 DFP

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High Performance Configurable 8-bit RISC Microcontroller 2.02 DFP

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DFPIC1655X
High Performance Configurable 8-bit RISC Microcontroller 2.02
DFPIC1655X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast memory (typically on-chip). core been designed with special concern about power consumption. DFPIC1655X software compatible with industry standard PIC16C554 PIC16C558. employs modified RISC architecture times faster than original implementation). DFPIC1655X have enhanced core features, configurable hardware stack, multiple internal external interrupt sources. separate instruction data buses allow wide instruction word with separate -bit wide data. DFPIC1655X typically achieve code compression speed improvement over other 8-bit microcontrollers their class. power-down mode SLEEP allow user reduce power consumption. User wake controller from SLEEP through several external internal interrupt reset. integrated Watchdog Timer with it's clock signal provides protection against software lock-up. DFPIC1655X Microcontroller fits perfectly applications ranging from highspeed automotive appliance motor control
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low-power remote transmitters/receivers, pointing devices telecom processors. Built-in power save mode small used area programmable devices make this perfect applications applications with space power consumption limitations. DFPIC1655X delivered with fully automated testbench complete tests allowing easy package validation each stage design flow
FEATURES
Software compatible with industry standard PIC16C55X Harvard architecture times faster compared original implementation instructions wide instruction word bytes internal Data Memory bytes Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with internal tri-states Scan test ready Technology Code independent Source
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PERIPHERALS
ports
Four 8-bit corresponding TRIS registers Interrupt feature PORTB(7:4) change
Address read from memory required data Three wire communication interface
CONFIGURATION
following parameters DFPIC1655X core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
MEMORY Type Number hardware stack levels synchronous asynchronous 1-16 default kWords default used unused used width unused used unused used unused used unused
Timer
8-bit timer/counter Readable Writable 8-bit software programmable prescaler Internal external clock select Interrupt generation timer overflow Edge select external clock
Watchdog Timer
Configurable Time period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input
Program Memory size SLEEP mode WATCHDOG Timer Timer system PORTS
DoCD Debug Unit
Interrupt Controller
Three individually maskable Interrupt sources External interrupt Timer Overflow interrupt Port B[7:4] change interrupt
DoCDdebug unit
Processor execution control Halt Step into instruction Skip instruction Read-write processor contents Program Counter (PC) Program Memory Data Memory Special Function Registers (SFRs) Hardware Stack Stack Pointer Hardware execution breakpoints Program Memory Data Memory Special Function Registers (SFRs) Hardware breakpoints activated certain Program address (PC) Address write into memory Address read from memory Address write into memory required data
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted Megafunction or/and plain text EDIF VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL, Verilog source code called Sour-
SYMBOL
clkwdt mclr prgdata(13:0) ramdatai(7:0) prgaddr(15:0) ramdatao(7:0) ramaddr(8:0) ramwe ramoe sleep portao(7:0) portbo(7:0) trisa(7:0) trisb(7:0)
intr t0cki portai(7:0) portbi(7:0)
docddatai
Encrypted, plain text EDIF called Netlist
docddatao docdclk DoCD Interface prgdatao(13:0) prgwe
Year license
Encrypted Netlist only
PINS DESCRIPTION
clkwdt mclr prgdata[13:0] ramdati[7:0] intr t0cki portax[7:0] docddatai prgaddr[15:0] ramdatao[7:0] ramaddr[8:0] ramwe ramoe sleep portxo[7:0] trisx[7:0] docddatao docdclk prgdatao[13:0] prgwe
TYPE
input input input input input input input input input input
DESCRIPTION
Global clock Watchdog clock Global reset Power Reset User reset Data from program memory Data from int. data memory External interrupt Timer input Port input DoCDDebugger input
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
output Program memory address output Data internal data memory output address output Data memory write output Data memory output enable output Sleep signal output Port output output Data direction pins Port output DoCDDebugger data output output DoCDClock line output Program Memory data output output Program Memory write enable
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BLOCK DIAGRAM
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. This module contains work register Status register. Control Unit performs core synchronization data flow control. This module manages execution instructions. Performs decode control functions other blocks. contains program counter (PC) hardware stack. Hardware Stack DFPIC1655X configurable hardware stack. stack space part either program data space stack pointer readable writable. pushed onto stack when CALL instruction executed interrupt causes branch. stack popped while RETURN, RETFIE RETLW instruction execution. stack operates circular buffer. This means that after stack been pushed eight times, ninth push overwrites value that stored from first push.
Hardware Stack
struction word. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed file select register FSR. Reading INDF register indirectly will produce 00h. Writing INDF register indirectly results no-operation. effective 9-bit address obtained concatenating (STATUS) 8-bit register. Interrupt Controller Interrupt Controller module responsible interrupt manage system external internal interrupt sources. contains interrupt related register called INTCON DFPIC1655X three interrupt sources: External interrupt TMR0 overflow interrupt PORTB change interrupt (pins B7:B4) interrupt control register INTCON records individual interrupt requests flag bits. global interrupt enable bit, enables unmasked interrupts. Each interrupt source individual enable bit, which enable disable corresponding interrupt. When interrupt responded cleared disable further interrupt, return address pushed into stack loaded with 0004h. interrupt flag bits must cleared software before reenabling interrupts. Timer Main system's timer prescaler. DFPIC1655X Timer operates modes: 8-bit timer 8-bit counter. "timer mode", timer registers incremented every periods. When prescaler assigned into TIMER prescale ration divided 256. "counter mode" timer register incremented every falling rising edge T0CKI pin, dependent T0SE OPTION register. Watchdog Timer- it's free running timer. clock input separate from system clock. means that will even system clock stopped execution SLEEP instruction. During normal operation, time-out generates Watchdog reset. device SLEEP mode time-out causes device wake-up continue with normal operation.
mclr sleep prgdata prgaddr
Control Unit
Controller
ramdatai ramdatao ramaddr ramwe ramoe
intr
Interrupt Controller Ports
t0cki
Timer
portai portbi portao portbo trisa trisb docddatai docddatao docdclk prgdatao prgwe
clkwdt
Watchdog Timer
DoCD Debugger
Controller performs interface functions between Data Memory DFPIC1655X internal logic. assures correct Data memory addressing data transfers. DFPIC1655X supports addressing modes: direct indirect. Direct Addressing 9-bit direct address computed from RP(1:0) bits (STATUS) least significant bits inAll trademarks mentioned this document trademarks their respective owners.
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Ports Block contains DFPIC1655X's general purpose ports data direction registers (TRIS). DFPIC1655X 8bit full bi-directional ports PORT PORT Read write accesses port performed their corresponding SFR's PORTA, PORTB. reading instruction always reads status Port pins. Writing instructions always write into Port latches. Each port's corresponding TRISA TRISB registers. When TRIS register this means that corresponding port configured input (output drivers into High Impedance). DoCDDebug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other on-chip debuggers DoCDprovides nonintrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE CYCLONE STRATIX STRATIX STRATIX APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE Core performance ALTERA® devices Device
IMPROVEMENT
Most instruction DFPIC1655X executed within cycles. Except conditional program memory branches case that condition branch instruction met. table below shows sample instructions execution times:
OPTIONAL MODULES
There also available optional peripherals, included presented DFPIC1655X Microcontroller Core. optional peripherals, implemented microcontroller core upon customer request. Full duplex UART Master Slave Serial Peripheral Interface Pulse Width Modulation Timer controller Master Slave
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Mnemonic DFPIC1655X operands (CLK cycles) ADDWF ANDWF DECFSZ 2(4)1 INCFSZ 2(4)1 BTFSC 2(4)1 BTFSS 2(4)1 CALL GOTO RETFIE RETLW RETURN
PIC16C554
(CLK cycles)
Impr.
4(8)1 4(8)1 4(8)1 4(8)1
number clock case that result operation
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DFPIC&DRPIC FAMILY family DFPICXX DRPICXX Cores combine high-performance, cost, small compact size, offering best price/performance ratio Market. DCD's Cores dedicated cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security telecommunication applications. DCD's DFPICXX DRPICXX Cores family contains four 8-bit microcontroller Cores best meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, DRPIC1655X DRPIC166X single cycle microcontrollers with 14-bit program word. three microcontroller cores binary compatible with widely accepted PIC16C5X PIC16CXXX. They employ modified RISC architecture four times faster than original ones. DFPICXXX DRPICXX Cores written pure VHDL/VERILOG languages which make them technologically independent. DFPICXX DRPICXX family members supports power saving SLEEP mode allows user configure watchdog time-out period number hardware stack levels. DFPICXX DRPICXX fully customized according customer needs.
Program Memory space Data Memory space Program word length Number instructions External interrupts Internal Interrupts Levels hardware stack Wake port change Watchdog Timer DoCDDebugger
Sleep Mode
Speed rate
Ports
Design
DFPIC 165X DFPIC 1655X DRPIC 1655X DRPIC 166X
Optional DFPIC DRPIC family High Performance Microcontroller Cores
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Size (gate)
Timer
Timer
Timer
USART
CCP1
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinfo@dcd.pl tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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High Performance Configurable 8-bit RISC Microcontroller 2.02 DFP

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