Floating Point Pipelined Divider Unit 2.15 DFPDIV uses pipelined

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Floating Point Pipelined Divider Unit 2.15 DFPDIV uses pipelined

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DFPDIV
Floating Point Pipelined Divider Unit 2.15
DFPDIV uses pipelined mathematics algorithm divide arguments. input numbers format according IEEE754 standard. DFPDIV supports single precision real number. Divide operation pipelined levels. Input data every clock cycle. first result appears after clock periods latency next results available each clock cycle. Full IEEE-754 precision accuracy included. Fully synthesizable, static synchronous design with internal tri-states
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
APPLICATION
Math coprocessors algorithms Embedded arithmetic coprocessor Data processing control
FEATURES
Full IEEE-754 compliance Single precision real format support Simple interface programming required levels pipeline Full accuracy precision Results available every clock Overflow, underflow invalid operation flags Fully configurable
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows using Core single FPGA bitstream ASIC http://www.dcd.pl
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2007 Digital Core Design. Rights Reserved.
tation. also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time limitations. Single Design license
VHDL, Verilog source code called
BLOCK DIAGRAM
adatai(31:0) bdatai(31:0)
Arguments Checker
Main Pipelined Unit
Result Composer
datao(31:0)
Source
Encrypted, plain text EDIF called Netlist
Unlimited Designs license
Source Netlist
Arguments Checker performs input data analyze against IEEE-754 number standard compliance. appropriate numbers information about input data classes given results Main Pipelined Unit. Main Pipelined Unit performs floating point divide function. Gives complex information about results makes final flags settings. Result Composer performs result rounding function, data alignment IEEE-754 standard, final flags setting.
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Netlist Source Single Design Unlimited Designs
SYMBOL
adatai(31:0) bdatai(31:0) datao(31:0)
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route
Speed Logic Fmax grade Cells FLEX10KE 3100 ACEX1K 3100 APEX20K 2720 APEX20KE 2720 APEX20KC 2720 APEX-II 2720 MERCURY 2780 STRATIX 2270 CYCLONE 2270 STRATIX-II 2040 Core performance ALTERA® devices Device
PINS DESCRIPTION
adatai[31:0] bdatai[31:0] datao[31:0]
TYPE
Input Input Input Input Input
DESCRIPTION
Global system clock Global system reset Enable computing data input data input
Output Data output Output Overflow flag Output Underflow flag Output Invalid result flag
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

Floating Point Pipelined Divider Unit 2.15 DFPDIV uses pipelined

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