Floating Point Arithmetic Coprocessor 2.05 DFPAU Floating Point A

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Floating Point Arithmetic Coprocessor 2.05 DFPAU Floating Point A

Datasheet Thumbnail

Top Searches for this datasheet

DFPAU
Floating Point Arithmetic Coprocessor 2.05
DFPAU Floating Point Arithmetic Coprocessor, designed assist performing floating point arithmetic computations. DFPAU directly replaces software functions, equivalent, very fast hardware operations, which significantly accelerate system performance. doesn't require programming, also doesn't require modifications made main software. Everything done automatically during software compilation DFPAU driver. DFPAU designed operate with DCD's DP8051, also operate with other 32-bit processor. Drivers popular 8051 compilers delivered together with DFPAU package DFPAU uses specialized algorithms compute arithmetic functions. supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign number. input numbers format according IEEE-754 standard single precision real numbers. DFPAU prepared with 32-bit processors. Trigonometric functions supported indirectly, because they computed add, multiply divide operations software subroutines. Each floating point function turned on/off configuration level providing flexible scalability DFPAU module. allows save silicon space provides exact configuration required certain application.
trademarks mentioned this document trademarks their respective owners.
DFPAU technology independent design that implemented variety process technologies.
APPLICATIONS
Math coprocessors algorithms Embedded arithmetic coprocessor Fast data processing control
FEATURES
Direct replacement float software functions such /,==, !=,>=, interface supplied popular compilers: C/C++, 8051 compilers programming required Configurability available functions IEEE-754 Single precision real format support float type Flexible arguments result registers location Performs following functions:
FADD, FSUB addition, subtraction FMUL, FDIV multiplication, division FSQRT square root
FCHS, FABS change sign, absolute value
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
FXAM FUCOM
examine input data comparison
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows using Core single FPGA bitstream ASIC implementation. also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time limitations. Single Design license
VHDL, Verilog source code called
Exceptions built-in routines Masks each exception indicator:
Precision lack Underflow result Overflow result Invalid operand Division zero Denormal operand
Fully configurable Fully synthesizable, static synchronous design with internal tri-states
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Source
Encrypted, plain text EDIF called Netlist
Unlimited Designs license
Source Netlist
Upgrade from
Netlist Source Single Design Unlimited Designs
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
SYMBOL
datai(31:0)1 addr(4:2)2 datao(31:0)1
Control Unit manages execution instructions internal operation required execute particular function.
datai(31:0)1 datao(31:0)1 addr(4:2)2
Interface Mantissa
Align
Exponent Shifter
PINS DESCRIPTION
datai[31:0]1 addr[4:2] datao[31:0]
TYPE
Input Input Input Input Input Input
DESCRIPTION
Global system clock Global system reset Chip select read/write Data input Register address read/write Data write enable
Control Unit
Interface makes interface between external device DFPAU internal 32-bit modules. contains data, control status registers. configured work with 32-bit processors.
Output Data output Output Interrupt request indicator
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade APEX20KE 2640 APEX20KC 2640 APEX-II 2640 CYCLONE 2410 CYCLONE-II 2280 STRATIX 2210 STRATIX-II 1680 Core performance ALTERA® devices Device
data configured depends processor's size address aligned work with (3:0), 16(3:1) (4:2) processors
BLOCK DIAGRAM
Mantissa performs operations mantissa part number. addition, subtraction, multiplication, division, square root, comparison conversion operations executed this module. contains mantissas work registers. Exponent performs operations exponent part number. addition, subtraction, shifting, comparison conversion operations executed this module. contains exponents work registers. Align performs numbers analyze against IEEE-754 standard compliance. Information about data classes passed result appropriate internal module. Shifter performs mantissa shifting during normalization, denormalization operations. Information about shifted-out bits stored rounding process.
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
IMPROVEMENTS
DFPAU floating point instructions performance been compared standard library functions delivered with every commercial compiler. Each program executed same system environments. Number clock periods were measured between input data loading into work registers output result storing after operation. results placed table below. Improvement been computed number (CPU clk) divided (CPU+DFPAU clk), required execute same operation. More details available core documentation. following table gives survey about DP8051+DFPAU performance compared 8051 microcontroller.
table below shows performance improvements NIOS-II processor with DFPAU, compared same system without DFPAU coprocessor.
Device
Improvement
NIOS-II/s NIOS-II+DFPAU (arithmetic) NIOS-II+DFPAU (trigonometric) NIOS-II+DFPAU (overall) General performance improvements
Device
Improvement
80C51 DP8051 DP8051+DFPAU 91.0 General performance improvements
32-bit NIOS-II/s NIOS-II+DFPAU (arithmetic) NIOS-II+DFPAU (trigonometric) NIOS-II+DFPAU (overall)
80C51 DP8051 DP8051+DFPAU
IEEE-754 Instruction Improvement Addition Subtraction Multiplication Division Square Root 12.9 Sine Cosine Tangent Arcs Tangent Average speed improvement: Improvements particular operations
IEEE-754 Instruction Improvement Addition Subtraction Multiplication Division Square Root Sine Cosine Tangent Arcs Tangent Average speed improvement: Improvements particular operations
trademarks mentioned this document trademarks their respective owners.
More details available core documentation.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinfo@dcd.pl tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

Floating Point Arithmetic Coprocessor 2.05 DFPAU Floating Point A

Top Searches for this datasheet

Other recent searches