8-bit FAST Microcontrollers Family 2.17 Document contains brief d

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DF6811CPU
8-bit FAST Microcontrollers Family 2.17
Document contains brief description DF6811CPU core functionality. DF6811CPU advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6811CPU soft core binarycompatible with industry standard 68HC11 8-bit microcontroller achieve performance 45-100 million instructions second. There configurations DF6811CPU: Harvard where data program buses separated, Neumann with common program data DF6811CPU FAST architecture that times faster compared original implementation. Self-monitoring circuitry included on-chip protect against system errors. illegal opcode detection circuit provides nonmaskable interrupt when illegal opcode detected. software-controlled power-saving modes, WAIT STOP, available conserve additional power. These modes make DF6811CPU Core especially attractive automotive battery-driven applications. DF6811CPU have built development support features designed into DF6811. signal intended debugging aid. This signal driven active first cycle each instruction, making easy reverse assemble (disassemble) instructions from display logic analyzer.
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DF6811CPU fully customizable, which means delivered exact configuration meet users requirements. There need extra used features wasted silicon. includes fully automated testbench with complete tests allowing easy package validation each stage design flow.
FEATURES FEATURES
FAST architecture, times faster than original implementation Software compatible with industry standard 68HC11 Configurable Harvard Neumann architectures times faster multiplication times faster division bytes remapped System Function Registers space (SFRs) bytes Data Memory De-multiplexed Address/Data allow easy connection memory power saving modes: STOP, Ready allows Core operate with slow program data memories Fully synthesizable, static synchronous design with internal tri-states
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internal reset generator gated clock Scan test ready Technology independent source code Core fully customized virtual clock frequency compared original implementation DoCDon Chip Debugger
Processor execution control Read, write processor contents Hardware execution breakpoints Three wire communication interface
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
DESIGN FEATURES
GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET DF6811 reset vectors sources, which easy identify cause system reset. ASYNCHRONOUS INPUT SIGNALS
SYNCHRONIZED BEFORE INTERNAL
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
CONFIGURATION
following parameters DF6811CPU core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
DoCD Hardware Debugger
DATA MEMORY:
DF6811 address bytes Data Memory function interconnect signals. bytes Data Memory every page reserved Function Registers. Extra (Data Page Pointer) register used segments swapping. Data Memory implemented synchronous asynchronous RAM.
SYSTEM FUNCTION REGISTERS:
used unused Harvard Neumann Synchronous Asynchronou used unused used unused used unused used unused
Architecture type Memories type Data Memory size Data Memory wait-states Power saving STOP mode Support Instructions Support Instruction
System Function Registers(SFRs) implemented DF6811 design. SFRs memory mapped into Data Memory within bytes address space.
PROGRAM MEMORY:
64kB Program Memory implemented DF6811 design. Program Memory implemented synchronous asynchronous ROM.
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LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL, Verilog source code called Sour-
SYMBOL
prgdata(7:0) ready datai(7:0) prgaddr(15:0) prgoe datao(7:0) addr(23:0) ramwe ramoe ufraddr(7:0) ufrwe ufroe halt docddatao docdclk prgwe
ufrdatai(7:0)
xirq clkdocd docddatai
DoCD
Encrypted, plain text EDIF called Netlist
Interface
Year license
Encrypted Netlist only
PINS DESCRIPTION
prgdata[7:0] ready datai[7:0] ufrdatai[7:0] xirq prgaddr[15:0] prgoe datao[7:0] addr[23:0] ramwe ramoe ufraddr[7:0] ufrwe ufroe halt clkdocd docddatai docddatao docdclk prgwe ACTIVE High TYPE input input input input input input input input input output output output output output output output output output output output input input output output output DESCRIPTION Global system clock Power Reset indicator Clock Monitor Fail Reset Program memory input Non-maskable interrupt input External memory input UFRs data input Ready CODE DATA Non-maskable interrupt input Program memory address Program memory output enable Data memory output Data memory address Data memory write enable Data memory output enable address UFRs write enable UFRs output enable Load instruction register Halt clock system (STOP inst.) Separate DoCD DoCD DoCD DoCD DoCD
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
Clock input
serial Data input Serial Data Output Serial Clock Output Program Memory Write
Kind activity configurable
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BLOCK DIAGRAM
Control Unit Performs core synchronization data flow control. This module manages execution instructions. Control Unit also manages execution STOP instruction waking-up processor from STOP mode. Opcode Decoder Performs instruction opcode decoding control functions other blocks. Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. contains accumulator Condition Code Register (CCREG), related logic like arithmetic unit, logic unit, multiplier divider. Controller Program Memory, Data Memory SFR's (Special Function Register) interface controls access into program data memories special registers. contains Program Counter (PC), Stack Pointer (SP) register, INIT register (INIT), Data Page Pointer (DPP), Stretch register (ST) related logic.
Opcode Decoder
intrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
OPTIONAL MODULES
There also available optional peripherals, included presented DF6811CPU Microcontroller Core. optional peripherals, implemented microcontroller core upon customer request. Four 8-bit Ports Interrupt Controller
interrupt sources priority levels Dedicated Interrupt vector each interrupt
prgdata(7:0) prgaddr(15:0) prgoe datao(7:0)
Controller
halt
Control Unit
xirq
Interrupt Controller
datai(7:0) addr(23:0) ramwe ramoe ufrdatai(7:0) ufraddr(7:0) ufrwe ufroe ready
source
Main16-bit timer/counter system
free running counter Four stage programmable prescaller Timer clocked internal source Real Time Interrupt
clkdocd docddatai docddatao docdclk prgwe
DoCD Debugger
Interrupt Controller DF6811CPU implemented only external interrupts from pins XIRQ. interrupts activated level (XIRQ,IRQ pins) falling edge (IRQ pin) sampled each system clock rising edge CLK. DoCD Debug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other on-chip debuggers DoCDprovides nonAll trademarks mentioned this document trademarks their respective owners.
16-bit Compare/Capture Unit
Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator http://www.dcd.pl
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Pulse width modulation Pulse width measuring
NORMAL speed FAST speed HIGH speed 3400 Wide range system clock frequencies User defined data setup time lines Interrupt generation
8-bit Pulse accumulator
major modes operation Simple event counter Gated time accumulation Clocked internal source external
Programmable Watchdog Timer Fixed-Point arithmetic coprocessor
Multiplication 16bit 16bit Division 32bit 16bit Division 16bit 16bit Left right shifting bits Normalization
Full-duplex UART
Standard Nonreturn Zero format (NRZ) data transfer Integrated baud rate generator Enhanced receiver data sampling technique Noise, Overrun Framing error detection IDLE BREAK characters generation Wake-up block recognize UART wake-up
from IDLE condition
Three related interrupts
Floating-Point arithmetic coprocessor IEEE-754 standard single precision
FADD, FSUB addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM compare FCHS change sign FABS absolute value
Master Slave Serial Peripheral Interface
Supports speeds system clock Software selectable polarity phase
rial clock
System errors detection Allows operation from wide range system
clock frequencies (build-in 5-bit timer)
Interrupt generation
Floating-Point math coprocessor IEEE754 standard single precision real, word short integers
FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS change sign FABS absolute value FSIN, FCOS- sine, cosine FTAN, FATAN tangent arcs tangent
Pulse Width Modulation Timer
independent 8-bit channels, concate-
nated 16-bit channel
Software-selectable duty from 100%
pulse period
Software-selectable polarity output wave-
form
controller Master
7-bit 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration synchronization User defined timings lines Wide range system clock frequencies Interrupt generation
controller Slave
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PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE 1834 STRATIX 1834 MERCURY 1808 APEX 1849 APEX20KC 1809 APEX20KE 1809 ACEX1K 1785 FLEX10KE 1785 Core performance ALTERA® devices Device
IMPROVEMENT
user most important application speed improvement. most commonly used arithmetic functions theirs improvement shown table below. Improvement computed {M68HC11 clock periods} divided {DF6811CPU clock periods} required execute identical function. More details available core documentation.
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Fractional division Integer division Improvement 14,9 16.4
DF68XX FAMILY main features each DF68XX family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Paged Data Memory space READY Prg. Data memories
Main Timer System
Real Time Interrupt
Speed acceleration
Pulse accumulator
Design
DF6805 DF6808 DF6811 DF6811CPU
2/2* 2/2* 5/3*
DF68XX family High Performance Microcontroller Cores
optional configurable
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Size ASIC gates
Compare\Capture
Interface
Motorola Memory Expansion Logic
Interrupt sources
DoCD Debugger
Watchdog Timer
Interface additional SFRs
Physical Linear memory space
Interrupt levels
Data Pointers
(UART)
Ports
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinfo@dcd.pl tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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