8-bit FAST Microcontrollers Family 1.04 Document contains brief d

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DF6805
8-bit FAST Microcontrollers Family 1.04
Document contains brief description DF6805 core functionality. DF6805 advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6805 soft core binary-compatible with industry standard 68HC05 8-bit microcontroller achieve performance 45-100 million instructions second. There configurations DF6805: Harvard where data program buses separated, Neumann with common program data DF6805 FAST architecture that times faster compared original implementation. Core standard configuration integrated chip major peripheral function. DF6805 Microcontroller Core contains full-duplex UART (Asynchronous serial communications interface (SCI), also equipped with Synchronous Serial Peripheral Interface SPI. main 16-bit, free-running timer system implemented input capture lines output-compare lines. Self-monitoring circuitry included on-chip protect against system errors. computer operating properly (COP) watchdog system protects against software failures. illegal opcode detection circuit provides nonmaskable interrupt illegal opcode detected. software-controlled power-saving modes, WAIT STOP, available conserve
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additional power. These modes make DF6805 Core especially attractive automotive battery-driven applications. DF6805 fully customizable, which means delivered exact configuration meet users requirements. There need extra used features wasted silicon. includes fully automated testbench with complete tests allowing easy package validation each stage design flow.
FEATURES
FAST architecture, times faster than original implementation Software compatible with industry standard 68HC05 Configurable Harvard Neumann architectures bytes System Function Registers space (SFRs) bytes Program Memory bytes Data Memory De-multiplexed Address/Data allow easy connection memory power saving modes: STOP, Ready allows Core operate with slow program data memories Fully synthesizable, static synchronous design with internal tri-states
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internal reset generator gated clock Scan test ready Technology independent source code Core fully customized virtual clock frequency compared original implementation
Dedicated Interrupt vector each interrupt
source
Main16-bit timer/counter system
free running counter Timer clocked internal source
16-bit Compare/Capture Unit
independent input-capture functions output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring
DESIGN FEATURES
GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET ASYNCHRONOUS INPUT SIGNALS
SYNCHRONIZED BEFORE INTERNAL
DATA MEMORY:
DF6805 address bytes Data Memory. lowest Bytes reserved Special Function Registers area. Data Memory implemented synchronous asynchronous
SYSTEM FUNCTION REGISTERS:
Full-duplex UART
Standard Nonreturn Zero format (NRZ) data transfer Integrated baud rate generator Noise, Overrun Framing error detection IDLE BREAK characters generation Wake-up block recognize UART wake-up
System Function Registers(SFRs) implemented DF6805 design.
PROGRAM MEMORY:
from IDLE condition
Three related interrupts
64kB Program Memory implemented DF6805 design. Program Memory implemented synchronous asynchronous ROM.
CORE DESIGNED SYNCHRONOUS LOGIC WITHOUT MICROCODE.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
PERIPHERALS
peripherals listed below implemented standard configuration DF6805. DoCDon Chip Debugger
Processor execution control Read, write processor contents Hardware execution breakpoints Three wire communication interface
Four 8-bit Ports Interrupt Controller
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Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
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CONFIGURATION
following parameters DF6805 core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
DoCD Hardware Debugger
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL, Verilog source code called Sour-
used unused Harvard Neumann Synchronous Asynchronou used unused used unused used unused used unused used unused used unused used unused used unused
Architecture type Memories type Data Memory wait-states Power saving STOP mode WATCHDOG Timer Timer system Compare Capture channels PORTS UART Interface Support Instruction
Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
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PINS DESCRIPTION
prgdata[7:0] datai[7:0] ufrdatai[7:0] ready portai[7:0] portbi[7:0] portci[7:0] portdi[7:0] cap1,2 clkdocd docddatai prgaddr[15:0] prgoe datao[7:0] addr[15:0] ramwe ramoe ufraddr[5:0] ufrwe ufroe halt portao[7:0] portbo[7:0] portco[7:0] portdo[7:0] ddra[7:0] ddrb[7:0] ddrc[7:0] ddrd[7:0] cmp1,2 docddatao docdclk prgwe ACTIVE High TYPE input input input input input input input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output output output DESCRIPTION Global system clock Global system reset Program memory input Memory input UFRs data input Code Data memory Ready Interrupt input Port input Port input Port input Port input Capture inputs receiver data input DoCD DoCD
SYMBOL
prgdata(7:0) prgaddr(15:0) prgoe datao(7:0) datai(7:0) addr(15:0) ramwe ramoe ufraddr(5:0) ufrwe ufroe halt portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 clkdocd docddatai
DoCD
ufrdatai(7:0) ready portai(7:0) portbi(7:0) portci(7:0) portdi(7:0)
clock input serial Data input
Program memory address Program memory output enable Data memory output Data memory address Data memory write enable Data memory output enable UFR's address UFRs write enable UFRs output enable Halt clock system (STOP inst.) Port output Port output Port output Port output Port data direction control Port data direction control Port data direction control Port data direction control Compare outputs transmitter data output DoCD DoCD DoCD
cmp1 cmp2 docddatao docdclk prgwe
Interface
BLOCK DIAGRAM
Control Unit Performs core synchronization data flow control. This module manages execution instructions. Control Unit also manages execution STOP instruction wakes-up processor from STOP mode. Opcode Decoder Performs instruction opcode decoding control functions other blocks. Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. contains accumulator (A), Condition Code Register (CCREG), Index registers related logic like arithmetic unit, logic unit multiplier.
Serial Data Output Serial Clock Output Program Memory Write
Kind activity configurable
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Controller Program Memory, Data Memory SFR's (Special Function Register) interface controls access into program data memories special registers. contains Program Counter (PC), Stack Pointer (SP) register, related logic.
Opcode Decoder
halt
Control Unit
Controller
ready prgdata(7:0) prgaddr(15:0) prgoe datai(7:0) datao(7:0) addr(23:0) ramwe ramoe ufraddr(5:0) ufrwe ufroe portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 cmp1 cmp2
ports pins cause data stored data registers. port pins configured output then data registers driven those pins. Reads from port pins configured input causes that input read. port pins configured output, during read data register read. Writes ports pins configured outputs cause data driven those pins, data stored output registers. Thus, pins later become outputs, last data written port will driven port pins. Timer Compare programmable timer based free-running 16-bit counter with fixed divide four prescaler. plus input capture/output compare circuitry. timer used many purposes including measuring pulse length input signals generating output signals. timer 16bit architecture, hence each specific functional segment represented 8-bit registers. These registers contains high byte that functional block. Accessing byte specific timer function allows full control that function, however, access high byte inhibits that specific timer function until byte also accessed. Each input-capture channel 16-bit time capture latch (input-capture register) each output-compare channel 16-bit compare register. Additional control bits permit software control edge(s) that trigger each input-capture function automatic actions that result from output-compare functions. Although hardwired logic included automate many timer activities, this timer architecture essentially software-oriented system. This structure easily adaptable very wide range applications although efficient dedicated hardware some specific timing applications. Watchdog Timer Watchdog Timer consist free running Timer CLK/213 plus control logic. Watchdog Timer enabled software writing WDOG MISC register ($000C). Once enabled Timer cannot disabled software. addition WDOG acts reset mechanism Timer. Writing logic WDOG clears Watchdog counter inhibits Watchdog timeout
Interrupt Controller
Watchdog Timer
Ports
clkdocd docddatai docddatao docdclk prgwe
Unit
DoCD Debugger
Timer with Compare Capture Unit
Interrupt Controller DF6805 extended implemented 7-level interrupt priority control. interrupt requests come from external (IRQ) well from particular peripherals. DF6805 peripheral systems generate maskable interrupts, which recognized only global interrupt mask cleared. Maskable interrupts prioritized according default arrangement established during reset. When interrupt condition occurs, interrupt status flag indicate condition. Ports ports 8-bit general-purpose bi-directional system. PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD control ports data flow. assures that DF6805's ports have full selectable registers. Writes
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full-duplex UART type asynchronous system, using standard return zero (NRZ) format start bit, data bits stop bit. DF6805 resynchronizes receiver clock zero transitions stream. Therefore differences baud rate between sending device likely cause reception errors. Three logic samples taken near middle data time, majority logic decides sense bit. start stop bits seven logic samples taken. Even noise causes these samples incorrect, will still received correctly. receiver also ability enter temporary standby mode (called receiver wakeup) ignore messages intended different receiver. Logic automatically wakes receiver time first character next message. This wakeup feature greatly reduces overhead multi-drop networks. transmitter produce queued characters idle (whole characters logic break (whole characters logic addition usual transmit data register empty (TDRE) status flag, this also provides transmit complete (TC) indication that used applications with modem. DoCD Debug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other on-chip debuggers DoCDprovides nonintrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
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OPTIONAL PERIPHERALS
There also available optional peripherals, included presented DF6805 Microcontroller Core. optional peripherals, implemented microcontroller core upon customer request. Master Slave Serial Peripheral Interface
Supports speeds system clock Mode fault error Write collision error Software selectable polarity phase
rial clock
System errors detection Allows operation from wide range system
clock frequencies (build-in 5-bit timer)
Interrupt generation
controller Master
7-bit 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration synchronization User defined timings lines Wide range system clock frequencies Interrupt generation
controller Slave
NORMAL speed FAST speed HIGH speed 3400 Wide range system clock frequencies User defined data setup time lines Interrupt generation
Pulse Width Modulation Timer Fixed-Point arithmetic coprocessor arithmetic coprocessor Floating-Point IEEE-754 standard single precision Floating-Point math coprocessor IEEE754 standard single precision real, word short integers
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PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE 1689 STRATIX 1690 MERCURY 1671 APEX 1850 APEX20KC 1698 APEX20KE 1698 ACEX1K 1739 FLEX10KE 1739 Core performance ALTERA® devices Device
IMPROVEMENT
user most important application speed improvement. most commonly used arithmetic functions theirs improvement shown table below. Improvement computed {M68HC04 clock periods} divided {DF6805 clock periods} required execute identical function. More details available core documentation
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Division Improvement
Area utilized each unit DF6805 core vendor specific technologies summarized table below.
Component
[LC]
Area
[FFs]
CPU* Main Timer COM/CAP Watchdog UART Ports Total area
1134 1856
*CPU consisted ALU, Control Unit Instruction Decoder, Controller with support 64KB RAM, External Interrupt Controller
Core components area utilization
DF68XX FAMILY main features each DF68XX family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Size ASIC gates Compare\Capture Interface Motorola Memory Expansion Logic Interrupt sources DoCD Debugger Pulse accumulator
Watchdog Timer
Main Timer System
Real Time Interrupt
Ports
Design
DF6805 DF6808 DF6811 DF6811CPU
2/2* 5/3*
DF68XX family High Performance Microcontroller Cores
optional
configurable
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Interface additional SFRs
READY Pro. Data mem.
Physical Linear memory space
Paged Data Memory space
Interrupt levels
Data Pointers
(UART)
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinfo@dcd.pl tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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