DCAN stand-alone controller Controller Area Network (CAN) widely used

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DCAN stand-alone controller Controller Area Network (CAN) widely used

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Configurable Controller 1.01
DCAN stand-alone controller Controller Area Network (CAN) widely used automotive industrial applications. DCAN conforms Bosch 2.0B specification (2.0B Active). Core simple interface (8/16/32 configurable data width) with little endian adressing scheme. Hardware message filtering byte receive FIFO enables back-to-back message reception with minimum load. DCAN described level allowing target FPGA ASIC technologies. Last Error Code Fully synthesizable Static synchronous design with positive edge clocking synchronous reset internal tri-states Scan test ready
APPLICATIONS
Embedded communication systems Automotive, industrial Medical equipment
FEATURES
Conforms Bosch 2.0B Active 8/16/32-bit slave interface with little endianess Simple interface allows easy connection Supports both standard (11-bit identifier) extended identifier) frames. Data rate Mbps Hardware message filtering (dual/single filter) byte receive FIFO transmit buffer overload frames generated Normal Listen Only Mode Single Shot transmission Ability abort transmission Readable error counters
DELIVERABLES
Source code: VHDL Source Code VHDL test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
http://www.dcd.pl
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2007 Digital Core Design. Rights Reserved.
SYMBOL
docdbusctrl qmt(31:0) dmt(31:0) waddrmt(1:0) raddrmt(1:0) enrmt enwmt
enrmt enwmt sclk
output output output output
DPRAM read enable DPRAM write enable transmit data SCLK clock output
BLOCK DIAGRAM
Figure below shows DCAN Core block diagram.
pins
datao(31:0)1 be(3:0)2 datai(31:0)1 dmr(31:0) waddrmr(3:0) addr(4:0) raddrmr(3:0) enrmr enwmr qmr(31:0) sclk
interface
sclk
Stream Processor
Baud Rate Prescaler Interface Management Logic
Timing Logic
be(3:0) addr(4:0) datai(31:0) datao(31:0)
Acceptance Filtering
Error Management Logic
Receive FIFO
interface
data configured depends processor's size byte enable (be) size accordingly data size
pins
PINS DESCRIPTION
addr(4:0) be(3:0)
Interface Management Logic (IML) interprets commands from CPU, provides interrupt status indication. Stream Processor (BSP) translates messages into frames vice versa. Baud Rate Prescaler (BRP) defines length time quantum. Timing Logic (BTL) processes time, calculates position sample point performs synchronization. Error Management Logic (EML) responsible fault confinement handling. Acceptance Filter (ACF) decides whether incoming messages accepted based upon filter registers settings. TX/RX interfaces interfaces external dual port memories used DCAN core store received transmitted frames.
TYPE
input input input input input input input input input input input input output output output output output output output output output output
DESCRIPTION
Global clock Global reset Chip select Read data strobe Write data strobe Host address Host byte enable Host output data DPRAM data output DPRAM data output receive data DoCD debugger input Host input data Interrupt signal DPRAM data input DPRAM write address DPRAM read address DPRAM read enable DPRAM write enable DPRAM data input DPRAM write address DPRAM read address
datai(31:0) qmr(31:0) qmt(31:0)
docdbusctrl datao(31:0) dmr(31:0) waddrmr(3:0) raddrmr(3:0) enrmr enwmr dmt(31:0) waddrmt(1:0) raddrmt(1:0)
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Speed Logic Cells Fmax grade CYCLONE 1956 CYCLONE2 1899 STRATIX 1956 STRATIX2 1956 STRATIXGX 1956 MERCURY 1956 EXCALIBUR 1956 APEX2A 1956 APEX20KC 1956 APEX20KE 1956 APEX20K 1956 ACEX1K 1956 FLEX10KE 1956 8-bit Core performance ALTERA® devices Device Speed Logic Cells Fmax grade CYCLONE 1967 CYCLONE2 1890 STRATIX 1967 STRATIX2 1523 STRATIXGX 1967 MERCURY 1967 EXCALIBUR 1967 APEX2A 1967 APEX20KC 1967 APEX20KE 1937 APEX20K 1967 ACEX1K 1967 FLEX10KE 1967 16-bit Core performance ALTERA® devices Device Speed Logic Cells Fmax grade CYCLONE 1931 CYCLONE2 1879 STRATIX 1931 STRATIX2 1510 STRATIXGX 1931 MERCURY 1931 EXCALIBUR 1931 APEX2A 1931 APEX20KC 1931 APEX20KE 1931 APEX20K 1931 ACEX1K 1931 FLEX10KE 1931 32-bit Core performance ALTERA® devices Device
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.

DCAN stand-alone controller Controller Area Network (CAN) widely used

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