Configurable UART 2.07 D16450 soft Core Universal Asynchronous Re
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D16450
Configurable UART 2.07
D16450 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C450. D16450 performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters received from CPU. read complete status UART time during functional operation. Status information reported includes type condition transfer operations being performed UART, well error conditions (parity, overrun, framing, break interrupt). D16450 includes programmable baud rate generator that capable dividing timing reference clock input divisors (216-1), producing clock driving internal transmitter logic. Provisions also included this clock drive receiver logic. D16450 complete MODEM control capability, processor-interrupt system. Interrupts programmed user's requirements, minimizing computing required handle communications link. separate BAUD line allows exact transmission speed, while UART internal logic clocked with frequency core perfect applications, where UART Core microcontroller clocked same clock signal implemented inside same ASIC FPGA chip, well
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standalone implementation, where several UARTs required implemented inside single chip, driven some off-chip devices. Thanks universal interface D16450 core implementation verification very simply, eliminating number clock trees complete system.
FEATURES
Software compatible with 16450 UART Configuration capability Separate configurable BAUD clock line Majority Voting Logic Adds deletes standard asynchronous communication bits (start, stop, parity) from serial data UART mode receiver transmitter double buffered eliminate need precise synchronization between serial data Independently controlled transmit, receive, line status, data interrupts False start detection programmable baud generator MODEM control functions (CTS, RTS, DSR, DTR, DCD)
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Fully programmable characteristics:
8-bit characters
serial-interface
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
Even, odd, no-parity generation detection 2-stop generation Baud generation
Complete status reporting capabilities Line break generation detection. Internal diagnostic capabilities:
Loop-back controls communications link fault isolation Break, parity, overrun, framing error simulation
Technology Code
independent
Source
Full prioritized interrupt system controls Fully synthesizable static design with internal tri-state buffers
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
APPLICATIONS
Serial Data communications applications Modem interface
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
Source Netlist Single Design Unlimited Designs
SYMBOL
rclk baudclk datai(7:0) address(2:0) baudclken rclken baudout intr datao(7:0) ddis
CONFIGURATION
following parameters D16450 core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
Baud generator External RCLK source External BAUDCLK source Modem Control logic Register enable disable enable disable enable disable enable disable enable disable
datai[7:0] addr[2:0] rclk baudclk baudclken rclken baudout datao[7:0] ddis out1 out2 intr
D16450
out1 out2
PINS DESCRIPTION
TYPE
input input input input input input input input input input input input input input input input output output output output output output output output output
DESCRIPTION
Global reset Global clock Parallel data input Address Chip select input Write input Read input Receiver clock Baud generator clock Serial data input Clear send input Data ready input Data carrier detect input Ring indicator input Baud generator clock enable Receiver clock enable Baud generator output Parallel data output Serial data output Driver disable output Request send output Data terminal ready output Output Output Interrupt request output
DESIGN FEATURES
functionality D16450 core based Texas Instruments TL16C450. following characteristics differentiate D16450 from Texas Instruments devices: bi-directional data been split into separate buses: datai(7:0), datao(7:0) Signals wr2, xin, xout have been removed from interface Signal address latch have been removed DLL, registers reset zeros TEMT THRE bits Line Status Register, reset during second clock rising edge following write RCLK clock replaced global clock CLK, internally divided BAUD factor. Asynchronous microcontroller interface replaced equivalent Universal interface latches implemented original 16450 devices replaced equivalent flip-flop registers, with same functionality
Note: When enabled RCLK BAUDCLK pins frequency should least times lower than CLK, 2*fRCLK< fCLK
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
APPLICATION
addr addr latch addr(2:0) D16450 baudclk rclk
Modem Control Logic controls interface with MODEM data peripheral device emulating MODEM). Interrupt Controller D16450 consists fully prioritized interrupt system controller. controls interrupt requests interrupt priority. Interrupt controller contains Interrupt Enable (IER) Interrupt Identification (IIR) registers.
Drivers
addr(2:0) datai(7:0) datao(7:0) ddis
Receiver Control Shift Register
datao(7:0) datai(7:0)
datai(7:0) datao(7:0) intr out1 out2
baudclken rclken
Data Buffer
rclk rclken
Typical D16450 processor connection shown figure above.
Transmitter Control Shift Register Interrupt Controller
BLOCK DIAGRAM
Data Buffer data Buffer accepts inputs from system generates control signals other D14750 functional blocks. Address ADDR(2:0) selects register read from/written into. Both signals active low, qualified ignored unless D16450 been selected holding low. Baud Generator D16450 contains programmable baud generator that divides clock input divisor range between (216-1). output frequency baud generator baud rate. formula divisor
baudclk baudclken baudout
Baud Generator Modem control logic
out1 out2
Receiver Control Receiving starts when falling edge Serial Input (SI) during IDLE State detected. After starting input sampled every internal baud cycles shown figure below. When logic state detected during START means that False Start detected receiver back IDLE state. Transmitter Control module controls transmission written (Transmitter Holding register) character serial output transmission starts next overflow signal internal baud generator, after writing register Transmitter FIFO. Transmission control contains register transmitter shift register.
frequency divisor baudrate
8-bit registers, called divisor latches DLM, store divisor 16-bit binary format. These divisor latches must loaded during initialization D16450 order ensure desired operation baud generator. When either divisor latches loaded, 16-bit baud counter also loaded rising edge following write prevent long counts initial load.
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE CYCLONE STRATIX STRATIX STRATIXGX MERCURY EXCALIBUR APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE Core performance ALTERA® devices Device
D16X50 UARTS FAMILY family D16X50 UART Cores combine high-performance, cost, small compact size, offering best price/performance ratio Market. DCD's Cores dedicated cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security telecommunication applications. D16X50 Cores written pure VHDL/VERILOG languages which make them technologically independent. D16X50 Cores fully customized according customer needs.
Prioritized interrupt system Internal diagnostic capabilities
D16450 D16550 D16750 D16552 D16752 D16754
IRDA Port
Design
*-Optional
D16X50 family Configurable UARTs with FIFO Cores
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
1284 Parallel Port
FIFO Size (Bytes)
Break generation detection
Complete status reporting
False START detection
MODEM Control
Separate BAUD Clock line
UARTS number
RTS/CTS Flow Control
Majority voting logic
Software Flow Control
FIFO Mode operation
UART Mode
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
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Copyright 1999-2007 Digital Core Design. Rights Reserved.
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