Programmable Interrupt Controller 1.04 D8259 soft Core Programmab
|
|
|
Top Searches for this datasheet
D8259
Programmable Interrupt Controller 1.04
D8259 soft Core Programmable Interrupt Controller. fully compatible with 82C59A device. D8259 Core manages 8-vectored priority interrupts processor. Programming cascade allows vectored interrupts. More than vectored interrupts accomplished programming Poll Command Mode. D8259 operate 82C59A modes, supports 82C59A features: MCS-80/85 8088/8086 processor modes Fully nested mode special fully nested mode Special mask mode Buffered mode Pool command mode Cascade mode with master slave selection Automatic end-of-interrupt mode Specific non-specific end-of-interrupt commands Automatic Specific Rotation Edge level triggered interrupt input modes Reading interrupt request register (IIR) in-service register (ISR) through data bus. Writing reading interrupt mask register (IMR) through data
FEATURES
vectored priority interrupts sixty-four vectored priority interrupts with cascading Support 82C59A modes features
MCS-80/85 8088/8086 processor modes Fully nested mode special fully nested mode Special mask mode Buffered mode Pool command mode Cascade mode with master slave selection Automatic end-of-interrupt mode Specific non-specific end-of-interrupt commands Automatic Specific Rotation Edge level triggered interrupt input modes Reading interrupt request register (IIR) in-service register (ISR) through data
Fully synthesizable, static design with internal tri-states
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
SYMBOL
datai(7:0) ir(7:0) inta casi(2:0) datao(7:0)
caso(2:0) case
PINS DESCRIPTION LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
datai(7:0) ir(7:0) inta casi(2:0) datao(7:0) caso(2:0) case
TYPE
input input input input input input input input input input
DESCRIPTION
Power-up reset Data (input) Processor address line Chip select Read strobe Write strobe Interrupt request lines Interrupt acknowledge Cascade input lines Slave program input
output Data (output) output Data output enable output Interrupt request output output Cascade output lines output Cascade output enable output Buffer transceiver enable
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source
http://www.dcd.pl
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2007 Digital Core Design. Rights Reserved.
BLOCK DIAGRAM
Read Write Logic Read/Write Logic accepts inputs from system generates control signals other functional blocks D8259. "low'' input tells D8259 that reading contents registers. "low'' input tells D8254 that writing Command Words D8259. Both qualified ignored unless D8259 been selected holding low. Data Buffer 8-bit buffer used interface D8259 system bus.
inta
Control logic Read/Write Logic
Control Logic block checks INTA pulses, which cause D8259 release vectoring information onto Data Bus. Format drive data depends mode operation. also manages state output. Interrupt Request Register register stores information about states lines. saves information about interrupt requests serviced. Priority Resolver block resolve which interrupt request highest priority, will served first. Service Register- register stores information about interrupts that being serviced.
datai(7:0) datao(7:0) casi(2:0) caso(2:0) case
Data Buffer
Interrupt Request Register
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route:
Speed Logic Cells Fmax grade CYCLONE CYCLONE STRATIX STRATIX STRATIXGX MERCURY EXCALIBUR APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE Core performance ALTERA® devices Device
Cascade Controller
Priority resolver
Interrupt Mask Register
Service Register
Cascade Controller Cascade Controller stores compares Identifiers 8259 devices system. Block manages direction input/output buses, depending device status: Master Slave. When operating master D8259 drives onto address interrupting 8259 device, then addressed 8259 slave during next consecutive INTA pulses send Data preprogrammed address subroutine. Interrupt Mask Register register stores information which interrupt request masked.
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND
nfo@dcd.pl e-mail: iinfo@dcd.pl
tel.
Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2007 Digital Core Design. Rights Reserved.
Other recent searches
TS914 - TS914 TS914 Datasheet
STi7710 - STi7710 STi7710 Datasheet
MC-4516CB646 - MC-4516CB646 MC-4516CB646 Datasheet
AN-2004-01 - AN-2004-01 AN-2004-01 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
