TLCS-900/L1 Series TMP91FU62FG TMP91FU62DFG TOSHIBA CORPORAT
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Microcontroller
TLCS-900/L1 Series
TMP91FU62FG TMP91FU62DFG
TOSHIBA CORPORATION
information contained herein subject change without notice. TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights TOSHIBA others. Please contact your sales representative product-by-product details this document regarding RoHS comaptibility. Please these products this document compliance with applicable laws regulations that regulate inclusion controlled substances. Toshiba assumes liability damage losses occurring result noncompliance with applicable laws regulations.
2007 TOSHIBA CORPORATION Rights Reserved
TMP91FU62
Revision History Date
2007/01/18
Revision
TENTATIVE Table Names Functions WAIT deletion. HV-monitor EMU0 P00-P07 large-current port RESET system clocks 16us 2.3.4 Prescaler Clock Controller Table Port Functions Table Port Setting List Port3 (P30 P33) Deleted input function wait control(WAIT) Deleted Note2. function Table. 4.9.1 Port (TXD0/RXD0), (TXD1/RXD0) 4.9.2 Port91(RXD0/TXD0), (RXD1/TXD1) function Table. 4.12 Open-drain Control 4.13 Serial channel change Control 14.1 Absolute Maximum Ratings Table Source Halt State Clearance Halt Clearance Operation Table Port Setting List (Port Port (P00 P07) Port (P10 P17) Port (P40 P43) Figure 4-12 Port72 4.13 Serial channel change/ Open-drain output Control Table Registers Pins TMRB 10-bit Converter (ADC) VREFH AVCC
2007/04/27
Figure Analog Input Voltage Conversion Result (Typ.) 13.6.10 Programming Flash Memory Internal Read Values Product Mode Example: Program loaded executed 14.2 Electrical Characteristics Low-level output current 14.3 Conversion Characteristics Deleted Analog current analog reference voltage 15.Table SFR's Deleted P4FC register
TMP91FU62
Date
2007/06/07
Revision
14.1 Absolute Maximum Ratings IOL, corrected 14.2 Electrical Characteristics ICC, IDDP-P corrected
2007/8/27
DMAR register (89H) corrected prohibition. 17.2 Points note Releasing HALT mode requesting interruption deleted. 2.3.2 Note3 added 7.2.1 Plescaler corrected, Table corrected Note2 Note3 added 17.2 Points note j.Clocks serial channels (SIO)is added Table SFR's TB0FFCR, TB1FFCR, TB2FFCR TB3FFCR register corrected.
2007/10/10
TMP91FU62
CMOS Microcontroller
TMP91FU62FG/DFG
Product TMP91FU62FG bytes TMP91FU62DFG bytes QFP80-P-1420-0.80B (Flash ROM) Package LQFP80-P-1212-0.50E
Features
High-speed 16-bit (900/L1 CPU) Instruction mnemonics upward-compatible with TLCS-900,900/H,900/L Mbytes linear address space General-purpose registers register banks 16-bit multiplication division instructions; transfer arithmetic instructions Micro DMA: channels (800ns/2 bytes 20MHz) Minimum instruction execution time:200ns 20MHz) Built-in memory ROM: bytes (Flash ROM) RAM: bytes 8-bit timers: channels 16-bit timers: channels General-purpose serial interface: channels UART/Synchronous mode: channels mode: channels 10-bit converter (Built-in Sample hold circuit): channels Special timer CLOCK Watchdog timer Program patch logic: banks
This product uses Super Flash® technology under licence Silicon Storage Technology, Inc. Super Flash® registered trademark Silicon Storage Technology, Inc.
20070701-EN
information contained herein subject change without notice. TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunctionor failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patents other rights TOSHIBA third parties. Please contact your sales representative product-by-product details this document regarding RoHS compatibility. Please these products this document compliance with applicable laws regulations that regulate inclusion controlled substances. Toshiba assumes liability damage losses occuuring result noncompliance with applicable laws regulations.
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TMP91FU62
Interrupts: interrupts interrupts: Software interrupt instruction illegal instruction internal interrupts: priority levels selectable external interrupts: priority levels selectable (among interrupts selectable edge mode) Input/output ports: pins Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 STOP Clock controller Clock gear function: Select High-frequency clock fc/1 fc/16 Oscillator CLOCK 32.768 kHz) Operating voltage Flash read operation Vcc=4.5 20MHz) Flash write/erase operation Vcc=4.75 5.25 20MHz) Package LQFP80-P-1212-0.50E (TMP91FU62FG) QFP80-P-1420-0.80B (TMP91FU62DFG)
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TMP91FU62
Assignment Diagram
P67/AN15 P66/AN14 P65/AN13 P64/AN12 P63/AN11 P62/AN10 P61/AN9 P60/AN8 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 P33/TB3OUT1
Figure Assignment(TMP91FU62FG)
DVCC DVSS RESET P94/RXD1/TXD1 P95/SCLK1/CTS1 P96/XT1 P97/XT2 PA0/TB2IN0/INT1 PA1/TB2IN1/INT2 PA2/TB2OUT0 PA3/TB2OUT1 P40/SCOUT P41/TXD2/RXD2 P42/RXD2/TXD2 P43/SCLK2/CTS2 EMU0
AVSS AVCC P70/TA0IN P71/TA1OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1
TMP91FU62FG
LQFP80 TOPVIEW
P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 DVSS
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P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/AN8 P61/AN9 P62/AN10 P63/AN11 P64/AN12 P65/AN13
QFP80
TOPVIEW
TMP91FU62DFG
Figure Assignment(TMP91FU62DFG)
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P66/AN14 P67/AN15 AVSS AVCC P70/TA0IN P71/TA1OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1 DVCC
P33/TB3OUT1 P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 DVSS EMU0 P43/SCLK2/CTS2
P42/RXD2/TXD2 P41/TXD2/RXD2 P40/SCOUT PA3/TB2OUT1 PA2/TB2OUT0 PA1/TB2IN1/INT2 PA0/TB2IN0/INT1 P97/XT2 P96/XT1 P95/SCLK1/CTS1 P94/RXD1/TXD1 RESET DVSS
TMP91FU62
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TMP91FU62
Block Diagram
Figure Block Diagram
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TMP91FU62
Names Functions
Table Names Functions(1/3)
Input Output
Name
Number
Functions
P00-P07 P10-P17 TB3IN0 INT3 SDA0 TB3IN1 INT4 SCL0 TB3OUT0 TB3OUT1 SCOUT TXD2 RXD2 RXD2 TXD2 SCLK2 CTS2 P50-57 AN0-AN7 P60-67 AN8-AN15 TA0IN TA1OUT TA4IN TA5OUT INT0 TB0IN0 INT5
Port port that allows selected level (large-current port) Port port that allows selected level Port port 16-bit timer input 0:Timer count/capture trigger Input Interrupt Request Interrupt request with programmable rising edge falling edge. Serial interface data Mode. Port port 16-bit timer input 1:Timer count/capture trigger Input Interrupt Request Interrupt request rising edge Serial interface clock Mode. Port port 16-bit timer output Timer Output Port port 16-bit timer output Timer Output Port port (with pull-up resistor) System Clock Output: Outputs fSYS clock. Port port (with pull-up resistor) Serial Send Data Serial Receive Data Port port (with pull-up resistor) Serial Receive Data Serial Send Data Port port (with pull-up resistor) Serial Clock Serial Data Send Enable (Clear Send) Port port Analog input: used input converter Port port Analog input: used input converter Port port 8-bit timer input: Timer Input Port port 8-bit timer output:Timer Output Port port Port port 8-bit timer input: Timer Input Port port 8-bit timer output:Timer Output Port port Interrupt Request Interrupt request with programmable level rising edge falling edge. Port port 16-bit timer input 0:Timer count/capture trigger Input Interrupt Request Interrupt request with programmable rising edge falling edge.
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Table Names Functions(2/3)
Input Output
Name
Number
Functions
TB0IN1 INT6 TB0OUT0 TB0OUT1 TB1IN0 INT7 TB1IN1 INT8 TB1OUT0 TB1OUT1 TXD0 RXD0 RXD0 TXD0 SCLK0 CTS0 TXD1 RXD1 RXD1 TXD1 SCLK1 CTS1 TB2IN0 INT1 TB2IN1 INT2 TB2OUT0 TB2OUT1
Port port 16-bit timer input 1:Timer count/capture trigger Input Interrupt Request Interrupt request rising edge Port port 16-bit timer output Timer Output Port port 16-bit timer output Timer Output Port port 16-bit timer input 0:Timer count/capture trigger Input Interrupt Request Interrupt request with programmable rising edge falling edge. Port port 16-bit timer input 1:Timer count/capture trigger Input Interrupt Request Interrupt request rising edge Port port 16-bit timer output Timer Output Port port 16-bit timer output Timer Output Port port Serial Send Data Serial Receive Data Port port Serial Receive Data Serial Send Data Port port Serial Clock Serial Data Send Enable (Clear Send) Port port Serial Send Data Serial Receive Data Port port Serial Receive Data Serial Send Data Port port Serial Clock Serial Data Send Enable (Clear Send) Port port Low-frequency oscillator connection Port port Low-frequency oscillator connection Port port 16-bit timer input 0:Timer count/capture trigger Input Interrupt Request Interrupt request with programmable rising edge falling edge. Port port 16-bit timer input 1:Timer count/capture trigger Input Interrupt Request Interrupt request rising edge Port port 16-bit timer output Timer Output Port port 16-bit timer output Timer Output
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Table Names Functions(3/3)
Input Output
Name
Number
Functions
PB0-PB2
Port port that allows selected level Operation mode:Fixed "1", "1". Single Boot mode:Fixed "0", "1". Programmer mode:Fixed "1", "0". Open Reset: initializes TMP91FU62. (with pull-up resistor) Power supply converter converter
AM0-1
EMU0 RESET AVCC AVSS X1/X2 DVCC DVSS
High frequency oscillator connection pins Power supply pins (All DVCC pins should connected with power supply pin.) pins (All DVSS pins should connected with (0V) pin.)
Note: pins that have built-in pull-up resistors (other than RESET pin) disconnected from built-in pull-up resistor software.
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TMP91FU62 incorporates high-performance 16-bit (The 900/L1-CPU). operation, "TLCS-900/L1 CPU". following describe unique function used TMP91FU62; these functions covered TLCS-900/L1 section.
RESET
When resetting TMP91FU62 microcontroller, ensure that power supply voltage within operating voltage range, that internal high-frequency oscillator stabilized. Then hold RESET input level least system clocks (1us MHz). Thus, when turn switch, power supply voltage within operating voltage range, that internal high-frequency oscillator stabilized. Then hold RESET input level least system clocks. means that system clock mode fSYS fc/2. When reset accept, CPU: Sets follows program counter (PC) accordance with reset vector stored address FFFF00H FFFF02H: (7:0) (15:8) Value FFFF00H address Value FFFF01H address
(23:16) Value FFFF02H address Sets stack pointer (XSP) 100H. Sets bits<IFF2:0> status register (SR) (Sets interrupt level mask register level Sets <MAX> status register (SR) (MAX mode). Clears bits<RFP2:0> status register (SR) (Sets register bank When reset released, starts executing instructions accordance with program counter settings. internal registers mentioned above change when reset released. When reset accepted, sets internal I/O, ports, other pins follows. Initializes internal registers. Sets port pins, including pins that also internal I/O, general-purpose input output port mode. Sets high impedance.
Note internal register (except CPU) internal data change resetting. Note necessary re-set stack pointer user program.
Figure reset timing chart TMP91FU62.
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fFPH
Sampling Sampling
RESET
Figure TMP91FU62 Reset Timing Chart
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(input mode) (input mode)
P40~P43
P07, P33, P67, P87, PA3,
TMP91FU62
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Memory
Figure memory TMP91FU62.
000000H
Internal Kbytes)
000100H 001000H Internal Kbytes)
Kbyte area (nn)
002000H 010000H
FE8000H
Kbyte
16-Mbyte area (-R) (R+) R8/16) d8/16) (nnn)
FFFF00H FFFFFFH
Figure TMP91FU62 Memory
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System Clock Function Standby Control
TMP91FU62 contains clock gear, stand-by controller noise-reduction circuit. used low-noise systems. clock operating modes follows: Single clock mode pins only), Dual clock mode (X1,X2,XT1 pins). Figure shows transition figure.
(fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
NORMAL mode (fOSCH /gear value/2)
STOP mode
(Stops circuits)
Single clock mode transition figure
(fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
NORMAL mode (fOSCH /gear value/2)
STOP mode
(Stops circuits)
IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
SLOW mode (fs/2) Dual clock mode transition figure
Figure TMP91FU62 Clock Operating Mode
Note: clock frequency input from pins called fOSCH clock frequency input from pins called clock frequency selected SYSCR1<SYSCK> called fFPH. system clock fSYSis defined divided clock fFPH, cycle fSYS regret state.
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TMP91FU62 2.3.1 Block Diagram System Clock
SYSCR0<WUEF> SYSCR2<WUPTM1:0> Warm-up timer (for high/low frequency oscillator) SYSCR0 <PRCK1> fc/16 fFPH
SYSCR0 <XTEN, RXTEN>
Lowfrequency oscillator
fFPH fc/2 fc/4 fc/8
fc/16
fSYS
SYSCR0 <XEN, RXEN>
Highfrequency oscillator
SYSCR1<SYSCK>
SYSCR1<GEAR2:0>
fOSCH
fSYS TMRA01 TMRA45 Prescaler
TMRB0 toTMRB3 Prescaler port SIO0 SIO2 Prescaler
SBI0 Prescaler
Binary counter
SYSCR2<SCOSEL>
Figure Block Diagram System Clock
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2.3.2
Table
System Clock
Symbol Read/Write After reset XTEN RXEN RXTEN Warm-up timer control Write: Don't care Write: Start warmup Read: warmup Read: warm-up GEAR2 RSYSCK WUEF PRCK1
SYSCR0 (00E0H) Function
Highfrequency oscillator 0:Stop 1:Oscillation
Lowfrequency oscillator 0:Stop 1:Oscillation
Highfrequency oscillator (fc) after release STOP mode 0:Stop 1:Oscillation
Lowfrequency oscillator (fs) after release STOP mode 0:Stop 1:Oscillation
Selects clock after release STOP mode 0:fc 1:fs
Select prescaler clock 0:fFPH 1:fc/16
Symbol Read/Write After reset
SYSCK
GEAR1
GEAR0
SYSCR1 (00E1H) Function
Select system clock
Select gear value high frequency (fc) 000:fc 001:fc/2 010:fc/4 011:fc/8 100:fc/16 101:reserved 110:reserved 111:reserved HALTM0
Symbol Read/Write After reset SYSCR2 (00E2H) Function
SCOSEL
WUPTM1
WUPTM0
HALTM1
DRVE state control STOP mode Remains state before HALT
Select SCOUT 0:fs 1:fSYS
Select warm-up time oscillator 00:218/inputted frequency 01:28/inputted frequency 10:214/inputted frequency 11:216/inputted frequency
HALT mode 00:reserved 01:STOP mode 10:IDLE1 mode 11:IDLE2 mode
Note Don't care Note SYSCR0<bit0>,SYSCR1<bit 7:4>,SYSCR2<bit7,bit1> read undefined value. Note serial channels SIO0, SIO1 SIO2, baud rate generator unavailable input clock interface clock serial transfer prescaler clock fc/16 when SYSCR0<PRCK1> "1".
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2.3.3
System Clock Controller
system clock controller generates system clock signal (fSYS) core internal I/O.It contains oscillation circuits clock gear circuit high-frequency (fc) operation. register SYSCR1<SYSCK> changes system clock either SYSCR0<XEN> SYSCR0<XTEN> control enabling disabling each oscillator, SYSCR1<GEAR2:0> sets high-frequency clock gear either (fc, fc/2, fc/4, fc/8 fc/16). These functions reduce power consumption equipment which device installed. combination settings <XEN> "1", <XTEN> "0", <SYSCK> <GEAR2:0> "000" will cause system clock (fSYS) fc/2 (=fc 1/2) after Reset. example, fSYS when oscillator connected pins. Switching from NORMAL mode SLOW mode When resonator connected pins, pins, warm-up timer used change operation frequency after stable oscillation been attained. warm-up time selected using SYSCR2<WUPTM1:0>. This warm-up timer programmed start stop shown following examples Table shows warm-up time.
Note When using oscillator (other than resonator) with stable oscillation, warm-up timer needed. Note warm-up timer operated oscillation clock. Hence, there some variation warm-up time. Note Note using low-frequency oscillator When connect low-frequency oscillator ports need below setting consumption power. (Case resonators) P9CR<P96C, P97C> "11", P9<P96:97> "00" (Case oscillator) P9CR<P96C, P97C> "11", P9<P96:97> "10"
Table Warm-up Times (when changing clock)
Select Warm-up Time SYSCR2<WUPTM1:0> 01(28/frequency) 10(214/frequency) 11(216/frequency) 00(218/frequency) Change NORMAL (fc) 12.8[us] 0.819[ms] 3.277[ms] 13.107[ms] Change SLOW (fs) 7.8[ms] 500[ms] 2000[ms] 8000[ms]
Note: fOSCH=20MHzfs=32.768kHz
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Example Changing from high frequency (fc) frequency (fs). SYSCR0 SYSCR1 SYSCR2 WUP: 00E0H 00E1H 00E2H (SYSCR2),X-11-X-B 6,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 7,(SYSCR0)
Detects stopping warm-up timer. Sets warm-up time 216/fs. Enables low-frequency oscillation. Clears starts warm-up timer.
Changes fSYS from Disables high-frequency oscillation.
Note: Don't care, -:No change
<XEN> pins <XTEN> pins
Counts fSYS
Counts
<SYSCK> fSYS
Figure Changing from high frequency (fc) frequency (fs)
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Example Changing from frequency (fs) high frequency (fc).
SYSCR0 SYSCR1 SYSCR2 WUP: 00E0H 00E1H 00E2H (SYSCR2),X-10-X-B 7,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 6,(SYSCR0) Detects stopping warm-up timer. Changes fSYS from Disables low-frequency oscillation. Sets warm-up time 214/fc. Enables high-frequency oscillation. Clears starts warm-up timer.
Note: Don't care, -:No change
<XEN> pins <XTEN> pins Counts fSYS
Counts
<SYSCK> fSYS
Figure Changing from frequency (fs) high frequency (fc)
Clock gear controller When high-frequency clock selected setting SYSCR1<SYSCK> "0", fFPH according contents clock gear select register SYSCR1<GEAR2:0> either fc/2, fc/4, fc/8 fc/16. Using clock gear select lower value fFPH reduces power consumption. Below show example changing clock gear.
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Example Changing clock gear SYSCR1 X:Don't care (Clock gear changing) change clock gear, write register value SYSCR1<GEAR2:0> register. necessary warm-up time until changing after writing register value. There possibility that instruction next clock gear changing instruction executed clock gear before changing. execute instruction next clock gear switching instruction clock gear after changing, input dummy instruction follows (instruction execute write cycle). 00E1H (SYSCR1),XXXX0000B
Changes fSYS fc/2.
SYSCR1
00E1H (SYSCR1),XXXX0000B (DUMMY),00H Changes fSYS fc/2. Dummy instruction
Instruction executed after clock gear changed.
(3)Internal clock output fSYS internal clock driven from P40/SCOUT pin. P40/SCOUT configured SCOUT (System clock output) programming port registers follows: P4CR<P40C> P4FC<P40F> "1". output clock selected through SYSCR2<SCOSEL> bit. Table shows states each clocking mode when P40/SCOUT configured SCOUT. Table SCOUT Output States
HALT mode NORMAL SLOW IDLE2 <SCOSEL>="0" <SCOSEL>="1" clock driven out. fSYS clock driven out. IDLE1 STOP HOLD either
2.3.4
Prescaler Clock Controller
internal (TMRA01 TMRA45, TMRB0 TMRB3, SIO0 SIO2, SBI0) there prescaler which divide clock. clock input prescaler either clock fFPH divided clock fc/16 divided setting SYSCR0<PRCK1> register determines which clock signal input.
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2.3.5
Runaway provision with protection register
(Purpose) Provision runaway program noise mixing. Write operation specified prohibited that provision program runaway prevents that state which fetch impossibility stopping clock, memory control register (CS/WAIT controller) changed.
Specified list
Clock gear (write enable only EMCCR1) SYSCR0, SYSCR1, SYSCR2
(Block diagram)
EMCCR0<PROTECT>
Write signal
(Setting method) writing except "1FH" code EMCCR1 register, become protect this operation, write operation specified disabling. writing "1FH" EMCCR1 register, become protect OFF. State protect confirm reading EMCCR0<PROTECT>. Table EMCCR
Symbol Read/Write EMCCR0 (00E3H) After reset PROTECT Protect flag
Function
Write "0".
Write "1".
Write "0".
Write "0".
Write "0".
Write "1".
Write "1".
Symbol EMCCR1 (00E4H) Read/Write After reset Function Protect writing "1FH". Protect writing except "1FH".
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2.3.6
Standby Controller
(1)HALT modes When HALT instruction executed, operating mode switches IDLE2, IDLE1 STOP mode, depending contents SYSCR2<HALTM1:0> register. subsequent actions performed each mode follows: IDLE2: Only halts. internal available select operation during IDLE2 mode setting following register. Shows registers setting operation during IDLE2 mode. Table Setting Operation during IDLE2 Mode
Internal TMRA01 TMRA45 TMRB0 TMRB1 TMRB2 TMRB3 TA01RUN<I2TA01> TA45RUN<I2TA45> TB0RUN<I2TB0> TB1RUN<I2TB1> TB2RUN<I2TB2> TB3RUN<I2TB3> Internal SIO0 SIO1 SIO2 SBI0 SC0MOD1<I2S0> SC1MOD1<I2S1> SC2MOD1<I2S2> SBI0BR<I2SBI0> ADCCR2<I2AD> WDMOD<I2WDT>
IDLE1: Only oscillator (Real time clock) continue operate. STOP: internal circuits stop operating. operation each different HALT modes described Table 2-6. Table Operation during HALT Modes
HALT mode SYSCR2<HALTM1:0> port TMRA,TMRB Block SIO,SBI Available select operation block Operate enable IDLE2 IDLE1 STOP
Stop
Keep state when HALT instruction executed.
Table
Stop
Interrupt controller Operate
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(2)How release HALT mode These halt states released resetting requesting interrupt. halt release sources determined combination between states interrupt mask register <IFF2:0> HALT modes. details releasing halt status shown Table 2-7. Released requesting interrupt operating released from HALT mode depends interrupt enabled status. When interrupt request level before executing HALT instruction exceeds value interrupt mask register, interrupt source processed after releasing HALT mode, status executing instruction that follows HALT instruction. When interrupt request level before executing HALT instruction less than value interrupt mask register, releasing HALT mode executed. non-maskable interrupts, interrupt processing processed after releasing HALT mode regardless value mask register.) However only INT0 interrupts, even interrupt request level before executing HALT instruction less than value interrupt mask register, releasing HALT mode executed. this case, interrupt processing, starts executing instruction next HALT instruction, interrupt request flag held "1".
Note:Usually, interrupts release halts status. However, interrupts (INT0, INTRTC) which release HALT mode able they input during period shifting HALT mode (for about clocks fFPH) with IDLE1 STOP mode (IDLE2 applicable this case). this case, interrupt request kept hold internally.) another interrupt generated after shifted HALT mode completely, halt status released without difficulty. priority this interrupt compared with that interrupt kept hold internally, interrupt with higher priority handled first followed other interrupt.
Releasing resetting Releasing halt status executed resetting. When STOP mode released RESET, necessary enough resetting time (See Table 2-6)to operation oscillator stable. When releasing HALT mode resetting, internal data keeps state before "HALT" instruction executed. However other settings contents initialized. (Releasing interrupts keeps state before "HALT" instruction executed.)
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Table Source Halt State Clearance Halt Clearance Operation
Status Received Interrupt
Interrupt Enable (Interrupt level) IDLE2
(Interrupt mask)
STOP
Interrupt Disable (Interrupt level) (Interrupt mask) IDLE2 IDLE1 STOP
HALT mode
INTWDT INT0(Note
IDLE1
(Note
Source Halt state clearance
INTRTC INT1-INT8
Interrupt
INTTA0, INTTA1, INTTA4, INTTA5 INTTB00-30, INTTB01-31 INTTB0F0-3 INTRX0-INTRX2, INTTX0-INTTX2 INTSBI0 INTAD RESET
Initialize
:After clearing HALT mode, starts interrupt processing. :After clearing HALT mode, resumes executing starting from instruction following HALT instruction. (Interrupt routine don't execute.) used release HALT mode. :The priority level (Interrupt request level) non-maskable interrupts fixed highest priority level. There this combination type. *1:Releasing HALT mode executed after passing warm-up time.
Note When HALT mode cleared INT0 interrupt level mode interrupt enabled status, hold high level until starting interrupt process. level before interrupt process stared, interrupt process started correctly. Note using external interrupt INT1 INT8 IDLE2 mode, 16-bit timer register TB0RUN<I2TB0>, TB1RUN<I2TB1>, TB2RUN<I2TB2>, TB3RUN<I2TB3> "1".
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Example:Clearing halt state INT0 interrupt clears halt state when device IDLE1 mode.
8203H 8206H 8209H 820BH 820EH INT0
HALT
(IIMC), (INTE0AD), (SYSCR2),
Selects INT0 interrupt rising edge. Sets INT0 interrupt level Sets interrupt level Sets HALT mode IDLE1 mode. Halts CPU. INT0 interrupt routine RETI
820FH
(3)Operation IDLE2 mode IDLE2 mode only specific internal operations, designated IDLE2 setting register, take place. Instruction execution stops. Figure illustrates example timing clearance IDLE2 mode halt state interrupt.
A0~A23
IDLE2
Figure Timing Chart IDLE2 Mode Halt State Cleared Interrupt
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IDLE1 mode IDLE1 mode, only internal oscillator continue operate. system clock stops. halt state, interrupt request sampled asynchronously with system clock; however, clearance Halt state (e.g., restart operation) synchronous with Figure illustrates timing clearance IDLE1 mode halt state interrupt.
A0A23
IDLE1 mode
Figure Timing Chart IDLE1 Mode Halt State Cleared Interrupt
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STOP mode When STOP mode selected, internal circuits stop, including internal oscillator. status STOP mode depends settings SYSCR2<DRVE> register. Table summarizes state these pins STOP mode. After STOP mode been cleared, system clock output starts when warm-up time elapsed, order allow oscillation stabilize. After STOP mode been cleared, either NORMAL mode SLOW mode selected using SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> <RXTEN> must set. sample warm-up times Table 2-8. Figure illustrates timing clearance STOP mode halt state interrupt.
A0A23
STOP
Figure Timing Chart STOP Mode Halt State Cleared Interrupt
Table Sample Warm-up Times after Clearance STOP Mode SYSCR0 <RSYSCK> 0(fc) 1(fs) SYSCR2<WUPTM1:0> 01(28) 12.8us 7.8ms 10(214) 0.819ms 500ms 11(216) 3.277ms 2000ms 00(218) 13.107ms 8000ms
Note: fOSCH=20MHz, fs=32.768kHz
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Example: "The STOP mode entered when low-frequency operates, high-frequency operates after releasing INT0.
SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H
INT0
HALT
00E0H 00E1H 00E2H (SYSCR1), (SYSCR2), X-1001X1B (SYSCR0), 011000
fSYS fs/2 214/fOSCH
INT0
9006H
change
RETI
Note:When different modes used before after STOP mode above mentioned, there possible release HALT mode without changing operation mode acceptance halt release interrupt request during execution "HALT" instruction (during state). system which accepts interrupts during execution "HALT" instruction, same operation mode before after STOP mode.
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Table Input/output Buffer State Table Port Name
P00-07
Input Output
input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode analog input input mode output mode analog input input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input input input output
<DRVE>=0
input input input level output
<DRVE>=1
output output output output output output input output input output output output output output input input level output
P10-17
P30-33
P40-43
P50-57
P60-67
P70-74
P80-87
P90-97
PA0-A3
PB0-B2 RESET AM0,AM1
Input input mode input pins invalid; output mode output high impedance.
input: Input gate operation. input voltage that input stays constant. output: Output state PU*: Programmable pull-up pin. Input gate disable state. through current even high impedance.
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TMP91FU62
Interrupts
Interrupts controlled interrupt mask register SR<IFF2:0> built-in interrupt controller. TMP91FU62 total interrupts divided into following three types:
Interrupts generated CPU: sources (Software interrupts, illegal instruction interrupt) Interrupts external pins INT0 INT8): sources Internal interrupts: sources
(fixed) individual interrupt vector number assigned each interrupt. (Variable) priority level assigned each maskable interrupt. priority level non-maskable interrupts fixed highest level. When interrupt generated, interrupt controller sends priority that interrupt CPU. multiple interrupts generated simultaneously, interrupt controller sends interrupt with highest priority CPU. (The highest priority level using non-maskable interrupts.) compares priority level interrupt with value interrupt mask register <IFF2:0>. priority level interrupt higher than value interrupt mask register, accepts interrupt. interrupt mask register <IFF2:0> value updated using value instruction ("EI num" sets <IFF2:0> data num). example, specifying "EI3" enables maskable interrupts which priority level interrupt controller higher, also non-maskable interrupts. Operationally, instruction (<IFF2:0> "7") identical "EI7" instruction. instruction used disable maskable interrupts because priority level maskable interrupts instruction valid immediately after execution. addition above general-purpose interrupt processing mode, TLCS-900/L1 micro interrupt processing mode well. transfer data (1/2/4 bytes) automatically micro mode, therefore this mode used speed-up interrupt processing, such transferring data internal external peripheral Moreover, TMP91FU62 software start function micro processing request software hardware interrupt. Figure shows overall interrupt processing flow.
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Interrupt processing
Interrupt specified micro start vector?
Micro soft start request
Clear interrupt request flag
Interrupt vector value read Interrupt request clear
General-purpose interrupt processing
Data transfer micro
PUSH PUSH SR<IFF2:0> INTNEST
Level accepted interrupt INTNEST
Count
Count
Micro processing
(FFFF00H
Count
Clear vector register generating micro transfer interrupt (INTTC0 INTTC3)
Interrupt processing program
RETI instruction INTNEST INTNEST
Figure Overall Interrupt Processing Flow
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TMP91FU62
General-purpose Interrupt Processing
When accepts interrupt, usually performs following sequence operations. That also same TLCS-900/L TLCS-900/H. reads interrupt vector from interrupt controller. same level interrupts occur simultaneously, interrupt controller generates interrupt vector accordance with default priority clears interrupt request. (The default priority already fixed each interrupt. smaller vector value higher priority level.) pushes value program counter (PC) status register (SR) onto stack area (Indicated XSP). sets value which priority level accepted interrupt plus (+1) interrupt mask register <IFF2:0>. However, priority level accepted interrupt register's value increases interrupt nesting counter INTNEST (+1). jumps address indicated data address "FFFF00H Interrupt vector" starts interrupt processing routine. above processing time states (1.8 MHz) best case (16-bit data width waits). When completed interrupt processing, RETI instruction return main routine. RETI restores contents program counter (PC) status register (SR) from stack decreases interrupt nesting counter INTNEST (-1). Non-maskable interrupts cannot disabled user program. Maskable interrupts, however, enabled disabled user program. program priority level each interrupt source. priority level setting will disable interrupt request.) interrupt request which priority level equal greater than value interrupt mask register <IFF2:0> comes out, accepts interrupt. Then, interrupt mask register <IFF2:0> value priority level accepted interrupt plus (+1). Therefore, interrupt generated with higher level than current interrupt during processing, accepts later interrupt goes nesting status interrupt processing. Moreover, receives another interrupt request while performing said processing steps current interrupt, latest interrupt request sampled immediately after execution first instruction current interrupt processing routine. Specifying start instruction disables maskable interrupt nesting. reset initializes interrupt mask register <IFF2:0> "111", disabling maskable interrupts. Table shows TMP91FU62 interrupt vectors micro start vectors. address FFFF00H FFFFFFH (256 bytes) assigned interrupt vector area.
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Table TMP91FU62 Interrupt Vectors Table(1/2)
Default Priority Maskable (Reserved) (Reserved) INTTA4: 8-bit timer INTTA5: 8-bit timer INTTB00: 16-bit timer (TB0RG0) INTTB01: 16-bit timer (TB0RG1) INTTB10: 16-bit timer (TB1RG0) INTTB11: 16-bit timer (TB1RG1) INTTB20: 16-bit timer (TB2RG0) INTTB21: 16-bit timer (TB2RG1) INTTB30: 16-bit timer (TB3RG0) INTTB31: 16-bit timer (TB3RG1) (Reserved) (Reserved) 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H Nonmaskable Type Interrupt Source Source Micro Request "Reset" "SWI instruction "SWI instruction INTUNDEF: Illegal instruction "SWI instruction "SWI instruction "SWI instruction "SWI instruction "SWI instruction "SWI instruction (Reserved) INTWD: Watchdog timer Micro (MDMA) INT0: INT0 INT1: INT1 INT2: INT2 INT3: INT3 INT4: INT4 INT5: INT5 INT6: INT6 INT7: INT7 INT8: INT8 (Reserved) (Reserved) INTTA0: 8-bit timer INTTA1: 8-bit timer Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H Micro Start Vector
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Table TMP91FU62 Interrupt Vectors Table(2/2)
Default Priority Maskable Type Interrupt Source Source Micro Request INTTBOF0: 16-bit timer (Over flow) INTTBOF1: 16-bit timer (Over flow) INTTBOF2: 16-bit timer (Over flow) INTTBOF3: 16-bit timer (Over flow) (Reserved) INTRX0:Serial reception (Channel INTTX0:Serial transmission (Channel INTRX1:Serial reception (Channel INTTX1:Serial transmission (Channel INTRX2:Serial reception (Channel INTTX2:Serial transmission (Channel INTSBI0:Serial interface interrupt (Channel (Reserved) INTRTC: Interrupt special timer CLOCK INTAD: conversion INTTC0 Micro (Channel INTTC1: Micro (Channel INTTC2: Micro (Channel INTTC3: Micro (Channel (Reserved) (Reserved) Vector Value 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00FCH Vector Reference Address FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFFCH Micro Start Vector
Note: Micro default priority: Micro stands prior other maskable interrupt.
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TMP91FU62
Micro Processing
addition general-purpose interrupt processing, TMP91FU62 supports micro function. Interrupt requests micro perform micro processing highest priority level (Level among maskable interrupts, regardless priority level particular interrupt source. micro channels possible continuous transmission specifying described later burst mode. micro channels possible continuous transmission specifying described later burst mode. Because micro function been implemented with cooperative operation CPU, when goes standby mode (STOP, IDLE1 IDLE2) HALT instruction, requirement micro will ignored (Pending) transfer started after release HALT.
3.2.1
Micro Operation
When interrupt request specified micro start vector register generated, micro triggers micro request interrupt priority level starts processing request spite interrupt source's level. micro ignored <IFF2:0> "7". micro channels allow micro processing types interrupts time. When micro accepted, interrupt request flip-flop assigned that channel cleared. data automatically transferred once (1/2/4 bytes) from transfer source address transfer destination address control register, transfer counter decreased (-1). decreased result "0", micro transfer interrupt (INTTC0 INTTC3) passes from interrupt controller. addition, micro start vector register DMAnV cleared next micro disabled micro processing completes. decreased result other than "0", micro processing completes does specify described later burst mode. this case, micro transfer interrupt (INTTC0 INTTC3) aren't generated. interrupt request triggered interrupt source during interval between clearing micro start vector next setting, general-purpose interrupt processing executes interrupt level set. Therefore, only using interrupt starting micro (Not using interrupts general-purpose interrupt: Level first interrupts level (Interrupt requests disabled). using micro general-purpose interrupts together, first level interrupt used start micro processing lower than other interrupt levels. (Note) this case, cause general interrupt limited edge interrupt. priority micro transfer interrupt (INTTC0 INTTC3) defined interrupt level default priority same other maskable interrupt. micro request more than channel same time, priority based interrupt priority level channel number. smaller channel number higher priority (Channel (High) Channel (Low)). While register setting transfer source/transfer destination addresses 32-bit control register, this register only effectively output 24-bit addresses. Accordingly, micro access Mbytes (The upper eight bits bits valid).
Note:If priority level micro higher than that other interrupts, operates follows. case INTxxx interrupt generated first then INTyyy interrupt generated between checking "Interrupt specified micro start vector" Figure 3-1) reading interrupt vector with setting below, vector shifts that INTyyy time. This because priority level INTyyy higher than that INTxxx. interrupt routine, reads vector INTyyy because checking micro been finished. INTyyy generated regardless transfer counter micro DMA. INTxxx: level without micro INTyyy: level with micro
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Three micro transfer modes supported: 1-byte transfer, 2-byte (One-word) transfer, 4-byte transfer. After transfer mode, transfer source/destination addresses increased, decreased, remain unchanged. This simplifies transfer data from memory, from memory I/O, from I/O. details transfer modes, see" 3.2.4 Detailed Description Transfer Mode Register transfer counter 16-bit counter, micro processing 65536 times interrupt source. (The micro processing count maximized when transfer counter initial value 0000H.) Micro processing started interrupts shown micro start vectors Table micro soft start, making total interrupts. Figure shows word transfer micro cycle transfer destination address mode (except counter mode, same other modes). (The conditions this cycle based external 16-bit bus, waits, transfer source/transfer destination addresses both even-numberd values).
state (Note (Note
Transfer destination address
Transfer source address
Input
Output
Figure Timing Micro Cycle
States Instruction fetch cycle (Gets next address code). bytes more instruction codes inserted instruction queue buffer, this cycle becomes dummy cycle. States Micro read cycle State Dummy cycle (The address remains unchanged from state
States Micro write cycle
Note source address area 8-bit bus, increased states. source address area 16-bit address starts from number, increased states. Note destination address area 8-bit bus, increased states. destination address area 16-bit address starts from number, increased states.
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3.2.2
Soft Start Function
addition starting micro function interrupts, TMP91FU62 includes micro software start function that starts micro generation write cycle DMAR register. Writing each DMAR register causes micro once write each bit, micro doesn't operate) transfer, corresponding DMAR register automatically cleared "0". Only one-channel once micro DMA. write plural bits.) When writing again DMAR register, check whether before writing "1". read "1", micro transfer isn't started yet. When burst specified DMAB register, data continuously transferred until value micro transfer counter after start micro DMA. execute soft start during micro transfer interrupt source, micro transfer counter doesn't change. Don't Read-modify-write instruction avoid writing other bits mistake.
Symbol
Name
Address
DMAR3
DMAR2
DMAR1
DMAR0
DMAR
Request Register
instructions prohibited.
request
3.2.3
Transfer Control Registers
transfer source address transfer destination address following registers CPU. Data setting these registers done "LDC instruction.
Channel
DMAS0 DMAD0 DMAC0 DMAM0
source address register Only bits destination address register Only bits counter register 65536 mode register
Channel
DMAS3 DMAD3 DMAC3 DMAM3
source address register destination address register counter register mode register
bits bits bits
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TMP91FU62 3.2.4 Detailed Description Transfer Mode Register
(DMAM0 DMAM3)
Mode
Note: upper three data programmed these registers must always Execution time
Byte transfer, Word transfer, 4-byte transfer, Reserved Transfer destination address modeI/O memory (DMADn+) (DMASn) DMACn DMACn DMACn then INTTC generated Transfer destination address mode memory (DMADn-) (DMASn) DMACn DMACn DMACn then INTTC generated Transfer source address modememory (DMADn) (DMASn+) DMACn DMACn DMACn then INTTC generated Transfer source address mode memory (DMADn) (DMASn-) DMACn DMACn DMACn then INTTC generated Address fixed modeI/O (DMADn) (DMASn) DMACn DMACn DMACn then INTTC generated Counter mode counting number times interrupt generated DMASn DMASn DMACn DMACn DMACn then INTTC generated states (800 byte/word transfer states (1200 4-byte/word transfer states (800 byte/word transfer states (1200 4-byte/word transfer states (800 byte/word transfer states (1200 4-byte/word transfer states (800 byte/word transfer states (1200 4-byte/word transfer states (800 byte/word transfer states (1200 4-byte/word transfer states (500
Note corresponding micro channels DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer) I/Os table mean fixed address memory means increment (INC) decrement (DEC) addresses. Note Execution time under condition 16-bit width (Both transfer destination address area)/0 waits/ MHz/selected high-frequency mode Note undefined code transfer mode register except defined codes listed above table.
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Interrupt Controller Operation
block diagram Figure shows interrupt circuits. left-hand side diagram shows interrupt controller circuit. right-hand side shows interrupt request signal circuit halt release circuit. interrupt controller there interrupt request flag (Consisting flip-flop), interrupt priority setting register micro start vector register. interrupt request flag latches interrupt requests from peripherals. flag cleared following cases: When reset occurs When reads channel vector after accepted interrupt When executing instruction that clears interrupt (Write start vector INTCLR register) When receives micro request (when micro set) When micro burst transfer terminated interrupt priority independently each interrupt source writing priority interrupt priority setting register (e.g., INTE0AD INTE56). interrupt priorities levels provided. Setting interrupt source's priority level disables interrupt requests from that source. priority non-maskable interrupts (watchdog timer interrupts) fixed interrupt request with same level generated same time, default priority used determine which interrupt request accepted first. bits interrupt priority setting register indicate state interrupt request flag thus whether interrupt request given channel occurred. interrupt controller sends interrupt request vector address CPU. compares priority value <IFF2:0> status register interrupt request signal with priority value set; latter higher, interrupt accepted. Then sets value higher than priority value (+1) SR<IFF2:0>. Interrupt request where priority value equals higher than value accepted simultaneously during previous interrupt routine. When interrupt processing completed (after execution RETI instruction), restores priority value saved stack before interrupt generated SR<IFF2:0>. interrupt controller also registers channels) used store micro start vector. Writing start vector interrupt source micro processing beforehand (see Table 3-1), enables corresponding interrupt processed micro processing. values must micro parameter register (e.g., DMAS DMAD) prior micro processing.
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Interrupt controller
Interrupt request
RESET Interrupt vector read
IFF2:0
Interrupt request signal INTRQ2 INTRQ0 Priority encoder RESET
Interrupt mask
INTWD
Decoder
Priority setting register
Dn+1 Dn+2 Interrupt level detect
Interrupt vector read INTRQ2 then IFF2
Interrupt request
Dn+3 Highest priority interrupt level select
Interrupt request signal
INT0
Interrupt request
RESET
Interrupt vector read Micro acknowledge
Interrupt vector generator
Figure Block Diagram Interrupt Controller
Page
Software start input
INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8
During IDLE1 During STOP
Halt release RESET INT0, INTRTC
Micro counter zero interrupt
INTAD INTTC0 INTTC1 INTTC2 INTTC3
Micro request then
Selector
Micro start vector setting register
Micro channel priority encoder
Micro channel specification
TMP91FU62
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INTTC0
DMA0V DMA1V DMA2V DMA3V
RESET
TMP91FU62 3.3.1 Interrupt Level Setting Registers
Interrupt Level Setting Registers
Symbol Name Address INTAD INTE0AD INT0 INTAD enable IADC INT2 INTE12 INT1 INT2 enable INT4 INTE34 INT3 INT4 enable INT6 INTE56 INT5 INT6 enable INT8 INTE78 INT7 INT8 enable I8M2 I8M1 I8M0 I7M2 INT7 I7M1 I7M0 I6M2 I6M1 I6M0 I5M2 INT5 I5M1 I5M0 I4M2 I4M1 I4M0 I3M2 INT3 I3M1 I3M0 I2M2 I2M1 I2M0 I1M2 INT1 I1M1 I1M0 IADM2 IADM1 IADM0 I0M2 INT0 I0M1 I0M0
INTTA1(TMRA1) INTETA01 INTTA0 INTTA1 enable ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C
INTTA0 (TMRA0) ITA0M2 ITA0M1 ITA0M0
IxxxC Interrupt request flag
IxxM2
IxxM1
IxxM0
Function (Write) Disables interrupt requests Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Disables interrupt requests
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Interrupt Level Setting Registers
Symbol Name Address
INTTA5 (TMRA5) INTETA45 INTTA4 INTTA5 enable ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C
INTTA4 (TMRA4) ITA4M2 ITA4M1 ITA4M0
INTTB01(TMRB0) INTETB0 Interrupt enable TMRB0 ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C
INTTB00(TMRB0) ITB00M2 ITB00M1 ITB00M0
INTTB11(TMRB1) INTETB1 Interrupt enable TMRB1 ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C
INTTB10(TMRB1) ITB10M2 ITB10M1 ITB10M0
INTTB21(TMRB2) INTETB2 Interrupt enable TMRB2 ITB21C ITB21M2 ITB21M1 ITB21M0 ITB20C
INTTB20(TMRB2) ITB20M2 ITB20M1 ITB20M0
INTTB31(TMRB3) INTETB3 Interrupt enable TMRB3 ITB31C Interrupt enable TMRB0/1 (Over flow) ITB31M2 ITB31M1 ITB31M0 ITB30C
INTTB30(TMRB3) ITB30M2 ITB30M1 ITB30M0
INTTBOF1(TMRB1 Over flow) ITF1C ITF1M2 ITF1M1 ITF1M0 ITF0C INTETB01V
INTTBOF0(TMRB0 Over flow) ITF0M2 ITF0M1 ITF0M0
IxxxC Interrupt request flag
IxxM2
IxxM1
IxxM0
Function (Write) Disables interrupt requests Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Disables interrupt requests
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Interrupt Level Setting Registers
Symbol Name Interrupt enable TMRB2/3 (Over flow) Address
INTTBOF3(TMRB3 Over flow) ITF3C INTRTC INTERTC Interrupt enable INTRTC IRTCC INTTX0 INTES0 INTRX0 INTTX0 enable ITX0C INTTX1 INTES1 INTRX1 INTTX1 enable ITX1C INTTX2 INTES2 INTRX2 INTTX2 enable ITX2C INTESBI0 INTSBI0 enable INTTC1 INTETC01 INTTC0 INTTC1 enable ITC1C INTTC3 INTETC23 INTTC2 INTTC3 enable ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC1M2 ITC1M1 ITC1M0 ITC0C ISBI0C ITX2M2 ITX2M1 ITX2M0 IRX2C ITX1M2 ITX1M1 ITX1M0 IRX1C ITX0M2 ITX0M1 ITX0M0 IRX0C IRTCM2 IRTCM1 IRTCM0 ITF3M2 ITF3M1 ITF3M0 ITF2C INTETB23V
INTTBOF2(TMRB2 Over flow) ITF2M2 ITF2M1 INTRX0 IRX0M2 IRX0M1 INTRX1 IRX1M2 IRX1M1 INTRX2 IRX2M2 IRX2M1 INTSBI0 ISBI0M2 ISBI0M1 INTTC0 ITC0M2 ITC0M1 INTTC2 ITC2M2 ITC2M1 ITC2M0 ITC0M0 ISBI0M0 IRX2M0 IRX1M0 IRX0M0 ITF2M0
IxxxC Interrupt request flag
IxxM2
IxxM1
IxxM0
Function (Write) Disables interrupt requests Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Disables interrupt requests
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TMP91FU62 3.3.2 External Interrupt Control
External Interrupt Control Register (IIMC)
Symbol Name Address instructions prohibited. INT0 EDGE Rising Falling INT0 mode Edge Level I0EDGE I0LE
IIMC
Interrupt input mode control
Always write "0".
INT0 setting
P7FC<P75F> <IOLE> <IOEDGE> INT0 Rising edge interruption Falling edge interruption level level
3.3.3
Interrupt Request Flag Clear Register
interrupt request flag cleared writing appropriate micro start vector, given Table register INTCLR. example, clear interrupt flag INT0, perform following register operation after execution instruction. INTCLR 0AH: Clears interrupt request flag INT0.
Interrupt Request Flag Clear Register (INTCLR)
Symbol Name Address Interrupt Clear Control instructions prohibited. CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0
INTCLR
Interrupt vector
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3.3.4
Micro Start Vector Registers
This register assigns micro processing which interrupt source. interrupt source with micro start vector that matches vector this register assigned micro start source. When micro transfer counter value reaches micro transfer interrupt corresponding channel sent interrupt controller, micro start vector register cleared, micro start source channel cleared. Therefore, continue micro processing, micro start vector register again during processing micro transfer interrupt. same vector micro start vector registers more than channel, channel with lowest number higher priority. Accordingly, same vector micro start vector registers channels, interrupt generated channel with lower number executed until micro transfer complete. micro start vector this channel again, next micro started channel with higher number. (Micro chaining)
Micro Start Vector Registers (DMAnV)
Symbol Name Address DMA0 Start Vector DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0
DMA0V
DMA0 start vector DMA1 Start Vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0
DMA1V
DMA1 start vector DMA2 Start Vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0
DMA2V
DMA2 start vector DMA3 Start Vector DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0
DMA3V
DMA3 start vector
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3.3.5
Micro Burst Specification
Specifying micro burst continues micro transfer until transfer counter register reaches after micro start. Setting which corresponds micro channel DMAB registers mentioned below specifies burst. other interrupts (maskable/nonmaskable concerned) generated during burst transfer, interrupt executed after completed burst transfer.
Micro Burst Request Registers (DMAR)
Symbol Name Address Software Request Register instructions prohibited. DMAR3 DMAR2 DMAR1 DMAR0
DMAR
software request DMAB3 DMAB2 DMAB1 DMAB0
DMAB
Burst Register
burst request
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3.3.6
Attention Point
instruction execution unit interface unit this operate independently. Therefore, immediately before interrupt generated, fetches instruction that clears corresponding interrupt request flag, execute instruction that clears interrupt request flag (Note) between accepting reading interrupt vector. this case, reads default vector 0008H reads interrupt vector address FFFF08H. avoid above problem, place instructions that clear interrupt request flags after instruction. case setting interrupt enable again instruction after execution clearing instruction, execute instruction after clearing more than 1-instructions (ex. "NOP" times). executed instruction without waiting instruction after execution clearing instruction, interrupt will enable before request flag cleared. case changing value interrupt mask register <IFF2:0> execution instruction, disable interrupt instruction before execution instruction. addition, take care following circuits exceptional demand special attention.
level mode INT0 edge-triggered interrupt. Hence, level mode interrupt request flip-flop INT0 does function. peripheral interrupt request passes through input flip-flop becomes output. interrupt input mode changed from edge mode level mode, interrupt request flag cleared automatically. enters interrupt response sequence result INT0 going from INT0 must then held until interrupt response sequence been completed. INT0 level mode release halt state, INT0 must held from time INT0 changes from until halt state released. (Hence, necessary ensure that input noise interpreted causing INT0 revert before halt state been released.) When mode changes from level mode edge mode, interrupt request flags which were level mode will cleared. Interrupt request flags must cleared using following sequence. (IIMC), Switches interrupt input mode from level mode edge mode. (INTCLR), Clears interrupt request flag. Wait instruction interrupt request flip-flop only cleared reset reading serial channel receive buffer. cannot cleared writing INTCLR register.
INT0 level mode
INTRXn
Note: following instructions input state changes equivalent instructions that clear interrupt request flag. INT0: Instructions which switch level mode after interrupt request been generated edge mode. input change from high after interrupt request been generated level mode. INTRXn: Instruction which reads receive buffer.
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TMP91FU62
Port Function
TMP91FU62 features settings which relate various ports. well general-purpose port functionality, port pins also have functions which relate built-in internal I/Os. Table lists functions each port pin. Table lists functions each port pin. Table lists registers their specifications. Table Port Functions with programmable pull-up resistor) (1/2)
Port Names Port0 Port1 Names Port3 Port4 Port5 Port6 Port7 TA4IN TA5OUT INT0 RXD2, TXD2 SCLK2, CTS2 AN10 AN11 AN12 AN13 AN14 AN15 TA0IN TA1OUT Number Pins Direction Direction Setting Unit TB3IN0, INT3, SDA0 TB3IN1, INT4, SCL0 TB3OUT0 TB3OUT1 SCOUT TXD2, RXD2 Names Built-in Functions
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Table Port Functions with programmable pull-up resistor) (2/2)
Port Names Names Port8 Port9 PortA PortB Number Pins Direction Direction Setting Unit Names Built-in Functions TB0IN0, INT5 TB0IN1, INT6 TB0OUT0 TB0OUT1 TB1IN0, INT7 TB1IN1, INT8 TB1OUT0 TB1OUT1 TXD0, RXD0 RXD0, TXD0 SCLK0, CTS0 TXD1, RXD1 RXD1, TXD1 SCLK1, CTS1 TB2IN0, INT1 TB2IN1, INT2 TB2OUT0 TB2OUT1
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Table
Ports
Port Setting List(1/3)
Register Setting Values Names Specifications Input port PnCR None None None None None None None None None None None None None None None None None None None None None PnFC PnFC2
Port0
Output port Input port
Port1
Output port Input port Output port (CMOS output) Output port (open drain output) Input port Output port TB3IN0 Input, INT3 Input
Port3
SDA0 input/output (CMOS output) SDA0 input/output (open drain output) TB3IN1 Input, INT4 Input
SCL0 input/output (CMOS output) SCL0 input/output (open drain output)#2
TB3OUT0 output TB3OUT1 output Input port (without pull
P40,
Input port (with pull Output port Input port (without pull Input port (with pull
Output port (CMOS output) Output port (open drain output) Input port (without pull Port4 Input port (with pull Output port SCOUT output TXD2 output (CMOS output) TXD2 output (open drain output)#2 RXD2 Input SCLK2 Input SCLK2 output CTS2 Input Input port Port5 Output port Input Input port Port6 Output port AN15 Input
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Table
Ports
Port Setting List(2/3)
Register Setting Values Names Specifications Input port Output port TA0IN Input TA1OUT output TA4IN Input TA5OUT output INT0 Input Input port Output port TB0IN0, INT5 Input TB0IN1, INT6 Input TB0OUT0 output TB0OUT1 output TB1IN0, INT7 Input TB1IN1, INT8 Input TB1OUT0 output TB1OUT1 output PnCR PnFC None None None None None None PnFC2
Port7
Port8
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Table
Ports
Port Setting List(3/3)
Register Setting Values Names Specifications P92, Input port Output port Input port P90, Output port (CMOS output) Output port (open drain output) TXD0 output (CMOS output) TXD0 output (open drain output)#2 RXD0 Input SCLK0 Input SCLK0 output CTS0 Input TXD1 output (CMOS output) TXD1 output (open drain output)#2 RXD1 Input SCLK1 Input SCLK1 output CTS1 Input Input port Output port Input port Output port TB2IN0 Input, INT1 Input TB2IN1 Input, INT2 Input TB2OUT0 TB2OUT1 Input port
PnCR
PnFC
PnFC2
None None None None None None None None None None
None
Port9
PortA
PortB
Output port
None
None
None
using P30/P31/P41/P90/P93 open-drain output SDA0/SCL0/TXD2/TXD0/TXD1 output, please ODE. using P57,P60 analog input, please ADCCR1<SAIN3:0>. using XT1-XT2, please SYSCR0.
Note:
care
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Port (P00 P07)
Port 8-bit general-purpose port. Each individually input output using control register P0CR. Reset operation initializes bits control register P0CR sets port input port.
Reset
Direction control basis)
Internal data
P0CR write Port Output buffer write read
Figure Port
Port Register
symbol (0000H) Read/Write After reset Data from external port (Output latch register undefined.)
Port Control Register
(Read-modify-write instructions prohibited.) P06C P05C P04C P03C P02C P01C P00C
symbol P0CR (0002H) Read/Write After reset Function
P07C
Input Output
P0xC
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
Note: <P0xC> each register P0CR.
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Port (P10 P17)
Port 8-bit general-purpose port. Each individually input output using control register P1CR. Reset operation initializes bits output latch control register P1CR sets port input port.
Reset
Direction control basis)
Internal data
P1CR write Port Output buffer write read
Figure Port
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Port Register
(0001H) symbol Read/Write After reset Data from external port (Output latch register cleared "0".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P1CR (0004H) Read/Write After reset Function P17C P16C P15C P14C P13C P12C P11C P10C
Input Output
P1xC
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
function input port output port
Note:<P1XC> each register P1CR.
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Port3 (P30 P33)
Port 4-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". There following functions addition port. This function enable each function writing applicable port function register P3FC. input function external interrupt (INT3, INT4) input function 16-bit timer (TB3IN0, TB3IN1) output function 16-bit timer (TB3OUT0, TB3OUT1) function serial interface (SDA0, SCL0) Reset operation initializes, P3CR,P3FC P3FC2 "0", bits input port. Port have programmable open-drain function which controlled register.
Direction control basis)
P3CR write
Function control basis) Internal data P3FC2 write
Open-drain possible: ODE<ODE30,31>
write
P30(TB3IN0,INT3,SDA0) P31(TB3IN1,INT4,SCL0)
SDA0 SCL0
Function control basis) P3FC write
TB3IN0,INT3 TB3IN1,INT4 SDA0 SCL0
Figure Port
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Direction control basis)
P3CR
Function control basis)
Internal data
P3FC
P32(TB3OUT0)
TB3OUT0
Direction control basis)
P3CR
P3FC write
Internal data
P33(TB3OUT1)
TB3OUT1
Figure Port
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Port Register
(000CH) symbol Read/Write After reset Function Data from external port (Output latch register "1".) output mode
Port Control Register (Read-modify-write instructions prohibited.)
symbol P3CR (000EH) Read/Write After reset Function P33C P32C P31C P30C
0:Input 1:Output
Port Function Register (Read-modify-write instructions prohibited.)
P3FC (000FH) symbol Read/Write After reset P33F P32F P31F P30F
Port Function Register (Read-modify-write instructions prohibited.)
P3FC2 (000DH) symbol Read/Write After reset P31F2 P30F2
P3xF2
P3xF
P3xC
function input port output port reserved TB3OUT1 reserved reserved reserved reserved
function input port output port reserved TB3OUT0 reserved reserved reserved reserved
function input port output port TB3IN1/INT4 reserved reserved SCL0 reserved reserved
function input port output port TB3IN0/INT3 reserved reserved SDA0 reserved reserved
Note <P3xF2>/<P3xF>/<P3xC> each register P3FC2/P3FC/P3CR.
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Port (P40 P43)
Port 4-bit general-purpose port. Reset operation initializes input port, connects pull-up resistor. bits output latch register "1". There following functions addition port. This function enable each function writing applicable port function register P4FC. function serial channel (RXD2, TXD2, SCLK2/CTS2) output function system clock signal (SCOUT) Reset operation initializes, P4CR,P4FC P4FC2 "0", bits input port. Port have programmable open-drain function which controlled register.
Reset
Direction control basis) P4CR write
Function control basis) Internal data P-ch P4FC2 write
(Programmable pull
Selector
Output buffer
write
read
Selector
Figure Port
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Reset
Direction control basis) P4CR write
Function control basis) P4FC2 write Internal data Open-drain possible: ODE<ODE41> P-ch
(Programmable pull
exchange SIOCHG1 write
write
read
Selector
Figure Port
Selector
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Reset
Direction control basis) P4CR write Open-drain possible: SIOCHG1<SIOCHG14> P-ch
(Programmable pull
Internal data
exchang SIOCHG1 write
Selector
Output buffer
write
read
Selector
Figure Port
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Reset
Direction control basis) P4CR write Function control basis) P-ch P4FC2 write
(Programmable pull
Internal data
Selector
Output buffer
write
read
Selector
Figure Port
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Port Register
(0010H) symbol Read/Write After reset Data from external port (Output latch register "1".) (Output latch register): Pull-up resistor (Output latch register): Pull-up resistor
Function
Port Control Register (Read-modify-write instructions prohibited.)
symbol P4CR (0012H) Read/Write After reset Function P43C P42C P41C P40C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
P4FC2 (0011H) symbol Read/Write After reset P43F2 P41F2 P40F2
P4xF2
P4xC
function input port (SCLK2/CTS2) output port reserved SCLK2
function input port (RXD2) output port reserved reserved
function input port output port reserved TXD2
function input port output port reserved SCOUT
Note <P4xF2>/<P4xC> each register P4FC2/P4CR. Note When port used input mode, register controls internal pull-up resistor. Read-modify-write instruction prohibited input mode mode. Setting internal pull-up resistor depended states input pin. Note When setting TXD2 open-drain output, write bit2 register. P42/RXD2 does have register which changes Port/Function. example, when also used input port, input signal inputted serial receiving data.
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Port (P50 P57)
Port 8-bit general-purpose port. reset action, becomes Hi-Z becomes analog input permission.All bits output latch register "1". There following functions addition port. input function Analog/Digital Converter (AN0 AN7) Reset operation initializes, P5CR,P5FC "0", bits input port.
Reset Direction control basis) P5CR write Function control basis) P5FC write
Internal data
write read
Port (AN0 AN7)
read
Figure Port
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Port Register
(0014H) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P5CR (0016H) Read/Write After reset Function P57C P56C P55C P54C P53C P52C P51C P50C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
symbol Read/Write P5FC (0017H) After reset input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable P57F P56F P55F P54F input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable P53F P52F P51F P50F
Function
P5xF
P5xC
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
Note <P5xF>/<P5xC> each register P5FC/P5CR. Note input channel selection converter converter mode register ADCCR1.
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Port (P60 P67)
Port 8-bit general-purpose port. reset action, becomes Hi-Z becomes analog input permission.All bits output latch register "1". There following functions addition port. input function Analog/Digital Converter (AN8 AN15) Reset operation initializes, P6CR,P6FC "0", bits input port.
Reset Direction control basis) P6CR write Function control basis) P6FC write
Internal data
write read
Port (AN8 AN15)
read
Figure 4-10 Port
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Port Register
(0018H) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P6CR (001AH) Read/Write After reset Function P67C P66C P65C P64C P63C P62C P61C P60C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
symbol Read/Write P6FC (001BH) After reset input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable P67F P66F P65F P64F input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable input 0:disable 1:enable P63F P62F P61F P60F
Function
P6xF
P6xC
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
function input disable output port input enable output port
Note <P6xF>/<P6xC> each register P6FC/P6CR. Note input channel selection converter converter mode register ADCCR1.
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Port (P70 P75)
Port 6-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". There following functions addition port. This function enable each function writing applicable port function register P7FC. function 8-bit timer (TA0IN,TA1OUT) function 8-bit timer (TA4IN,TA5OUT) input function external interrupt (INT0) Reset operation initializes, P7CR P7FC "0", bits input port.
Direction control basis) P7CR (TA0IN) (TA4IN)
TA0IN TA4IN
Internal data
Direction control basis) P7CR Function control basis) P7FC
TA1OUT: TMRA1 TA3OUT: TMRA3 TA5OUT: TMRA5
(TA1OUT) (TA5OUT)
Figure 4-11 Port
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Reset
Direction control basis)
Internal data
P7CR write Output buffer write read
Figure 4-12 Port
Direction control basis) Internal data P7CR Function control basis) P7FC
Output latch
P75(INT0)
Selector
IIMC<I0LE,I0EDGE>
Figure 4-13 Port
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Port Register
(001CH) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P7CR (001EH) Read/Write After reset Function P75C P74C P73C P72C P71C P70C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
symbol P7FC (001FH) Read/Write After reset Function P75F port INT0 port TA5OUT P74F P71F port TA1OUT
INT0 setting
<P75F> <IOLE> <IOEDGE> INT0 Rising edge detect falling edge detect level level
P7xF
P7xC
function input port output port INT0 reserved
function input port output port reserved TA5OUT
function input port (TA4IN) output port reserved reserved
function input port output port reserved reserved
function input port output port reserved TA1OUT
function input port (TA0IN) output port reserved reserved
Note <P7xF>/<P7xC> each register P7FC/P7CR. Note P70/TA0IN, P73/TA4IN dose have register changing PORT/FUNCTION. example, when used input port, input signal inputted 8bit Timer.
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Port (P80 P87)
Port 8-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". There following functions addition port. This function enable each function writing applicable port function register P8FC. function 16-bit timer (TB0IN0,TB0IN1,TB0OUT0,TB0OUT1) function 16-bit timer (TB1IN0,TB1IN1,TB1OUT0,TB1OUT1) input function external interrupt (INT5 INT8) Reset operation initializes, P8CR P8FC "0", bits input port.
Direction control basis) P8CR Function control basis) P8FC (TB0IN0/INT5) (TB0IN1/INT6) (TB1IN0/INT7) (TB1IN1/INT8)
Internal data
TB0IN0, INT5 TB0IN1, INT6 TB1IN0, INT7 TB1IN1, INT8
Direction control basis) P8CR Function control basis) P8FC
TB0OUT0: TMRB0 TB0OUT1: TMRB0 TB1OUT0: TMRB1 TB1OUT1: TMRB1
(TB0OUT0) (TB0OUT1) (TB1OUT0) (TB1OUT1)
Figure 4-14 Port
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Port Register
(0020H) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P8CR (0022H) Read/Write After reset Function P87C P86C P85C P84C P83C P82C P81C P80C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
symbol P8FC (0023H) Read/Write After reset port TB1OUT1 port TB1OUT0 port TB1IN1, INT8 port TB1IN0, INT7 P87F P86F P85F P84F port TB0OUT1 port TB0OUT0 port TB0IN1, INT6 port TB0IN0, INT5 P83F P82F P81F P80F
Function
P8xF
P8xC
function input port output port reserved TB1OUT1
function input port output port reserved TB1OUT0
function input port output port TB1IN1/ INT8 reserved
function input port output port TB1IN0/ INT7 reserved
function input port output port reserved TB0OUT1
function input port output port reserved TB0OUT0
function input port output port TB0IN1/ INT6 reserved
function input port output port TB0IN0/ INT5 reserved
Note: <P8xF>/<P8xC> each register P8FC/P8CR.
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Port (P90 P97)
Port Port 6-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". addition functioning port, port also function SIO0, SIO1. This function enable each function writing applicable port function register P9FC. Reset operation initializes P9CR P9FC "0", bits input port. Port Port 2-bit general-purpose port. case output port, this open drain output. Reset operation initializes output latch register control register "1", "High-Z" (High impedance). addition functioning port, port also function low-frequency oscillator connection (XT1 XT2) during using speed clock function. Therefore, dual clock function setting system clock control registers SYSCR0 SYSCR1.
4.9.1
Port (TXD0/RXD0), (TXD1/RXD0)
addition functioning port, Port also function output input serial channel. Port have programmable open-drain function which controlled register.
Direction control basis) P9CR Function control basis) Internal data P9FC exchange
SIOCHG0 TXD0, TXD1
Open-drain possible: ODE<ODE90,93> (TXD0) (TXD1)
RXD0, RXD1
Figure 4-15 Port
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4.9.2
Port (RXD0/TXD0), (RXD1/TXD1)
addition functioning port, port also function input output serial channel. Port have programmable open-drain function which controlled SIOCHG0 register.
Direction control basis) P9CR Internal data exchange Open-drain possible: SIOCHG<SIOCHG02,05> TXD0, TXD1 RXD0, RXD1 (RXD0/TXD0) (RXD1/TXD1)
SIOCHG0
Figure 4-16 Port
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4.9.3
Port 92(CTS0/SCLK0), (CTS1/SCLK1)
addition functioning port, port also function input SCLK serial channel.
Direction control basis) P9CR Internal data Function control basis) P9FC SCLK0, SCLK1 CTS0, CTS1 SCLK0, SCLK1 (SCLK0/CTS0) (SCLK1/CTS1)
Figure 4-17 Port
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4.9.4
Port (XT1), (XT2)
addition functioning port, port also function frequency oscillator connection pins.
Function control basis)
Direction control basis)
Internal data
Function control basis)
Direction control basis)
Figure 4-18 Port
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Port Register
(0024H) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol P9CR (0026H) Read/Write After reset Function P97C P96C P95C P94C P93C P92C P91C P90C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
Symbol P9FC (0027H) Read/Write After reset Port disable enable P97F P96F Port disable enable port SCLK1 output P95F port TXD1 output P93F port SCLK0 output P92F P90F port TXD0 output
Function
P9xF
P9xC
function
function
function input port (SCLK1/ CTS1) output port reserved SCLK1
function input port (RXD1) output port reserved reserved
function
function input port (SCLK0/ CTS0) output port reserved SCLK0
function input port (RXD0) output port reserved reserved
function
input port
input port
reserved input port output port
reserved input port output port
output port reserved TXD1
output port reserved TXD0
Note <P9xF>/<P9xC> each register P9FC/P9CR. Note When setting open-drain output, write bit3 register (for TXD0 pin), bit4 (for TXD1 pin). P91/ RXD0 P94/RXD1 does have register which changes Port/Function. example, when also used input port, input signal inputted serial receiving data. Note frequency oscillation circuit connect frequency resonator port necessary following procedure reduce consumption power supply. (Case resonator connection) P9CR<P96C, P97C> "11", P9<P96:97> "00" (Case external clock input) P9CR<P96C, P97C> "11", P9<P96:97> "10"
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4.10 Port (PA0 PA3)
Port 4-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". There following functions addition port. This function enable each function writing applicable port function register PAFC. function 16-bit timer (TB2IN0,TB2IN1,TB2OUT0,TB2OUT1) input function external interrupt (INT1, INT2) Reset operation initializes, PACR PAFC "0", bits input port.
Direction control basis) PACR Function control basis) PAFC (TB2IN0/INT1) (TB2IN1/INT2)
Internal data
TB2IN0, INT1 TB2IN1, INT2
Direction control basis) PACR Function control basis) PAFC
TB02UT0: TMRB2 TB02UT1: TMRB2
(TB2OUT0) (TB2OUT1)
Figure 4-19 Port
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Port Register
(0028H) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol PACR (002AH) Read/Write After reset Function PA3C PA2C PA1C PA0C
Input Output
Port Function Register (Read-modify-write instructions prohibited.)
symbol PAFC (002BH) Read/Write After reset port TB2OUT1 0:port TB2OUT0 PA3F PA2F port TB2IN1, INT2 port TB2IN0, INT1 PA1F PA0F
Function
PAxC
PAxF
function input port output port reserved TB2OUT1
function input port output port reserved TB2OUT0
function input port output port TB2IN1/ INT2 reserved
function input port output port TB2IN0/INT1 reserved
Note: <PAxF>/<PAxC> each register PAFC/PACR.
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4.11 Port (PB0 PB2)
Port 3-bit general-purpose port. Reset operation initializes input port. bits output latch register "1". Reset operation initializes, PBCR "0", bits input port.
Reset
Direction control basis)
Internal data
PBCR write Port Output buffer write read
Figure 4-20 Port
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Port Register
(002CH) symbol Read/Write After reset Data from external port (Output latch register "1".)
Port Control Register (Read-modify-write instructions prohibited.)
symbol PBCR (002EH) Read/Write After reset Function PB2C PB1C Input Output PB0C
PBxC
function input port output port
function input port output port
function input port output port
Note: <PBxC> each register PBCR.
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4.12 Open-drain Control
P30,P31,P41,P90,P93 perform selection open-drain output bit. Reset operation initializes bits control register sets CMOS output. Open-drain Control Register
(003FH) symbol Read/Write After reset Function ODE93 ODE90 ODE41 ODE31 ODE30
CMOS output 1:Open drain output
4.13 Serial pins switching Open-drain output Control
serial channel interchangeable P41, P42, P90, P91, P94. Serial pins switching Open-drain Control Register (Read-modify-write instructions prohibited.)
SIOCHG0 (0025H) symbol Read/Write After reset SIOCHG05 SIOCHG04 SIOCHG03 port CMOS output Opendrain output port CMOS output Opendrain output SIOCHG02 SIOCHG01 SIOCHG00
Function
Setting P94C TXD1
Setting P93C P93F RXD1
Setting P91C TXD0
Setting P90C P90F RXD0
SIOCHG02
SIOCHG01
SIOCHG00
Setting P91C TXD0 (CMOS output) TXD0 (Open-drain output)
Setting P90C P90F RXD0
RXD0
SIOCHG05
SIOCHG04
SIOCHG03
Setting P94C TXD1 (CMOS output) TXD1 (Open-drain output)
Setting P93C P93F RXD1
RXD1
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Serial pins switching Open-drain Control Register (Read-modify-write instructions prohibited.)
SIOCHG1 (0015H) symbol Read/Write After reset SIOCHG14 port CMOS output Opendrain output SIOCHG12 SIOCHG11
Function
Setting P42C TXD2
Setting P41C P41F2 RXD2
SIOCHG14
SIOCHG12
SIOCHG11
Setting P42C TXD2 (CMOS output) TXD2 (Open-drain output)
Setting P41C P41F2 RXD2
RXD2
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8-Bit Timers (TMRA)
TMP91FU62 features channels (TMRA0, TMRA1, TMRA4, TMRA5) built-in 8-bit timers. These timers paired into modules: TMRA01 TMRA45. Each module consists channels operate following operating modes. 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM Variable duty cycle with constant period) Figure Figure show block diagrams TMRA01 TMRA45. Each channel consists 8-bit counter, 8-bit comparator 8-bit timer register. addition, timer flip-flop prescaler provided each pair channels. operation mode timer flip-flops controlled 5-byte registers SFRs (Special function registers). Each three modules (TMRA01 TMRA45) operated independently. modules operate same manner; hence only operation TMRA01 explained here. Table
Specification Input external clock External Output timer flip-flop TA1OUT (Shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TA5OUT (Shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H)
Registers Pins Each Module
Module TMRA01 TA0IN (Shared with P70) TMRA45 TA4IN (Shared with P73)
Timer register
Timer register (Address) Timer mode register
Timer flip-flop control register
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Prescaler <TA01PRUN> T256 Run/clear TA01RUN
Block Diagrams
Prescaler clock:
Selector TA01RUN<TA0RUN> Selector 8-bit counter (UC1)
External input clock: TA0IN 8-bit counter (UC0) T256
TA01MOD <TA1CLK1:0>
TA01RUN <TA1RUN>
Timer flip-flop TA1FF
Timer flip-flop output: TA1OUT TA1FFCR
Figure TMRA01 Block Diagram
TA01MOD <TA0CLK1:0> overflow TA01MOD <PWM01:00> Match detect TA0TRG
TA01MOD <TA01M1:0>
Page
8-bit comparator (CP0) 8-bit timer register TA0REG TA01RUN <TA0RDE> Register buffer Internal data TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG
Match detect 8-bit comparator (CP1)
8-bit timer register TA1REG
Internal data
TMRA1 interrupt output: INTTA1
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Prescaler <TA45PRUN> T256 Run/clear TA45RUN
Prescaler clock:
Selector TA45RUN<TA4RUN> Selector
External input clock: TA4IN 8-bit counter (UC4) T256
TA45MOD <TA5CLK1:0>
TA45RUN <TA5RUN> 8-bit counter (UC5)
Timer flip-flop TA5FF
Timer flip-flop output: TA5OUT TA5FFCR
Figure TMRA45 Block Diagram
TA45MOD <TA4CLK1:0> overflow TA45MOD <PWM41:40> Match detect TA4TRG
TA45MOD <TA45M1:0>
Page
8-bit comparator (CP4) 8-bit timer register TA4REG TA45RUN <TA4RDE> Register buffer Internal data TMRA4 interrupt output: INTTA4 TMRA4 match output: TA4TRG
Match detect 8-bit comparator (CP5)
8-bit timer register TA5REG
Internal data
TMRA5 interrupt output: INTTA5
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Operation Each Circuit
5.2.1 Prescalers
9-bit prescaler generates input clock TMRA01. "T0" input clock prescaler clock divided which selected using prescaler clock selection register SYSCR0<PRCK1>. prescaler's operation controlled using TA01RUN<TA01PRUN> timer control register. Setting <TA01PRUN> starts count; setting <TA01PRUN> clears prescaler stops operation. Table shows various prescaler output clock resolutions. Table Prescaler Output Clock Resolution
MHz, 32.768 System Clock Selection SYSCR1<SYSCK> (fs) Prescaler Clock Selection SYSCR0<PRCK1> Prescaler Output Clock Resolution (1/2) 23/fs (244 23/fc (0.4 (1/1) fFPH 24/fc (0.8 25/fc (1.6 26/fc (3.2 27/fc (6.4 (1/16) fc/16 CLOCK 27/fc (6.4 (1/8) 25/fs (977 25/fc (1.6 26/fc (3.2 27/fc (6.4 28/fc (12.8 29/fc (25.6 29/fc (25.6 (1/32) 27/fs (3.9 27/fc(6.4 28/fc (12.8 29/fc (25.6 210/fc (51.2 211/fc (102.4 211/fc (102.4 T256 (1/512) 211/fs (62.5 211/fc (102.4 212/fc (204.8 213/fc (409.6 214/fc (819.2 215/fc (1638.4 215/fc (1638.4
Gear Value SYSCR1<GEAR2:0>
(fc) (fc/2) (fc/4)
(fc)
(fc/8) (fc/16)
Note: xxx: Don't care
5.2.2
counters (UC0 UC1)
These 8-bit binary counters which count input clock pulses clock specified TA01MOD. input clock selectable either external clock input TA0IN three internal clocks T16. clock setting specified value TA01MOD<TA01CLK1:0>. input clock depends operation mode. 16-bit timer mode, overflow output from used input clock. mode other than 16-bit timer mode, input clock selectable either internal clocks T256, comparator output (The match detection signal) from TMRA0. each interval timer timer operation control register bits TA01RUN<TA0RUN> TA01RUN<TA1RUN> used stop clear counters control their count. reset clears both counters, stopping timers.
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5.2.3
Timer registers (TA0REG TA1REG)
These 8-bit registers which used time interval. When value timer register TA0REG TA1REG matches value corresponding counter, comparator match detect signal goes active. value timer register 00H, signal goes active when counter overflows. TA0REG double buffer structure, each which makes pair with register buffer. setting TA01RUN<TA0RDE> determines whether TA0REG's double buffer structure enabled disabled. disabled <TA0RDE> enabled <TA0RDE> "1". When double buffer enabled, data transferred from register buffer timer register when overflow occurs mode, start cycle mode. Hence double buffer cannot used timer mode. reset initializes <TA0RDE> "0", disabling double buffer. double buffer, write data timer register, <TA0RDE> "1", write following data register buffer. Figure shows configuration TA0REG.
Timer registers (TA0REG)
Selector
Shift trigger Register buffers Write Internal data
Matching detection cycle overflow Write TA0REG
TA01RUN<TA0RDE>
Figure Configuration TA0REG
Note:The same memory address allocated timer register TA0REG register buffer When <TA0RDE> same value written register buffer timer register TA0REG; when <TA0RDE> only register buffer written
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5.2.4
Comparator (CP0 CP1)
comparator compares value counter with value timer register. they match, counter cleared interrupt signal (INTTA0 INTTA1) generated. timer flip-flop inversion enabled, timer flip-flop inverted same time.
Note:If value smaller than up-counter value written timer register while timer counting this will cause timer overflow interrupt cannot generated expected time. (The value timer register changed without problem value larger than up-counter value.) 16bit interval timer mode, sure write both TA0REG TA1REG this order bits total), compare circuit will function only lower bits set.
5.2.5
Timer flip-flop (TA1FF)
timer flip-flop (TA1FF) flip-flop inverted match detects signal (8-bit comparator output) each interval timer. Whether inversion enabled disabled determined setting TA1FFCR<TA1FFIE> timer flip-flop control register. reset clears value TA1FF1 "0". Writing "01" "10" TA1FFCR<TA1FFC1:0> sets TA1FF Writing "00" these bits inverts value TA1FF (This known software inversion). TA1FF signal output TA1OUT (Concurrent with P71). When this used timer output, timer flip-flop should beforehand using port function registers P7CR, P7FC.
condition TA1FF inversion varies with mode shown below
8-bit interval timer mode 16-bit interval timer mode mode mode matches TA0REG matches TA1REG (Select either two) matches TA0REG matches TA1REG matches TA0REG overflow occurs matches TA0REG matches TA1REG
Note: inversion match-detect signal setting change TMRA1 flip-flop control register occur simultaneously, resultant operation varies depending situation, shown below.
inversion match-detect signal inversion register occur simultaneously, flip-flop will
inverted only once.
inversion match-detect signal attempt flip-flop register occur simultaneously, timer flip-flop will inversion match-detect signal attempt clear flip-flop register occur simultaneously flip-flop will cleared
sure stop timer before changing flip-flop insertion setting. setting changed while timer counting, proper operation cannot obtained.
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TMRA01 Register
symbol TA01RUN (0100H) Read/Write After Reset TA0RDE Double buffer Disable Enable TMRA01 prescaler I2TA01 TA01PRUN counter (UC1) counter (UC0) TA1RUN TA0RUN
Function
IDLE2 Stop Operate
Stop clear (count
Count operation
TA01PRUN TA1RUN TA0RUN Stop clear
TA0REG double buffer control
TA0RDE (Count Enable Disable
Note: values bits TA01RUN when read.
TMRA45 Register
symbol TA45RUN (0110H) Read/Write After Reset TA4RDE Double buffer Disable Enable TMRA45 prescaler I2TA45 TA45PRUN counter (UC5) counter (UC4) TA5RUN TA4RUN
Function
IDLE2 Stop Operate
Stop clear (count TA4REG double buffer control
Count operation
TA45PRUN TA5RUN TA4RUN Stop clear
TA4RDE
Disable Enable
(Count
Note: values bits TA45RUN when read.
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TMRA01 Mode Register
symbol TA01MOD (0104H) Read/Write After reset Operation mode 8-bit timer mode 16-bit timer mode 8-bit mode 8-bit mode cycle Reserved TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0
Function
Input clock TMRA1 TA0TRG T256
Input clock TMRA0 TA0IN
TMRA0 input clock selection
<TA0CLK1:0> TA0IN
TMRA1 input clock selection
TA01MOD<TA01M1:0> <TA1CLK1:0> Comparator output from TMRA0 T256 Overflow output from TMRA0 (16-bit timer mode) TA01MOD<TA01M1:0>
cycle selection
<PWM01:00> Reserved Clock source Clock source Clock source
TMRA01 operation mode selection
<TA01M1:0> 8-bit 8-bit (TMRA0) 8-bit timer (TMRA1) 8-bit timers 16-bit timer
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TMRA45 Mode Register
symbol TA45MOD (0114H) Read/Write After reset Operation mode 8-bit timer mode 16-bit timer mode 8-bit mode 8-bit mode cycle Reserved TA45M1 TA45M0 PWM41 PWM40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0
Function
Input clock TMRA5 TA4TRG T256
Input clock TMRA4 TA4IN
TMRA4 input clock selection
<TA4CLK1:0> TA4IN
TMRA5 input clock selection
TA45MOD<TA45M1:0> <TA5CLK1:0> Comparator output from TMRA4 T256 Overflow output from TMRA4 (16-bit timer mode) TA45MOD<TA45M1:0>
cycle selection
<PWM41:40> Reserved Clock source Clock source Clock source
TMRA45 operation mode selection
<TA45M1:0> 8-bit 8-bit (TMRA4) 8-bit timer (TMRA5) 8-bit timers 16-bit timer
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TMRA1 Flip-Flop Control Register
symbol TA1FFCR (0105H) Read/Write After reset Invert TA1FF TA1FF Clear TA1FF Don't care TA1FFC1 TA1FF control inversion Disable Enable TA1FFC0 TA1FFIE TA1FF inversion select TMRA0 1:TMRA1 TA1FFIS
Function
Inverse signal timer flip-flop (TA1FF) (Don't care except 8-bit timer mode)
TA1FFIS Inversion TMRA1 Inversion TMRA0
Inversion TA1FF
TA1FFIE Enabled Disabled
Control TA1FF
<TA1FFC1:0> Clears TA1FF Don't care Inverts value TA1FF (Software inversion) Sets TA1FF
Note: values bits TA1FFCR when read.
TMRA5 Flip-Flop Control Register
symbol TA5FFCR (0115H) Read/Write After reset Invert TA5FF TA5FF Clear TA5FF Don't care TA5FFC1 TA5FF control inversion Disable Enable TA5FFC0 TA5FFIE TA5FF inversion select TMRA4 1:TMRA5 TA5FFIS
Function
Inverse signal timer flip-flop (TA5FF) (Don't care except 8-bit timer mode)
TA5FFIS Inversion TMRA5 Inversion TMRA4
Inversion TA5FF
TA5FFIE Enabled Disabled
Control TA5FF
<TA5FFC1:0> Clears TA5FF Don't care Inverts value TA5FF (Software inversion) Sets TA5FF
Note: values bits TA5FFCR when read.
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Timer Register
symbol TA0REG (0102H) Read/Write After Reset symbol TA1REG (0103H) Read/Write After Reset symbol TA4REG (0112H) Read/Write After Reset symbol TA5REG (0113H) Read/Write After Reset
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Operation Each Mode
5.4.1 8-bit timer mode
Both TMRA0 TMRA1 used independently 8-bit interval timers. function counter data TMRA0 TMRA1 after stop these registers.
5.4.1.1
Generating interrupts fixed interval (Using TMRA1)
generate interrupts constant intervals using TMRA1 (INTTA1), first stop TMRA1 then operation mode, input clock cycle TA01MOD TA1REG register, respectively. Then, enable interrupt INTTA1 start TMRA1 counting. Example: generate INTTA1 interrupt every MHz, each register follows:
Clock state System clock Prescaler clock Clock gear High frequency (fc) fFPH (fc)
TA01RUN TA01MOD TA1REG INTETA01 TA01RUN
Stop TMRA1 clear Select 8-bit timer mode select (0.4 MHz) input clock. TA1REG Enable INTTA1 level Start TMRA1 counting.
Note: Don't care, change
Select input clock using Table 5-2.
Note: input clocks TMRA0 TMRA1 different from follows. TMRA0: TA0IN input, TMRA1: Match output TMRA0, T16, T256
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5.4.1.2
Generating duty ratio square wave pulse
state timer flip-flop (TA1FF) inverted constant intervals status output timer output (TA1OUT). Example: output square wave pulse from TA1OUT MHz, following procedure make appropriate register settings. This example uses TMRA1; however, either TMRA0 TMRA1 used.
Clock state System clock Prescaler clock Clock gear High frequency (fc) fFPH (fc)
TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN
function TA1OUT pin. Start TMRA1 counting. Stop TMRA1 clear Select 8-bit timer mode select (0.4 MHz) input clock. timer register Clear TA1FF invert match detects signal from TMRA1.
Note: Don't care, change
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TA01RUN <TA1RUN> Bits
counter Bit1
Bit0 Comparator timig Comparator output (Match detect) INTTA1 clear
TA1FF
TA1OUT
Figure Square Wave Output Timing Chart (50% duty)
5.4.1.3
Making TMRA1 count match signal from TMRA0 comparator
Select 8-bit timer mode comparator output from TMRA0 input clock TMRA1.
Comparator output (TMRA0 match)
TMRA0 counter (when TA0REG TMRA1 counter (when TA1REG
TMRA1 match output
Figure TMRA1 Count Signal from TMRA0
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5.4.2
16-bit timer mode
16-bit interval timer configured pairing 8-bit timers TMRA0 TMRA1. make 16-bit interval timer which TMRA0 TMRA1 cascaded together, TA01MOD<TA01M1:0> 16-bit timer mode, overflow output from TMRA0 used input clock TMRA1, regardless value TA01MOD<TA1CLK1:0>. Table shows cycle input clock TMRA0. 8-bit TA0REG 8-bit TA1REG. Please keep setting TA0REG first because setting data TA0REG inhibit compare function setting data TA1REG permit Example: generate INTTA1 interrupt every MHz, timer registers TA0REG TA1REG follows:
Clock state System clock Prescaler clock Clock gear High frequency (fc) fFPH (fc)
(27/fc MHz) used input clock counting, following value registers: s/(27/fc) 62500 F424H (e.g., TA1REG TA0REG 24H). result, INTTA1 interrupt generated every [s]. comparator match signal output from TMRA0 each time counter matches TA0REG, though counter cleared also INTTA0 generated. case TMRA1 comparator, match detect signal output each comparator pulse which values counter TA1REG match. When match detect signal output simultaneously from both comparators TMRA0 TMRA1, counters cleared interrupt INTTA1 generated. Also, inversion enabled, value timer flip-flop TA1FF inverted. Example: When TA1REG TA0REG
Value counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1
0080H
0180H
0280H
0380H
0480H
0080H
Timer output TA1OUT
Inversion
Figure Timer Output 16-Bit Timer Mode
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5.4.3
8-bit (Programmable pulse generation) output mode
Square wave pulses generated frequency duty ratio TMRA0. output pulses active active high. this mode TMRA1 cannot used. TMRA0 outputs pulses TA1OUT pin.
<TA1FFC1:0> "10" <TA1FFC1:0> "01"
Example: <TA1FFC1:0> "01"
TA0REG match (Interrupt INTTA0) TA1REG match (Interrupt INTTA1)
TA1OUT TA0REG TA1REG
Figure 8-Bit Output Waveforms
this mode, programmable square wave generated inverting timer output each time 8-bit counter (UC0) matches value timer registers TA0REG TA1REG. value TA0REG must smaller than value TA1REG. Although counter TMRA1 (UC1) used this mode, TA01RUN<TA1RUN> should "1", that counting. Figure shows block diagram representing this mode.
TA1OUT TA01RUN<TA0RUN>
Selector
TA0IN TA01MOD<TA0CLK1:0>
TA1FF 8-bit counter (UC0)
TA1FFCR<TA1FFIE>
Inversion
INTTA0
Comparator
Comparator
INTTA1
Selector TA0REG-WR
TA0REG
Shift trigger
Register buffer TA01RUN<TA0RDE>
TA1REG
Internal data
Figure Block Diagram 8-Bit Output Mode
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TA0REG double buffer enabled this mode, value register buffer will shifted into TA0REG each time TA1REG matches UC0. double buffer facilitates handling low-duty waves (when duty varied).
Match with TA0REG counter
counter Match wiht TA1REG Shift from register buffer TA0REG (Value compared) Register buffer counter
TA0REG (Register buffer write
Figure Operation Register Buffer
Note:The values that TAxREG range from (equivalent 100h). maximum value set, match-detect signal goes active when up-counter overfolws.
Example: generate 1/4-duty 50-kHz pulses MHz):
Clock state
System clock Prescaler clock Clock gear
High frequency (fc) fFPH (fc)
Calculate value which should timer register. obtain frequency kHz, pulse cycle should 1/50 23/fc MHz); s/(23/fc) Therefore TA1REG (32H), 50-kHz pulses obtained. duty 1/4: s/(23/fc) Therefore, TA0REG 0DH.
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TA01RUN TA01MOD TA0REG TA1REG TA1FFCR
Stop TMRA0 TMRA01 clear "0".(Double buffer disable) 8-bit mode, select input clock. Write 0DH. Write 32H. TA1FF, enabling both inversion double buffer. Writing "10" provides negative logic pulse.
P7CR P7FC TA01RUN
TA1OUT pin. Start TMRA0 TMRA01 counting.(Double buffer enable)
Note:X Don't Care change
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5.4.4
8-bit output mode
This mode only valid TMRA0. this mode, pulse with maximum resolution bits output. When TMRA0 used pulse output TA1OUT pin. TMRA1 also used 8-bit timer. timer output inverted when counter (UC0) matches value timer register TA0REG when counter overflow occurs specified TA01MOD<PWM01:00>). counter cleared when counter overflow occurs. following conditions must satisfied before this mode used. Value TA0REG Value counter overflow Value TA0REG
TA0REG match overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle)
Figure 5-10 8-Bit Waveforms
Figure 5-11 shows block diagram representing this mode.
Selector
TA0IN 8-bit counter (UC0)
TA01RUN<TA0RUN>
TA1OUT
Clear overflow control Overflow
TA1FF
Invert TA01MOD <PWM01:00>
TA1FFCR <TA1FFIE>
TA01MOD<TA0CLK1:0>
Comparator
INTTA0
Selector TA0REG-WR
TA0REG
Shift trigger
Register buffer0 TA01RUN<TA0RDE> Internal data
Figure 5-11 Block Diagram 8-Bit Mode
this mode, value register buffer will shifted into TA0REG overflow detected when TA0REG double buffer enabled. Page
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double buffer facilitates handling duty ratio waves.
Match with TA0REG
counter overflow counter
Shift into TA0REG
TA0REG (Value compared) Register buffer
TA0REG (Register buffer write
Figure 5-12 Operation Register Buffer
Example: output following waves TA1OUT MHz:
Clock state
System clock Prescaler clock Clock gear
High frequency (fc) fFPH (fc)
achieve 51.2 cycle setting 23/fc MHz): 51.2 s/(23/fc) Therefore should Since low-level period 29.6 when 23/fc MHz), following value TA0REG: 29.6 s/(23/fc)
TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN
TA1OUT pin. Start TMRA0 counting. Stop TMRA0 clear Select 8-bit mode (Cycle: select input clock. Write 4AH. Clear TA1FF enable inversion double buffer.
Note:X Don't Care change
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Table Cycle
Select System Clock SYSCR1 <SYSCK> (fs) Gear Value SYSCR1 <GEAR2:0> (fc) (fc/2) (fc/4) (fc) (fc/8) (fc/16) (1/16) fc/16 clock (1/1) fFPH Select Prescaler Clock SYSCR0 <PRCK1> cycle 15.6 25.6 51.2 102.4 204.8 409.6 409.6 62.5 102.4 204.8 409.6 819.2 1638 1638 409.6 819.2 1638 3277 6554 6554 31.3 51.2 102.4 204.8 409.6 819.2 819.2 204.8 409.6 810.2 1638 3277 3277
MHz, 32.768
819.2 1638 3277 6554 13107 13107 62.5 102.4 204.8 409.6 819.2 1638 1638 409.6 819.2 1638 3277 6554 6554 1000 1638 3277 6554 13107 26214 26214
Note: xxx: Don't care
5.4.5
Settings each mode
Table shows settings each mode.
Table Timer Mode Setting Registers
Register Name <Bit Symbol> Function <TA01M1:0> Timer Mode <PWM01:00> Cycle TA01MOD <TA1CLK1:0> Upper Timer Input Clock Lower timer match T16, T256 (00, <TA0CLK1:0> Lower Timer Input Clock External clock (00, External clock (00, External clock (00, External clock (00, TA1FFCR TA1FFIS Timer Invert Signal Select Lower timer output Upper timer output
8-bit timer channels
16-bit timer mode
8-bit channel
8-bit channel
(01,
8-bit timer channel
T16, T256 (01,
Output disabled
Note: Don't care
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16-Bit Timer/Event Counters (TMRB)
TMP91FU62 incorporates four multifunctional 16-bit timer/event counters (TMRB0, TMRB1, TMRB2, TMRB3) which have following operation modes: 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode capture function enables selection following modes: Frequency measurement mode Pulse width measurement mode Time differential measurement Figure show block diagrams TMRB0, TMRB1, TMRB2 TMRB3. Each timer/event counter channel consists 16-bit up-counter, 16-bit timer registers (one them with double-buffer structure), 16-bit capture registers, comparators, capture input controller, timer flipflops timer flip-flop controller. Each timer/event counter controlled 11-byte (special-function register). Each four channels (TMRB0, TMRB1, TMRB2, TMRB3) used independently. Each channel features same operations except those described Table 6-1. Hence, only operation TMRB0 explained below. Table
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