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TLCS-870/C1 Series
TMP89FS60
information contained herein subject change without notice. 021023_D TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. 021023_B products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. 060106_Q information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patents other rights TOSHIBA third parties. 070122_C products described this document subject foreign exchange foreign trade control laws. 060925_E discussion reliability microcontrollers predicted, please refer Section chapter entitled Quality Reliability Assurance/Handling Precautions. 030619_S
2007 TOSHIBA CORPORATION Rights Reserved
Revision History
Date 2007/10/27 2007/11/2 Revision First Release Contents Revised
Table Contents
TMP89FS60
Features Assignment Block Diagram Names Functions
Core
Configuration Memory space
Code area
BOOTROM Flash BOOTROM Flash 2.2.1.1 2.2.1.2 2.2.1.3 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4
2.2.1
2.2.2
Data area
System clock controller
Configuration Control Functions
Clock generator Clock gear Timing generator
2.3.1 2.3.2 2.3.3
2.3.4 2.3.5
2.3.3.1 2.3.3.2 2.3.3.3 2.3.4.1 2.3.4.2 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.6.1 2.3.6.2 2.3.6.3 2.3.6.4
Warm-up counter Operation mode control circuit
Single-clock mode Dual-clock mode STOP mode Transition operation modes STOP mode IDLE1/2 SLEEP1 modes IDLE0 SLEEP0 modes SLOW mode Warm-up counter operation when oscillation enabled hardware Warm-up counter operation when oscillation enabled software
2.3.6
Operation Mode Control
Reset Control Circuit
Configuration Control Functions Reset Signal Generating Factors.
External reset input (RESET input) Power-on reset Voltage detection reset Watchdog timer reset System clock reset Trimming data reset Flash standby reset Internal factor reset detection status register external reset input port
2.4.1 2.4.2 2.4.3 2.4.4
2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.4.4.6 2.4.4.7 2.4.4.8 2.4.4.9
Revision History.
Interrupt Control Circuit
Configuration Interrupt Latches (IL27 IL3) Interrupt Enable Register (EIR) Maskable Interrupt Priority Change Function Interrupt Sequence
Initial Setting Interrupt acceptance processing. Saving/restoring general-purpose registers
Using PUSH instructions Using data transfer instructions Using register bank save/restore general-purpose registers
3.3.1 3.3.2
Interrupt master enable flag (IMF) Individual interrupt enable flags (EF27 EF4)
3.5.1 3.5.2 3.5.3
3.5.4 3.6.1 3.6.2
3.5.3.1 3.5.3.2 3.5.3.3
Software Interrupt (INTSW) Undefined Instruction Interrupt (INTUNDEF). Revision History.
Address error detection Debugging
Interrupt return
External Interrupt control circuit
Configuration Control Function.
power consumption function External interrupt External interrupts 1/2/3.
Interrupt request signal generating condition detection function noise canceller pass signal monitoring function when interrupt request signals generated Noise cancel time selection function Interrupt request signal generating condition detection function noise canceller pass signal monitoring function when interrupt request signals generated Noise cancel time selection function
4.3.1 4.3.2 4.3.3
4.3.4
4.3.3.1 4.3.3.2 4.3.3.3 4.3.4.1 4.3.4.2 4.3.4.3
External interrupt
4.3.5
External interrupt
Watchdog Timer (WDT)
Configuration Control Functions
Setting enabling/disabling watchdog timer operation Setting clear time 8-bit counter Setting overflow time 8-bit counter Setting overflow detection signal 8-bit counter Writing watchdog timer control codes Reading 8-bit counter Reading watchdog timer status
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7
Power-on Reset Circuit
Configuration
Function.
Voltage Detection Circuit
Configuration Control Function.
Enabling/disabling voltage detection operation Selecting voltage detection operation mode Selecting detection voltage level Voltage detection flag voltage detection status flag. Selecting STOP mode release signal
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4.1 7.4.2
Register Settings Revision History.
Setting procedure when operation mode generate voltage detection interrupt request signals Setting procedure when operation mode generate voltage detection reset signals
Ports
Port Control Registers List Port Settings Port Registers
Port (P03 P00). Port (P13 P10). Port (P27 P20). Port (P47 P40). Port (P57 P50). Port (P77 P70). Port (P84 P80). Port (P94 P90). Port (PB7 PB0)
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9
Serial Interface Selecting Function Revision History.
Special Function Registers
SFR1 (0x0000 0x003F) SFR2 (0x0F00 0x0FFF). SFR3 (0x0E40 0x0EFF)
Power Consumption Function Peripherals
10.1 Control
Divider Output (DVO)
11.1 11.2 11.3 Configuration Control Revision History.
Function
11.2.1
Time Base Timer (TBT)
12.1 Time Base Timer
Configuration Control Functions 12.1.1 12.1.2 12.1.3
12.2
Revision History.
16-bit Timer Counter (TCA)
13.1 13.2 13.3 13.4 Configuration Control Power Consumption Function Timer Function.
Timer mode.
Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation 13.4.1.1 13.4.1.2 13.4.1.3 13.4.1.4 13.4.2.1 13.4.2.2 13.4.2.3 13.4.2.4 13.4.3.1 13.4.3.2 13.4.3.3 13.4.3.4 13.4.4.1 13.4.4.2 13.4.4.3 13.4.4.4 13.4.5.1 13.4.5.2 13.4.6.1 13.4.6.2 13.4.6.3
13.4.1
13.4.2
External trigger timer mode
13.4.3
Event counter mode.
13.4.4
Window mode
13.4.5 13.4.6
Pulse width measurement mode Programmable pulse generate (PPG) mode
Setting Operation Register buffer configuration
13.5 13.6
Noise Canceller Revision History.
Setting.
13.5.1
8-bit Timer Counter (TC0)
14.1 14.2 Configuration Control
Timer counter Timer counter Common timer counters Operation modes usable source clocks
14.3 14.4
14.2.1 14.2.2 14.2.3 14.2.4
Power Consumption Function Functions
8-bit timer mode
Setting Operation Double buffer Setting
14.4.1
14.4.2
14.4.1.1 14.4.1.2 14.4.1.3 14.4.2.1
8-bit event counter mode
14.4.3
14.4.2.2 14.4.2.3 14.4.3.1 14.4.3.2 14.4.3.3 14.4.4.1 14.4.4.2 14.4.4.3 14.4.5.1 14.4.5.2 14.4.5.3 14.4.6.1 14.4.6.2 14.4.6.3 14.4.7.1 14.4.7.2 14.4.7.3 14.4.8.1 14.4.8.2 14.4.8.3
8-bit pulse width modulation (PWM) output mode
Setting Operations Double buffer Setting Operation Double buffer Setting Operations Double buffer Setting Operations Double buffer Setting Operations Double buffer Setting Operations Double buffer
Operation Double buffer
14.4.4
8-bit programmable pulse generate (PPG) output mode
14.4.5
16-bit timer mode
14.4.6
16-bit event counter mode
14.4.7
12-bit pulse width modulation (PWM) output mode
14.4.8
16-bit programmable pulse generate (PPG) output mode
Real Time Clock (RTC)
15.1 15.2 15.3 Configuration Control Function
Power Consumption Function Enabling/disabling real time clock operation. Selecting interrupt generation interval
15.4
15.3.1 15.3.2 15.3.3 15.4.1 15.4.2
Real Time Clock Operation
Enabling real time clock operation Disabling real time clock operation
Asynchronous Serial Interface (UART)
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Configuration Control Power Consumption Function Protection Prevent UART0CR1 UART0CR2 Registers from Being Changed Activation STOP, IDLE0 SLEEP0 Mode Transfer Data Format Infrared Data Format Transfer Mode Transfer Baud Rate
Transfer baud rate calculation method
width adjustment using UART0CR2<RTSEL> Calculation values UART0CR2<RTSEL> UART0DR
16.5.1 16.5.2
Transition register status Transition status
16.8.1
16.9 Data Sampling Method 16.10 Received Data Noise Rejection 16.11 Transmit/Receive Operation 16.12
16.11.1 16.11.2
16.8.1.1 16.8.1.2
Status Flag
Data transmit operation Data receive operation.
16.13 16.14 16.15
16.12.1 16.12.2 16.12.3 16.12.4 16.12.5 16.12.6
Receiving Process Properties Revision History.
IrDA properties.
Parity error Framing Error. Overrun error Receive Data Buffer Full. Transmit busy flag Transmit Buffer Full
16.14.1
Synchronous Serial Interface (SIO)
17.1 17.2 17.3 17.4 Configuration Control Power Consumption Function Functions
Transfer format Serial clock Transfer edge selection 8-bit transmit mode
Setting Starting transmit operation Transmit buffer shift operation Operation completion transmission Stopping transmit operation Setting Starting receive operation Operation completion reception Stopping receive operation
17.5
17.4.1 17.4.2 17.4.3 17.5.1
Transfer Modes
17.5.2
17.5.1.1 17.5.1.2 17.5.1.3 17.5.1.4 17.5.1.5 17.5.2.1 17.5.2.2 17.5.2.3 17.5.2.4 17.5.3.1 17.5.3.2 17.5.3.3 17.5.3.4 17.5.3.5
8-bit Receive Mode
17.5.3
8-bit transmit/receive mode
Setting Starting transmit/receive operation Transmit buffer shift operation Operation completion transmission/reception Stopping transmit/receive operation
17.6 17.7
Characteristics Revision History.
Serial Interface (SBI)
18.1 18.2 18.3 18.4 Communication Format Configuration Control Functions
Free data format 18.1.1 18.1.2
18.4.1 Power Consumption Function 18.4.2 Selecting slave address match detection GENERAL CALL detection. 18.4.3 Selecting number clocks data transfer selecting acknowledgement non-acknowledgment mode 18.4.4 18.4.5 18.4.6 18.4.7
18.4.3.1 18.4.3.2 18.4.4.1 18.4.4.2
Serial clock
Clock source Clock synchronization
Number clocks data transfer Output acknowledge signal
Master/slave selection Transmitter/receiver selection. Start/stop condition generation
18.5
18.4.8 Interrupt service request release 18.4.9 Setting serial interface mode 18.4.10 Software reset. 18.4.11 Arbitration lost detection monitor 18.4.12 Slave address match detection monitor. 18.4.13 GENERAL CALL detection monitor 18.4.14 Last received monitor. 18.4.15 Slave address address recognition mode specification 18.5.1 18.5.2 18.5.3 18.5.4 18.5.5
Data Transfer
Device initialization Start condition slave address generation. 1-word data transfer. Stop condition generation Restart
When SBI0SR2<MST> (Master mode) When SBI0SR2<MST> (Slave mode)
18.5.3.1 18.5.3.2
18.6 18.7
Specifications Revision History.
Key-on Wakeup (KWU)
19.1 19.2 19.3 Configuration Control Functions
10-bit Converter (ADC)
20.1 20.2 20.3 Configuration Control Functions
Single mode. Repeat mode operation disable forced stop operation.
20.4 20.5 20.6 20.7
20.3.1 20.3.2 20.3.3
Register Setting Starting STOP/IDLE0/SLOW Modes Analog Input Voltage Conversion Result Precautions about Converter
Analog input voltage range Analog input pins used input/output ports Noise countermeasure.
20.7.1 20.7.2 20.7.3
Flash Memory
21.1 21.2 Flash Memory Control Functions
Flash memory command sequence execution toggle control (FLSCR1 <FLSMD>) Flash memory area switching (FLSCR1<FAREA>). area switching (SYSCR3<RAREA>). BOOTROM area switching (FLSCR1<BAREA>). Flash memory standby control (FLSSTB<FSTB>) Port input control register (SPCR<PIN0, PIN1>)
21.3
21.2.1 21.2.2 21.2.3 21.2.4 21.2.5 21.2.6 21.3.1 21.3.2 21.3.3
Command Sequence
Byte program Sector erase (4-kbyte partial erase) Chip erase (all erase)
21.4 21.5
21.3.4 21.3.5 21.3.6
Toggle (D6) Access Flash Memory Area.
Flash memory control serial PROM mode Flash memory control mode
write flash memory transferring control program area write flash memory using support program (API) BOOTROM transfer write control program area loader mode serial PROM mode
Product entry Product exit Security program
21.5.1 21.5.2
21.5.1.1 21.5.2.1 21.5.2.2
21.6
Revision History.
Serial PROM Mode
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Outline Security Serial PROM Mode Setting Example Connection On-board Writing Activating Serial PROM Mode Interface Specifications Memory Mapping Operation Commands
Flash memory erase command (0xF0)
Specifying erase area
22.3.1
Serial PROM mode control pins
22.6.1 22.6.2
communication UART communication
22.8.1 22.8.2 22.8.3 22.8.4 22.8.5 22.8.6 22.8.7 22.8.8 22.8.9
22.8.1.1
Flash memory write command (operation command: 0x30). Flash memory read command (operation command: 0x40) loader command (operation command: 0x60) Flash memory output command (operation command: 0x90) Product code output command (operation command: 0xC0). Flash memory status output command (0xC3)
Flash memory status code
22.8.7.1
22.9 Error Code 22.10 Checksum (SUM) 22.11 22.12
22.10.1 22.10.2
Mask emulation setting command (0xD0) Flash memory security setting command (0xFA).
Intel Format (Binary) Security
Passwords
password specified Password structure Password setting, cancellation authentication Password values setting range security program functions Enabling disabling security program
Calculation method Calculation data
22.12.1
22.12.2
22.12.1.1 22.12.1.2 22.12.1.3 22.12.1.4 22.12.2.1 22.12.2.2
Security program
22.13 22.14
22.12.3 22.12.4
Flowchart Characteristics (UART)
Reset timing Flash memory erase command (0xF0) Flash memory write command (0x30). Flash memory read command (0x40) loader command (0x60) Flash memory output command (0x90)
Option codes. Recommended settings
22.14.1 22.14.2 22.14.3 22.14.4 22.14.5 22.14.6
viii
22.15
22.14.7 Product code output command (0xC0) 22.14.8 Flash memory status output command (0xC3) 22.14.9 Mask emulation setting command (0xD0) 22.14.10 Flash memory security setting command (0xFA).
Revision History.
On-chip Debug Function (OCD)
23.1 23.2 23.3 23.4 Features Control Pins Connect On-chip Debug Emulator Target System Security
Input/Output Circuit
24.1 Control Pins
Electrical Characteristics
25.1 25.2 Absolute Maximum Ratings Operating Conditions
mode (Flash Programming erasing) mode (Except Flash Programming erasing) Serial PROM mode
25.3 25.4 25.5 25.6 25.7
25.2.1 25.2.2 25.2.3
Characteristics. Conversion Characteristics Power-on Reset Circuit Characteristics Voltage Detecting Circuit Characteristics Characteristics
mode (Flash programming erasing) mode (Except Flash Programming erasing) Serial PROM mode
25.8
25.7.1 25.7.2 25.7.3 25.8.1
Flash Characteristics
Write characteristics
25.9 Recommended Oscillating Condition- 25.10 Handling Precaution 25.11 Revision History.
Package Dimensions
TMP89FS60
CMOS 8-Bit Microcontroller
TMP89FS60
TMP89FS60 single-chip 8-bit high-speed high-functionality microcomputer incorporating 61440 bytes Flash Memory.
Product TMP89FS60UG 61440 bytes TMP89FS60FG Note Under development 3072 bytes QFP64-P-1414-0.80A (Flash) Package LQFP64-P-1010-0.50D TMP89C900XBG Emulation Chip
Features
8-bit single chip microcomputer TLCS-870/C1 series Instruction execution time MHz) 32.768 kHz) types basic instructions interrupt sources (External Internal Except reset) Input Output ports pins)
Note above pins used port, because they should connected with high frequency input.
Large current output: pins (Typ. 20mA) Watchdog timer Interrupt reset selected program. Power-on reset circuit Voltage detection circuit Divider output function Time base timer 16-bit timer counter Timer, External trigger, Event Counter, Window, Pulse width measurement, OUTPUT modes
This product uses Super Flash® technology under licence Silicon Storage Technology, Inc. Super Flash® registered trademark Silicon Storage Technology, Inc.
information contained herein subject change without notice. 021023_D TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. 021023_B products described this document shall used embedded downstream products which manufacture, and/or sale prohibited under applicable laws regulations. 060106_Q information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patents other rights TOSHIBA third parties. 070122_C products described this document subject foreign exchange foreign trade control laws. 060925_E discussion reliability microcontrollers predicted, please refer Section chapter entitled Quality Reliability Assurance/Handling Precautions. 030619_S
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Features
TMP89FS60
8-bit timer counter: Timer, Event Counter, PWM, OUTPUT modes Usable 16-bit timer, 12-bit output 16-bit output cascade connection channels. Real time clock UART UART/SIO Note channels used same time. I2C/SIO Key-on wake-up 10-bit successive approximation type converter Analog input 16ch On-chip debug function Break/Event Trace monitor Flash memory writing Clock operation mode control circuit circuit Single clock mode Dual clock mode power consumption operation mode) STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: stops, only Time-Based-Timer(TBT) peripherals operate using high frequency clock. Released when reference time elapsed. IDLE1 mode: stops, peripherals operate using high frequency clock. Release interruputs(CPU restarts). IDLE2 mode: stops peripherals operate using high frequency clock. Release interruputs. (CPU restarts). SLEEP0 mode: stops, only Time-Based-Timer(TBT) peripherals operate using frequency clock. Released when reference time elapsed. SLEEP1 mode: stops, peripherals operate using frequency clock. Release interruput.(CPU restarts). Wide operation voltage:
8MHz /32.768 /32.768
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Assignment
(SO1/TXD1) (SI1/RXD1) (SCLK1) (TXD2) (RXD2)
Figure Assignment
Page
(XIN) (XOUT) MODE (XTIN) (XTOUT) (RESET) (STOP/INT5) (INT0) (INT1) (OCDCK/SO0/TXD0) (OCDIO/SI0/RXD0) (SCLK0) (SO0/SDA0) (SI0/SCL0)
(TC03/PPG03/PWM03) (TC02/PPG02/PWM02) (INT4) (INT3) (INT2) (DVO) (TCA1/PPGA1) (TCA0/PPGA0) (TC01/PPG01/PWM01) (TC00/PPG00/PWM00) (AIN15) (AIN14) (AIN13) (AIN12) (AIN11) (AIN10)
P51(AIN9) P50(AIN8) P47(AIN7/KWI7) P46(AIN6/KWI6) P45(AIN5/KWI5) P44(AIN4/KWI4) P43(AIN3/KWI3) P42(AIN2/KWI2) P41(AIN1/KWI1) P40(AIN0/KWI0) VAREF AVDD AVSS P25(SCLK0)
TMP89FS60
Block Diagram
TMP89FS60
Block Diagram
Figure Block Diagram
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TMP89FS60
Names Functions
TMP89FS60 mode, parallel PROM mode, serial PROM mode. Table shows functions mode. serial PROM mode explained later separate chapter. Table Names Functions(1/3)
Name XTOUT XTIN XOUT INT1
INT0
Input/Output
Functions PORT03 frequency output PORT02 frequency input PORT01 High frequency output PORT00 High frequency input PORT13 External interrupt input PORT12 External interrupt input PORT11 External interrupt input STOP mode release input PORT10 Reset signal input PORT27 PORT26 PORT25 Serial clock input/output PORT24 clock input/output Serial data input PORT23 data input/output Serial data output PORT22 Serial clock input/output PORT21 UART data input Serial data input data input/output PORT20 UART data output Serial data output clock input PORT47 Analog input Key-on wake-up input PORT46 Analog input Key-on wake-up input
INT5 STOP
RESET
SCLK0 SCL0 SDA0 SCLK0 RXD0 OCDIO TXD0 OCDCK AIN7 KWI7 AIN6 KWI6
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Names Functions
TMP89FS60
Table Names Functions(2/3)
Name AIN5 KWI5 AIN4 KWI4 AIN3 KWI3 AIN2 KWI2 AIN1 KWI1 AIN0 KWI0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 INT4 INT3 INT2
Input/Output PORT45 Analog input Key-on wake-up input PORT44 Analog input Key-on wake-up input PORT43 Analog input Key-on wake-up input PORT42 Analog input Key-on wake-up input PORT41 Analog input Key-on wake-up input PORT40 Analog input Key-on wake-up input PORT57 Analog input PORT56 Analog input PORT55 Analog input PORT54 Analog input PORT53 Analog input PORT52 Analog input PORT51 Analog input PORT50 Analog input PORT77 External interrupt input PORT76 External interrupt input PORT75 External interrupt input PORT74 Divider output PORT73 TCA1 input PPGA1 output PORT72 TCA0 input PPGA0 output
Functions
TCA1
PPGA1
TCA0
PPGA0
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TMP89FS60
Table Names Functions(3/3)
Name TC01
PPG01 PWM01
Input/Output PORT71 TC01 input PPG01 output PWM01 output PORT70 TC00 input PPG00 output PWM00 output PORT84 PORT83 PORT82 PORT81 TC03 input PPG03 output PWM03 output PORT80 TC02 input PPG02 output PWM02 output PORT94 UART data input PORT93 UART data output
Functions
TC00
PPG00 PWM00
TC03
PPG03 PWM03
TC02
PPG02 PWM02
RXD2 TXD2 SCLK1 RXD1 TXD1 MODE VAREF AVDD AVSS
PORT92 Serial clock input/output PORT91 UART data input Serial data input PORT90 UART data output Serial data output PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Test out-going test (fix level). Analog reference voltage input conversion. Analog power supply pin. Analog
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Names Functions
TMP89FS60
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TMP89FS60
Core
Configuration
core consists CPU, system clock controller reset circuit. This chapter describes core address space, system clock controller reset circuit.
Memory space
870/C1 memory space consists code area accessed instruction operation codes operands data area accessed sources destinations transfer calculation instructions. Both code data areas have independent 64-Kbyte address spaces.
2.2.1
Code area
code area stores operation codes, operands, vector tables vector call instructions interrupt vector tables. RAM, BOOTROM Flash mapped code area.
0x0000 0x003F 0x0040 0x0C3F instruction (0xFF) fetched. 0x1000 0x17FF 0x1800 Flash (61440 bytes) Flash (61440 bytes) Flash (59392 bytes) Flash (59392 bytes)
instruction (0xFF) fetched. (3072 bytes)
instruction (0xFF) fetched. (3072 bytes)
instruction (0xFF) fetched.
instruction (0xFF) fetched.
instruction (0xFF) fetched.
BOOTROM (2048 bytes)
BOOTROM (2048 bytes)
0xFFA0
0xFFBF
Vector table vector call instructions bytes)
Vector table vector call instructions bytes)
Vector table vector call instructions bytes)
Vector table vector call instructions bytes)
0xFFC8
0xFFFF
Interrupt vector table bytes) Immediately after reset release
Interrupt vector table bytes) When mapped code area
Interrupt vector table bytes) When BOOTROM mapped code area
Interrupt vector table bytes) When BOOTROM mapped code area
Note: Only first Kbytes BOOTROM mapped memory map, except serial PROM mode.
Figure Memory Code Area
2.2.1.1
mapped data area immediately after reset release.
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Core
Memory space TMP89FS60
setting SYSCR3<RAREA> writing 0xD4 SYSCR4, mapped 0x0040to 0x0C3F code area execute program. this time, setting SYSCR<RVCTR> writing 0xD4 SYSCR4, vector table vector call instructions interrupt except reset mapped RAM. serial PROM mode, mapped 0x0040 0x0C3F code area, regardless value SYSCR3<RAREA>. program executed using loader function.
Note When mapped code area, instruction fetched from 0x0040 0x0C3F. Note2: contents become unstable when power turned immediately after reset released. execute program using RAM, transfer program executed initialization routine.
System control register
SYSCR3 (0x0FDE) Symbol Read/Write After reset RVCTR RAREA (RSTDIS)
RAREA
Specifies mapping code area
mapped from 0x0040 0x0C3F code area. mapped from 0x0040 0x0C3F code area. Vector table vector call instructions Vector table interrupt 0xFFC8 0xFFFF code area 0x01C8 0x01FD code area
RVCTR
Specifies mapping vector table vector call instructions interrupts
0xFFA0 0xFFBF code area 0x01A0 0x01BF code area
Note value SYSCR3<RAREA> invalid until 0xD4 written into SYSCR4. Note assign vector address areas RAM, SYSCR3<RVCTR> SYSCR3<RAREA> "1". Note SYSCR3<RVCTR> using loader program. interrupt occurs with SYSCR3<RVCTR> "0", BOOTROM area referenced vector address and, therefore, program will function properly. Note Bits SYSCR3 read "0".
System control register
SYSCR4 (0x0FDF) Symbol Read/Write After reset SYSCR4
SYSCR4
Writes SYSCR3 data control code.
0xB2 0xD4 0x71
Enables contents SYSCR3<RSTDIS>. Enables contents SYSCR3<RAREA> SYSCR3 <RVCTR>. Enables contents IRSTSR<FCLR> Others Invalid
Note SYSCR4 write-only register, must accessed using read-modify-write instruction, such operation. Note After SYSCR3<RSTDIS> modified, SYSCR4 should written 0xB2 (Enable code SYSCR3<RSTDIS>) NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> enabled unexpected timing. Note After IRSTSR<FCLR> modified, SYSCR4 should written 0x71 (Enable code IRSTSR<FCLR> NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> enabled unexpected timing.
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System control status register
SYSSR4 (0x0FDF) Symbol Read/Write After reset RVCTRS RAREAS (RSTDIS)
RAREAS
Status mapping code area Status mapping vector address area
enabled SYSCR3<RAREA> data "0". enabled SYSCR3<RAREA> data "1". enabled SYSCR3<RVCTR> data "0". enabled SYSCR3<RVCTR> data "1".
RVCTRS
Note: Bits SYSSR4 read "0". Example: Program transfer (Transfer program saved data area RAM.)
TRANS_RAM: TRANSFER_START_ADDRESS PROGRAM_START_ADDRESS BYTE_OF_PROGRAM (DE) (HL), TRANS_RAM Destination address Source address Number bytes program executed Reading program transferred Writing program transferred Destination address increment Source address increment Have programs been transferred?
2.2.1.2
BOOTROM
BOOTROM mapped code area data area after reset release. Setting FLSMD<BAREA> maps BOOTROM 0x1000 0x17FF code area 0x1000 0x17FF data area. BOOTROM easily written into Flash using Application Programming Interface (API) integrated BOOTROM.
Note When BOOTROM mapped code area, instruction fetched from Flash instruction fetched, depending capacity internal Flash. Note Only first Kbytes BOOTROM mapped memory map, except serial PROM mode.
Flash memory control register
FLSCR1 (0x0FD0) Symbol Read/Write After reset (FLSMD) BAREA (FAREA) (ROMSEL)
BAREA
Specifies mapping BOOTROM code data areas
BOOTROM mapped 0x1000 0x17FF code area 0x1000 0x17FF data area. BOOTROM mapped 0x1000 0x17FF code area 0x1000 0x17FF data area.
Note: flash memory control register double-buffer structure comprised register FLSCR1 shift register. Writing "0xD5" register FLSCR2 allows register setting reflected take effect shift register. This means that register setting value does take effect until "0xD5" written register FLSCR2. value shift register checked reading register FLSCRM.
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Flash memory control register
FLSCR2 (0x0FD1) Symbol Read/Write After reset CR1EN
CR1EN
FLSCR1 register enable/disable control
0xD5 Others
Enable change FLSCR1 setting Reserved
2.2.1.3
Flash
Flash mapped 0x1000 0xFFFF code area after reset release.
2.2.2
Data area
data area stores data accessed sources destinations transfer calculation instructions. SFR, RAM, BOOTROM FLASH mapped data area.
0x0000 0x003F 0x0040 0x0C3F
SFR1 bytes) (3072 bytes) 0xFF read
SFR1 bytes) (3072 bytes) 0xFF read SFR3 (192 bytes) SFR2 (256 bytes) BOOTROM (2048 bytes)
0x0E40 0x0EFF 0x0F00 0x0FFF 0x1000 0x17FF 0x1800
SFR3 (192 bytes) SFR2 (256 bytes)
Flash (61440 bytes)
Flash (59392 bytes)
0xFFFF Immediately after reset release When BOOTROM mapped data area
Note: Only first Kbytes BOOTROM mapped memory map, except serial PROM mode.
Figure Memory Data Area
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2.2.2.1
mapped 0x0000 0x003F (SFR1), 0x0F00 0x0FFF (SFR2) 0x0E40 0x0EFF (SFR3) data area after reset release.
Note: Don't access reserved SFR.
2.2.2.2
mapped 0x0040 0x0C3F data area after reset release.
Note: contents become unstable when power turned immediately after reset released. execute program using RAM, transfer program executed initialization routine. Example: initialization program
RAM_TOP_ADDRESS 0x00 BYTE_OF_CLEAR_BYTES (HL), CLR_RAM Head address initialized Initialization data Number bytes initialized Initialization Initialization address increment Have RAMs been initialized?
CLR_RAM:
2.2.2.3
BOOTROM
BOOTROM mapped code area data area after reset release. Setting FLSMD<BAREA> maps BOOTROM 0x1000 0x17FF code area 0x1000 0x17FF data area. BOOTROM easily written into Flash using Application Programming Interface (API) integrated BOOTROM.
Note1: Only first Kbytes BOOTROM mapped memory map, except serial PROM mode.
Flash memory control register
FLSCR1 (0x0FD0) Symbol Read/Write After reset (FLSMD) BAREA (FAREA) (ROMSEL)
BAREA
Specifies mapping BOOTROM code data areas
BOOTROM mapped 0x1000 0x17FF code area 0x1000 0x17FF data area. BOOTROM mapped 0x1000 0x17FF code area 0x1000 0x17FF data area.
Note: flash memory control register double-buffer structure comprised register FLSCR1 shift register. Writing "0xD5" register FLSCR2 allows register setting reflected take effect shift register. This means that register setting value does take effect until "0xD5" written register FLSCR2. value shift register checked reading register FLSCRM.
Flash memory control register
FLSCR2 (0x0FD1) Symbol Read/Write After reset CR1EN
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CR1EN
FLSCR1 register enable/disable control
0xD5 Others
Enable change FLSCR1 setting Reserved
2.2.2.4
Flash
Flash mapped 0x1000 0xFFFF data area after reset release.
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System clock controller
2.3.1 Configuration
system clock controller consists clock generator, clock gear, timing generator, warm-up counter operation mode control circuit.
WUCCR WUCDR
Warm-up counter INTWUC interrupt XEN/XTEN STOP Clock generator TBTCR DV9CK SYSCR1 SYSCR2
High-frequency clock oscillation circuit
XOUT
Clock gear (x1/4,x1/2,x1) FCGCKSEL Clock gear control register
fcgck Timing generator Operation mode control circuit
System control register System clock
XTIN Low-frequency clock oscillation circuit XTOUT
Oscillation/stop control
Figure System Clock Controller
2.3.2
Control
system clock controller controlled system control register (SYSCR1), system control register (SYSCR2), warm-up counter control register (WUCCR), warm-up counter data register (WUCDR) clock gear control register (CGCR).
System control register
SYSCR1 (0x0FDC) Symbol Read/Write After reset STOP RELM OUTEN DV9CK
STOP
Activates STOP mode
Operate peripheral circuits Stop peripheral circuits (activate STOP mode) Edge-sensitive release mode (Release STOP mode rising edge STOP mode release signal) Level-sensitive release mode (Release STOP mode level STOP mode release signal) High impedance Output hold fcgck/29 fs/4
RELM
Selects STOP mode release method
OUTEN
Selects port output state STOP mode Selects input clock stage divider
DV9CK
Note fcgck: Gear clock [Hz], Low-frequency clock [Hz] Note Bits SYSCR1 read "0". read "1".
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Note STOP mode activated with SYSCR1<OUTEN> "0", port internal input fixed "0". Therefore, external interrupt falling edge, depending state when STOP mode activated. Note also used STOP pin. When STOP mode activated, reverts high impedance state input mode, regardless state SYSCR1<OUTEN>. Note Writing second byte data will executed improperly operation switched STOP state instruction, such LDW, which executes 2-byte data transfer time. Note Don't SYSCK1<DV9CK> before oscillation low-frequency clock oscillation circuit becomes stable. Note SLOW1/2 SLEEP1 mode, fs/4 input stage divider, regardless state SYSCR1< DV9CK
System control register
SYSCR2 (0x0FDD) Symbol Read/Write After reset XTEN SYSCK IDLE TGHALT
Controls high-frequency clock oscillation circuit Controls low-frequency clock oscillation circuit Selects system clock control (IDLE1/2 SLEEP1 mode) control (IDLE0 SLEEP0 mode)
Stop oscillation Continue start oscillation Stop oscillation Continue start oscillation Gear clock (fcgck) (NORMAL1/2 IDLE1/2 mode) Low-frequency clock (fs/4) (SLOW1/2 SLEEP1 mode) Operate Stop (Activate IDLE1/2 SLEEP1 mode) Enable clock supply from peripheral circuits Disable clock supply from peripheral circuits except (Activate IDLE0 SLEEP0 mode)
XTEN
SYSCK
IDLE
TGHALT
Note fcgck: Gear clock [Hz], Low-frequency clock [Hz] Note WDT: Watchdog timer, Timing generator Note Don't both SYSCR2<IDLE> SYSCR2<TGHALT> simultaneously. Note Writing second byte data will executed improperly operation switched IDLE state instruction, such LDW, which executes 2-byte data transfer time. Note When IDLE1/2 SLEEP1 mode released, SYSCR2<IDLE> cleared automatically. Note When IDLE0 SLEEP0 mode released, SYSCR2<TGHALT> cleared automatically. Note Bits SYSCR2 read "0".
Warm-up counter control register
WUCCR (0x0FCD) Symbol Read/Write After reset WUCRST WUCDIV WUCSEL
WUCRST
Resets stops warm-up counter
Clear stop counter Source clock Source clock Source clock Source clock Select high-frequency clock (fc) Select low-frequency clock (fs)
WUCDIV
Selects frequency division warm-up counter source clock
WUCSEL
Selects warm-up counter source clock
Note High-frequency clock [Hz], Low-frequency clock [Hz] Note WUCCR<WUCRST> cleared automatically, need cleared after being "1". Note Bits WUCCR read "0". read "1". Note Before starting warm-up counter operation, source clock frequency division rate WUCCR warm-up time WUCDR.
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Warm-up counter data register
WUCDR (0x0FCE) Symbol Read/Write After reset WUCDR
WUCDR
Warm-up time setting
Note Don't start warm-up counter operation with WUCDR "0x00".
Clock gear control register
CGCR (0x0FCF) Symbol Read/Write After reset FCGCKSEL
FCGCKSEL
Clock gear setting
fcgck fcgck fcgck Reserved
Note fcgck: Gear clock [Hz], High-frequency clock [Hz] Note Don't change CGCR<FCGCKSEL> SLOW mode. Note Bits CGCR read "0".
2.3.3
Functions
Clock generator
clock generator generates basic clock system clocks supplied core peripheral circuits. contains oscillation circuits: high-frequency clock other low-frequency clock. oscillation circuit pins also used ports setting them ports, refer chapter Ports. ports high-frequency clock oscillation circuits (the XOUT pins), P0FC0 then SYSCR2<XEN> "1". ports low-frequency clock oscillation circuits (the XTIN XTOUT pins), P0FC2 then SYSCR2<XTEN> "1". high-frequency (fc) clock low-frequency (fs) clock easily obtained connecting oscillator between XOUT pins between XTIN XTOUT pins respectively. Clock input from external oscillator also possible. this case, external clocks applied XIN/XTIN pins XOUT/XTOUT pins kept open. Enabling/disabling oscillation high-frequency clock oscillation circuit low-frequency clock oscillation circuit switching function ports controlled software hardware. software control executed SYSCR2<XEN>, SYSCR2<XTEN> port function control register P0FC.
2.3.3.1
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hardware control executed reset release operation mode control circuit when operation switched STOP mode described "2.3.5 Operation mode control circuit".
Note: hardware function available external direct monitoring basic clock. oscillation frequency adjusted programming system output pulses certain frequency port (for example, clock output) with interrupts disabled watchdog timer disabled monitoring output. adjustment program must created advance system that requires adjustment oscillation frequency.
prevent dead lock core software-controlled enabling/disabling oscillation, internal factor reset generated depending combination values clock selected main system clock, SYSCR2<XEN>, SYSCR2<XTEN> port function control register P0FC0. Table Prohibited Combinations Oscillation Enable Register Conditions
P0FC0 Don't Care SYSCR2 <XEN> SYSCR2 <XTEN> SYSCR2 <SYSCK> Don't Care State oscillation circuits stopped. low-frequency clock (fs) selected main system clock, low-frequency clock oscillation circuit stopped. high-frequency clock (fc) selected main system clock, high-frequency clock oscillation circuit stopped. high-frequency clock oscillation circuit allowed oscillate, port general-purpose port.
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Note: takes certain period time after SYSCR2<SYSCK> changed before main system clock switched. currently operating oscillation circuit stopped before main system clock switched, internal condition becomes shown Table system clock reset occurs. details clock switching, refer "2.3.6 Operation Mode Control".
High-frequency clock XOUT XOUT XTIN
Low-frequency clock XTOUT XTIN XTOUT
(Open)
(Open)
Crystal ceramic oscillator
External oscillator
Crystal oscillator
External oscillator
Figure Examples Oscillator Connection
2.3.3.2
Clock gear
clock gear circuit that selects gear clock (fcgck) obtained dividing high-frequency clock (fc) inputs timing generator. Selects divided clock CGCR<FCGCKSEL>. machine cycles needed after CGCR<FCGCKSEL> changed before gear clock (fcgck) changed. gear clock (fcgck) longer than clock width, immediately after CGCR<FCGCKSEL> changed.
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Immediately after reset release, gear clock (fcgck) becomes clock that quarter highfrequency clock (fc). Table Gear Clock (fcgck)
CGCR<FCGCKSEL> fcgck Reserved
Note: Don't change CGCR<FCGCKSEL> SLOW mode. This stop gear clock (fcgck) from being changed.
2.3.3.3
Timing generator
timing generator circuit that generates system clocks supplied core peripheral circuits, from gear clock (fcgck) clock that quarter low-frequency clock (fs). timing generator following functions: Generation main system clock (fm) Generation clocks timer counter, time base timer other peripheral circuits
Main system clock
Main system clock generator
Machine cycle counter
SYSCR2<SYSCK> SYSCR1<DV9CK> Prescaler Gear clock fcgck Divider Multiplexer quarter basic clock low-frequency clock Divider
Timer counter, time base timer other peripheral circuits
Figure Configuration Timing Generator
Configuration timing generator timing generator consists main system clock generator, prescaler, 21-stage divider machine cycle counter. Main system clock generator This circuit selects gear clock (fcgck) clock that quarter low-frequency clock (fs) main system clock (fm) operate core. Clearing SYSCR2<SYSCK> selects gear clock (fcgck). Setting selects clock that quarter low-frequency clock (fs). takes certain period time after SYSCR2<SYSCK> changed before main system clock switched. currently operating oscillation circuit stopped before main system clock switched, internal condition becomes shown Table system clock reset occurs. details clock switching, refer "2.3.6 Operation Mode Control".
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Prescaler divider These circuits divide fcgck. divided clocks supplied timer counter, time base timer other peripheral circuits. When both SYSCR1<DV9CK> SYSCR2<SYSCK> "0", input clock stage divider becomes output stage divider. When SYSCR1<DV9CK> SYSCR2<SYSCK> "1", input clock stage divider becomes fs/4. When SYSCR2<SYSCK> "1", outputs stages divider prescaler stopped. prescaler divider cleared reset warm-up operation that follows release STOP mode. Machine cycle Instruction execution synchronized with main system clock (fm). minimum instruction execution unit called "machine cycle". machine cycle corresponds main system clock. There total different types instructions TLCS-870/C1 Series: types ranging from 1-cycle instructions, which require machine cycle execution, 10cycle instructions, which require machine cycles execution, 13-cycle instructions, which require machine cycles execution.
2.3.4
Warm-up counter
warm-up counter circuit that counts high-frequency clock (fc) low-frequency clock (fs), consists source clock selection circuit, 3-stage frequency division circuit 14-stage counter. warm-up counter used secure time after power-on reset released before supply voltage becomes stable secure time after STOP mode released operation mode changed before oscillation oscillation circuit becomes stable.
WUCCR WUCSEL WUCDIV WUCRST
SYSCR2 XTEN STOP
SYSCR1
INTWUC interrupt
Warm-up counter controller
Clock high-frequency clock oscillation circuit (fc) Clock low-frequency clock oscillation circuit (fs) Enable/disable counting
Enable operation
Comparator
WUCDR
Figure Warm-up Counter Circuit
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2.3.4.1
Warm-up counter operation when oscillation enabled hardware
When power-on reset released reset released warm-up counter serves secure time after power-on reset released before supply voltage becomes stable time after reset released before oscillation high-frequency clock oscillation circuit becomes stable. When power turned supply voltage exceeds power-on reset release voltage, warm-up counter reset signal released. this time, peripheral circuits held reset state. reset signal initializes WUCCR<WUCSEL> WUCCR<WUCDIV> "11", which selects high-frequency clock (fc) input clock warm-up counter. When reset released warm-up counter, high-frequency clock (fc) input warm-up counter, 14-stage counter starts counting high-frequency clock (fc). When upper bits warm-up counter become equal WUCDR, counting stopped reset released peripheral circuits. WUCDR initialized 0x66 after reset release, which makes warm-up time 0x66 29/fc[s].
Note: clock output from oscillation circuit used input clock warm-up counter. warm-up time contains errors because oscillation frequency unstable until oscillation circuit becomes stable.
When STOP mode released warm-up counter serves secure time after oscillation enabled hardware before oscillation becomes stable release STOP mode. high-frequency clock (fc) low-frequency clock (fs), which generates main system clock when STOP mode activated, selected input clock frequency division circuit, regardless WUCCR<WUCSEL>. Before STOP mode activated, select division rate input clock warm-up counter WUCCR<WUCDIV> warm-up time WUCDR. When STOP mode released, 14-stage counter starts counting input clock selected frequency division circuit. When upper bits warm-up counter become equal WUCDR, counting stopped operation restarted instruction that follows STOP mode activation instruction.
Clock that generates main system clock when STOP mode activated
WUCCR<WUCSEL>
WUCCR<WUCDIV>
Counter input clock
Warm-up time
Don't Care Don't Care
Note When operation switched STOP mode during warm-up oscillation enabled software, warm-up counter holds value time, restarts counting after STOP mode released. this case, warm-up time release STOP mode becomes insufficient. Don't switch operation STOP mode during warm-up oscillation enabled software.
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Note clock output from oscillation circuit used input clock warm-up counter. warm-up time contains errors because oscillation frequency unstable until oscillation circuit becomes stable. sufficient time oscillation start property oscillator.
2.3.4.2
Warm-up counter operation when oscillation enabled software
warm-up counter serves secure time after oscillation enabled software before oscillation becomes stable, mode change from NORMAL1 NORMAL2 from SLOW1 SLOW2. Select input clock frequency division circuit WUCCR<WUCSEL>. Select input clock 14-stage counter WUCCR<WUCDIV>. After warm-up time WUCDR, setting SYSCR2<XEN> SYSCR2<XTEN> allows stopped oscillation circuit start oscillation 14-stage counter start counting selected input clock. When upper bits counter become equal WUCDR, INTWUC interrupt occurs, counting stopped counter cleared. WUCCR<WUCRST> discontinue warm-up operation. setting "1", count-up operation stopped, warm-up counter cleared, WUCCR<WUCRST> cleared "0". SYSCR2<XEN> SYSCR2<XTEN> hold values when WUCCR<WUCRST> "1". restart warm-up operation, SYSCR2<XEN> SYSCR2<XTEN> must cleared "0".
Note: warm-up counter starts counting when SYSCR2<XEN> SYSCR2<XTEN> changed from "1". counter will start counting writing SYSCR2<XEN> SYSCR2<XTEN> when state "1".
WUCCR<WUCSEL>
WUCCR<WUCDIV>
Counter input clock
Warm-up time
Note: clock output from oscillation circuit used input clock warm-up counter. warm-up time contains errors because oscillation frequency unstable until oscillation circuit becomes stable. sufficient time oscillation start property oscillator.
2.3.5
Operation mode control circuit
operation mode control circuit starts stops oscillation circuits high-frequency lowfrequency clocks, switches main system clock (fm). There three operating modes: single-clock mode, dual-clock mode STOP mode. These modes controlled system control registers (SYSCR1 SYSCR2). Figure shows operating mode transition diagram.
2.3.5.1
Single-clock mode
Only gear clock (fcgck) used operation single-clock mode.
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main system clock (fm) generated from gear clock (fcgck). Therefore, machine cycle time 1/fcgck [s]. gear clock (fcgck) generated from high-frequency clock (fc). single-clock mode, low-frequency clock generation circuit pins (XTIN) (XTOUT) used ports.
NORMAL1 mode this mode, core peripheral circuits operate using gear clock (fcgck). NORMAL1 mode becomes active after reset release.
IDLE1 mode this mode, watchdog timer stop peripheral circuits operate using gear clock (fcgck). IDLE1 mode activated setting SYSCR2<IDLE> NORMAL1 mode. When IDLE1 mode activated, watchdog timer stop. When interrupt latch enabled interrupt enable register becomes "1", IDLE1 mode released NORMAL1 mode. When (interrupt master enable flag) (interrupts enabled), operation returns normal after interrupt processing completed. When (interrupts disabled), operation restarted instruction that follows IDLE1 mode activation instruction.
IDLE0 mode this mode, peripheral circuits stop, except oscillation circuits time base timer. IDLE0 mode, peripheral circuits stop states when IDLE0 mode activated become same states when reset released. operations peripheral circuits IDLE0 mode, refer section each peripheral circuit. IDLE0 mode activated setting SYSCR2<TGHALT> NORMAL1 mode. When IDLE0 mode activated, stops timing generator stops clock supply peripheral circuits except time base timer. When falling edge source clock selected TBTCR<TBTCK> detected, IDLE0 mode released, timing generator starts clock supply peripheral circuits NORMAL1 mode restored. Note that IDLE0 mode activated restarted, regardless setting TBTCR<TBTEN>. When IDLE0 mode activated with TBTCR<TBTEN> "1", INTTBT interrupt latch after NORMAL mode restored. When (the individual interrupt enable flag time base timer) "1", operation returns normal after interrupt processing completed. When when (the individual interrupt enable flag time base timer) "0", operation restarted instruction that follows IDLE0 mode activation instruction.
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2.3.5.2
Dual-clock mode
gear clock (fcgck) low-frequency clock (fs) used operation dual-clock mode. main system clock (fm) generated from gear clock (fcgck) NORMAL2 IDLE2 mode, generated from clock that quarter low-frequency clock (fs) SLOW1/2 SLEEP0/1 mode. Therefore, machine cycle time 1/fcgck NORMAL2 IDLE2 mode 4/fs SLOW1/2 SLEEP0/1 mode. (XTIN) (XTOUT) used low-frequency clock oscillation circuit pins. (These pins cannot used ports dual-clock mode.) operation TLCS-870/C1 Series becomes single-clock mode after reset release. operate dual-clock mode, allow low-frequency clock oscillate beginning program.
NORMAL2 mode this mode, core operates using gear clock (fcgck), peripheral circuits operate using gear clock (fcgck) clock that quarter low-frequency clock (fs).
SLOW2 mode this mode, core peripheral circuits operate using clock that quarter low-frequency clock (fs). SLOW mode, some peripheral circuits become same states when reset released. operations peripheral circuits SLOW mode, refer section each peripheral circuit. SYSCR2<SYSCK> switch operation mode from NORMAL2 SLOW2 from SLOW2 NORMAL2. SLOW2 mode, outputs prescaler stages divider stop.
SLOW1 mode this mode, high-frequency clock oscillation circuit stops operation core peripheral circuits operate using clock that quarter low-frequency clock (fs). This mode requires less power operate high-frequency clock oscillation circuit than SLOW2 mode. SLOW mode, some peripheral circuits become same states when reset released. operations peripheral circuits SLOW mode, refer section each peripheral circuit. SYSCR2<XEN> switch operation between SLOW1 SLOW2 modes. SLOW1 SLEEP1 mode, outputs prescaler stages divider stop.
IDLE2 mode this mode, watchdog timer stop peripheral circuits operate using gear clock (fcgck) clock that quarter low-frequency clock (fs). IDLE2 mode activated released same IDLE1 mode. operation returns NORMAL2 mode after this mode released.
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SLEEP1 mode this mode, high-frequency clock oscillation circuit stops operation, watchdog timer stop, peripheral circuits operate using clock that quarter low-frequency clock (fs). SLEEP1 mode, some peripheral circuits become same states when reset released. operations peripheral circuits SLEEP1 mode, refer section each peripheral circuit. SLEEP1 mode activated released same IDLE1 mode. operation returns SLOW1 mode after this mode released. SLOW1 SLEEP1 mode, outputs prescaler stages divider stop.
SLEEP0 mode this mode, high-frequency clock oscillation circuit stops operation, time base timer operates using clock that quarter low-frequency clock (fs), core peripheral circuits stop. SLEEP0 mode, peripheral circuits stop states when SLEEP0 mode activated become same states when reset released. operations peripheral circuits SLEEP0 mode, refer section each peripheral circuit. SLEEP0 mode activated released same IDLE0 mode. operation returns SLOW1 mode after this mode released. SLEEP0 mode, stops timing generator stops clock supply peripheral circuits except time base timer.
2.3.5.3
STOP mode
this mode, operations system, including oscillation circuits, stopped internal states effect before system stopped held with power consumption. STOP mode, peripheral circuits stop states when STOP mode activated become same states when reset released. operations peripheral circuits STOP mode, refer section each peripheral circuit. STOP mode activated setting SYSCR1<STOP> "1". STOP mode released STOP mode release signals. After warm-up time elapsed, operation returns mode that active before STOP mode, operation restarted instruction that follows STOP mode activation instruction.
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2.3.5.4
Transition operation modes
RESET Reset release IDLE0 mode
Warm-up that follows reset release
Warm-up completed SYSCR2<TGHA (Note SYSCR2<IDLE> IDLE0 mode Interrupt Single-clock mode SYSCR2<XTEN> SYSCR2<IDLE> NORMAL2 mode Interrupt SYSCR2<SYSCK> SYSCR2<SYSCK> STOP mode release signal STOP NORMAL1 mode STOP mode release signal SYSCR2<XTEN> SYSCR1<STOP> SYSCR1<STOP>
IDLE2 mode
SLOW2 mode SYSCR2<XEN> SYSCR2<XEN> SYSCR2<IDLE> SLEEP1 mode Interrupt Dual-clock mode SLEEP0 mode SLOW1 mode STOP mode release (Note SYSCR2<TGHALT> signal SYSCR1<STOP>
Note NORMAL1 NORMAL2 modes generically called NORMAL mode; SLOW1 SLOW2 modes called SLOW mode; IDLE0, IDLE1 IDLE2 modes called IDLE mode; SLEEP0 SLEEP1 called SLEEP mode. Note mode released falling edge source clock selected TBTCR<TBTCK>.
Figure Operation Mode Transition Diagram
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Table Operation Modes Conditions
Oscillation circuit Operation mode High-frequency Low-frequency core Watchdog timer Time base timer Other peripheral circuits Machine cycle time
RESET NORMAL1 Oscillation Single clock IDLE1 IDLE0 STOP Stop Stop
Reset Operate
Reset Operate
Reset
Reset
Operate Operate Stop Stop Stop Stop Operate with high frequency Operate with high/low frequency Stop Operate with frequency Operate with frequency
fcgck
NORMAL2
fcgck
IDLE2
Oscillation
Stop Operate with frequency Operate with frequency
SLOW2 Oscillation Dual clock SLOW1
Operate Operate
SLEEP1 SLEEP0 STOP
Stop Stop Stop Stop Stop Stop
2.3.6
Operation Mode Control
STOP mode
STOP mode controlled system control register (SYSCR1) STOP mode release signals.
2.3.6.1
Start STOP mode STOP mode started setting SYSCR1<STOP> "1". STOP mode, following states maintained: Both high-frequency low-frequency clock oscillation circuits stop oscillation internal operations stopped. data memory, registers program status word held states effect before STOP mode started. port output latch determined value SYSCR1<OUTEN>. prescaler divider timing generator cleared "0". program counter holds address instruction ahead instruction (e.g., [SET (SYSCR1).7]) which started STOP mode.
Release STOP mode STOP mode released following STOP mode release signals. also released reset RESET pin, power-on reset reset voltage detection circuits. When reset released, warm-up starts. After warm-up completed, NORMAL1 mode becomes active. Release STOP
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Release key-on wakeup Release voltage detection circuits
Note: During STOP period (from start STOP mode warm-up), changes external interrupt signal, interrupt latches interrupts accepted immediately after STOP mode released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode released, clear unnecessary interrupt latches.
Release STOP Release STOP mode using STOP pin. release STOP mode using STOP pin, VDCR2<VDSS> "00" "10". (For details VDCR2, refer section voltage detection circuits.) STOP mode release STOP includes level-sensitive release mode edge-sensitive release mode, either which selected SYSCR1<RELM>. STOP also used port INT5 (external interrupt input pin. Level-sensitive release mode STOP mode released setting STOP high. Setting SYSCR1<RELM> selects level-sensitive release mode. This mode used capacitor backup when main power supply long term battery backup. Even instruction starting STOP mode executed while STOP input high, STOP mode does start. Thus, start STOP mode levelsensitive release mode, necessary program first confirm that STOP input low. This confirmed testing port software using interrupts
Note: When STOP mode released, warm-up counter source clock automatically changes clock that generated main system clock when STOP mode started, regardless WUCCR<WUCSEL>.
Example: Starting STOP mode from SLOW mode with INT5 interrupt (Warm-up time release STOP mode about 450ms fs=32.768 KHz.)
PINT5: TEST SINT5: RETI (SYSCR1).7 (P0PRD).5 SINT5 (SYSCR1), 0x40 (WUCCR), 0x03 (WUCDR),0xE8 reject noise, STOP mode does start STOP input high. Sets level-sensitive release mode WUCCR<WUCDIV> division) (Note) Sets warm-up time ms/1.953 230.4 round 0xE8 Starts STOP mode
Note: When STOP mode released, warm-up counter source clock automatically changes clock that generated main system clock when STOP mode started, regardless WUCCR<WUCSEL>.
STOP
XOUT NORMAL mode STOP mode Confirm program that STOP input start STOP mode. Warm-up NORMAL mode
STOP mode released hardware. Always released STOP input high.
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Even STOP input returns after warm-up starts, STOP mode restarted.
Figure Level-sensitive Release Mode (Example when high-frequency clock oscillation circuit selected)
Edge-sensitive release mode this mode, STOP mode released rising edge STOP input. Setting SYSCR1<RELM> selects edge-sensitive release mode. This used applications where relatively short program executed repeatedly periodic intervals. This periodic signal (for example, clock from low-power consumption oscillator) input STOP pin. edge-sensitive release mode, STOP mode started even when STOP input high
Example: Starting STOP mode from NORMAL mode (Warm-up time release STOP mode about 200ms fc=8 MHz.)
(SYSCR1) 0x80 (WUCCR),0x01 (WUCDR),0x19 WUCCR<WUCDIV> division) (Note) Sets warm-up time 200ms 0x19 Starts STOP mode with edge-sensitive release mode selected
Note: When STOP mode released, warm-up counter source clock automatically changes clock that generated main system clock when STOP mode started, regardless WUCCR<WUCSEL>.
STOP
XOUT NORMAL mode STOP mode started program. STOP mode
Warm-up
NORMAL mode
STOP mode
STOP mode released hardware rising edge STOP input.
Note: rising edge input STOP within machine cycle after SYSCR1<STOP> "1", STOP mode will released.
Figure Edge-sensitive Release Mode (Example when high-frequency clock oscillation circuit selected)
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Release key-on wakeup STOP mode released inputting prescribed level key-on wakeup pin. level release STOP mode selected from "L". release key-on wakeup, refer section "Key-on Wakeup".
Note: key-on wakeup input becomes opposite level release level after warm-up starts, STOP mode restarted.
Release voltage detection circuits STOP mode released supply voltage detection voltage detection circuits. release STOP mode using voltage detection circuits, VDCR2<VDSS> "01" "10". voltage detection operation mode voltage detection circuits generate reset signals (when VDCR2<VDxMOD> (x=1 2)), STOP mode released reset applied soon supply voltage becomes lower than detection voltage. When supply voltage becomes equal higher than detection voltage voltage detection circuits, reset released warm-up starts. After warm-up completed, NORMAL1 mode becomes active. voltage detection operation mode voltage detection circuits generate interrupt request signals (when VDCR2<VDxMOD> (x=1 2)), STOP mode released when supply voltage becomes equal higher than detection voltage. details, refer section voltage detection circuits.
Note: supply voltage becomes equal higher than detection voltage within machine cycle after SYSCR1<STOP> "1", STOP mode will released.
STOP mode release operation STOP mode released following sequence: Oscillation starts. oscillation start operation each mode, refer "Table Oscillation Start Operation Release STOP Mode". Warm-up executed secure time required stabilize oscillation. internal operations remain stopped during warm-up. warm-up time warm-up counter, depending oscillator characteristics. After warm-up time elapsed, normal operation restarted instruction that follows STOP mode start instruction. this time, prescaler divider timing generator cleared "0".
Note: When STOP mode released with hold voltage, following cautions must observed. supply voltage must operating voltage level before releasing STOP mode. RESET input must also level, rising together with supply voltage. this case, external time constant circuit been connected, RESET input voltage will increase slower pace than power supply voltage. this time, there danger that reset occur input voltage level RESET drops below non-inverting high-level input voltage (Hysteresis input).
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Table Oscillation Start Operation Release STOP Mode
Operation mode before STOP mode started High-frequency clock High-frequency clock oscillation circuit Low-frequency clock Oscillation start operation after release high-frequency clock oscillation circuit starts oscillation. low-frequency clock oscillation circuit stops oscillation. high-frequency clock oscillation circuit starts oscillation. low-frequency clock oscillation circuit starts oscillation. high-frequency clock oscillation circuit stops oscillation. low-frequency clock oscillation circuit starts oscillation.
Single-clock mode
NORMAL1
NORMAL2 Dual-clock mode SLOW1
High-frequency clock oscillation circuit
Low-frequency clock oscillation circuit
Low-frequency clock oscillation circuit
Note: When operation returns NORMAL2 mode, input frequency division circuit warm-up counter.
2.3.6.2
IDLE1/2 SLEEP1 modes
IDLE1/2 SLEEP1 modes controlled system control register (SYSCR2) maskable interrupts. following states maintained during these modes. watchdog timer stop their operations. peripheral circuits continue operate. data memory, registers, program status word port output latches held status effect before IDLE1/2 SLEEP1 mode started. program counter holds address instruction ahead instruction which starts IDLE1/2 SLEEP1 mode.
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Starting IDLE1/2 mode SLEEP1 mode instruction
stop
Reset input Interrupt request (Normal release mode)
Reset
(Interrupt release mode)
Interrupt processing
Execution instruction which follows IDLE1/2 mode SLEEP1 mode start instruction
Figure 2-10 IDLE1/2 SLEEP Modes
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Start IDLE1/2 SLEEP1 modes After interrupt master enable flag (IMF) "0", individual interrupt enable flag (EF) "1", which releases IDLE1/2 SLEEP1 modes. start IDLE1/2 SLEEP1 mode, SYSCR2<IDLE> "1". release condition satisfied when attempted start IDLE1/2 SLEEP1 mode, SYSCR2<IDLE> remains cleared IDLE1/2 SLEEP1 mode will started.
Note When watchdog timer interrupt generated immediately before IDLE1/2 SLEEP1 mode started, watchdog timer interrupt will processed IDLE1/2 SLEEP1 mode will started. Note Before starting IDLE1/2 SLEEP1 mode, enable interrupt request signals generated release IDLE1/2 SLEEP1 mode individual interrupt enable flag.
Release IDLE1/2 SLEEP1 modes IDLE1/2 SLEEP1 modes include normal release mode interrupt release mode. These modes selected interrupt master enable flag (IMF). After releasing IDLE1/2 SLEEP1 mode, SYSCR2<IDLE> automatically cleared operation mode returned mode preceding IDLE1/2 SLEEP1 mode. IDLE1/2 SLEEP1 modes also released reset RESET pin, power-on reset reset voltage detection circuits. After releasing reset, warm-up starts. After warm-up completed, NORMAL1 mode becomes active. Normal release mode (IMF "0") IDLE1/2 SLEEP1 mode released when interrupt latch enabled individual interrupt enable flag (EF) "1". operation restarted instruction that follows IDLE1/2 SLEEP1 mode start instruction. Normally, interrupt latch (IL) interrupt source used releasing must cleared load instructions. Interrupt release mode (IMF "1") IDLE1/2 SLEEP1 mode released when interrupt latch enabled individual interrupt enable flag (EF) "1". After interrupt processed, operation restarted instruction that follows IDLE1/2 SLEEP1 mode start instruction.
2.3.6.3
IDLE0 SLEEP0 modes
IDLE0 SLEEP0 modes controlled system control register (SYSCR2) time base timer control register (TBTCR). following states maintained during IDLE0 SLEEP0 modes: timing generator stops clock supply peripheral circuits except time base timer. data memory, registers, program status word port output latches held states effect before IDLE0 SLEEP0 mode started. program counter holds address instruction ahead instruction which starts IDLE0 SLEEP0 mode.
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Stopping peripherals instructions
Starting IDLE0 SLEEP0 mode instruction
stop
Reset input
source clock falling edge
Reset
TBTCR<TBTEN> interrupt enabled (Interrupt release mode)
(Normal release mode)
Interrupt processing
Execution instruction which follows IDLE0 SLEEP0 mode start instruction
Figure 2-11 IDLE0 SLEEP0 Modes
Start IDLE0 SLEEP0 modes Stop (disable) peripherals such timer counter. start IDLE0 SLEEP0 mode, SYSCR2<TGHALT> "1". Release IDLE0 SLEEP0 modes IDLE0 SLEEP0 modes include normal release mode interrupt release mode. These modes selected interrupt master enable flag (IMF), individual interrupt enable flag (EF5) time base timer TBTCR<TBTEN>. After releasing IDLE0 SLEEP0 mode, SYSCR2<TGHALT> automatically cleared operation mode returned mode preceding IDLE0 SLEEP0 mode. TBTCR<TBTEN> been "1", INTTBT interrupt latch set. IDLE0 SLEEP0 modes also released reset RESET pin, power-on reset reset voltage detection circuits. When reset released, warm-up starts. After warm-up completed, NORMAL1 mode becomes active.
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Normal release mode (IMF, EF5, TBTCR<TBTEN> "0") IDLE0 SLEEP0 mode released when falling edge source clock selected TBTCR<TBTCK> detected. After IDLE0 SLEEP0 mode released, operation restarted instruction that follows IDLE0 SLEEP0 mode start instruction. When TBTCR<TBTEN> "1", time base timer interrupt latch set.
Interrupt release mode (IMF, EF5, TBTCR<TBTEN> "1") IDLE0 SLEEP0 mode released when falling edge source clock selected TBTCR<TBTCK> detected. After release, INTTBT interrupt processing started.
Note IDLE0 SLEEP0 mode released NORMAL1 SLOW1 mode asynchronous internal clock selected TBTCR<TBTCK>. Therefore, period from start release mode shorter than time specified TBTCR<TBTCK>. Note When watchdog timer interrupt generated immediately before IDLE0 SLEEP0 mode started, watchdog timer interrupt will processed IDLE0 SLEEP0 mode will started.
2.3.6.4
SLOW mode
SLOW mode controlled system control register (SYSCR2).
Switching from NORMAL2 mode SLOW1 mode SYSCR2<SYSCK> "1". When maximum 2/fcgck 10/fs elapsed since SYSCR2<SYSCK> "1", main system clock (fm) switched fs/4. After switching, wait machine cycles longer, then clear SYSCR2<XEN> turn high-frequency clock oscillator. oscillation low-frequency clock (fs) unstable, confirm stable oscillation warm-up counter before implementing procedure described above.
Note sure follow this procedure switch operation from NORMAL2 mode SLOW1 mode. Note also possible allow basic clock high-frequency clock oscillate continuously return NORMAL2 mode. However, sure turn oscillation basic clock high-frequency clock when STOP mode started from SLOW mode. Note After switching SYSCR2<SYSCK>, sure wait machine cycles longer before clearing SYSCR2<XEN> "0". Clearing within machine cycles causes system clock reset. Note When main system clock (fm) switched, gear clock (fcgck) synchronized with clock that quarter basic clock (fs) low-frequency clock. synchronization, stopped period 10/fs shorter.
Quarter low-frequency clock (fs/4) Gear clock (fcgck)
SYSCR2<SYSCK>
Main system clock
10/fs (max.) When rising edge fcgck When rising edge fs/4 detected detected twice after SYSCR2<SYSCK> twice after stopped, switched changed from stopped synchronization.
Figure 2-12 Switching Main System Clock (fm) (Switching from fcgck fs/4)
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Example Switching from NORMAL2 mode SLOW1 mode (when used basic clock high-frequency clock)
(SYSCR2).4 SYSCR2<SYSCK> (Switches main system clock basic clock low-frequency clock SLOW2 mode) (SYSCR2).6 SYSCR2<XEN> (Turns high-frequency clock oscillation circuit) Waits machine cycles
Example Switching SLOW1 mode after stable oscillation low-frequency clock oscillation circuit confirmed warm-up counter (fs=32.768KHz, warm-up time about
#### Initialize routine #### (WUCCR), 0x02 (WUCDR), 0x33 WUCCR<WUCDIV> division) WUCCR<WUCSEL> (Selects source clock) Sets warm-up time (Determines time depending oscillator characteristics) ms/1.95 51.2 round 0x33 Enables INTWUC interrupts SYSCR2<XTEN> (Starts low-frequency clock oscillation starts warm-up counter) (P0FC).2 P0FC2 (Uses P02/03 oscillators)
(EIRL).4 (SYSCR2).5
#### Interrupt service routine warm-up counter interrupts #### PINTWUC: RETI VINTWUC: PINTWUC INTWUC vector table (SYSCR2).6 SYSCR2<XEN> (Turns high-frequency clock oscillation circuit) (SYSCR2).4 SYSCR2<SYSCK> (Switches main system clock low-frequency clock) Waits machine cycles
Switching from SLOW1 mode NORMAL1 mode SYSCR2<XEN> enable high-frequency clock (fc) oscillate. Confirm warm-up counter that oscillation basic clock high-frequency clock stabilized, then clear SYSCR2<SYSCK> "0". When maximum 8/fs 2.5/fcgck elapsed since SYSCR2<SYSCK> cleared "0", main system clock (fm) switched fcgck. After switching, wait machine cycles longer, then clear SYSCR2<XTEN> turn low-frequency clock oscillator. SLOW mode also released reset RESET pin, power-on reset reset voltage detection circuits. When reset released, warm-up starts. After warm-up completed, NORMAL1 mode becomes active.
Note sure follow this procedure switch operation from SLOW1 mode NORMAL1 mode. Note After switching SYSCR2<SYSCK>, sure wait machine cycles longer before clearing SYSCR2<XTEN> "0". Clearing within machine cycles causes system clock reset. Note When main system clock (fm) switched, gear clock (fcgck) synchronized with clock that quarter basic clock (fs) low-frequency clock. synchronization, stopped period 2.5/fcgck shorter. Note When P0FC0 "0", setting SYSCR2<XEN> causes system clock reset. Note When SYSCR2<XEN> "1", writing SYSCR2<XEN> does cause warm-up counter start counting source clock.
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Quarter low-frequency clock (fs/4) Gear clock (fcgck)
SYSCR2<SYSCK>
2.5/fcgck(max.)
Main system clock When rising edge fs/4 When rising edge fcgck detected detected twice after SYSCR2<SYSCK> twice after stopped, switched fcgck. changed from stopped synchronization.
Figure 2-13 Switching Main System Clock (fm) (Switching from fs/4 fcgck)
Example Switching from SLOW1 mode NORMAL1 mode after stability high-frequency clock oscillation circuit confirmed warm-up counter MHz, warm-up time
#### Initialize routine #### (WUCCR), 0x09 (WUCDR), 0x7D WUCCR<WUCDIV> (Divided WUCCR<WUCSEL> (Selects source clock) Sets warm-up time (Determine time depending frequency oscillator characteristics) 32us 0x7D Enables INTWUC interrupts SYSCR2<XEN> (Starts oscillation high-frequency clock oscillation circuit) (P0FC).2 P0FC2 (Uses P02/03 oscillators)
(EIRL). (SYSCR2)
#### Interrupt service routine warm-up counter interrupts #### PINTWUC: RETI VINTWUC: PINTWUC INTWUC vector table (SYSCR2). SYSCR2<XTEN> (Turns low-frequency clock oscillation circuit) (SYSCR2). SYSCR2<SYSCK> (Switches main system clock gear clock) Waits machine cycles
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Reset Control Circuit TMP89FS60
Reset Control Circuit
reset circuit controls external internal factor resets initializes system.
2.4.1
Configuration
reset control circuit consists following reset signal generation circuits: External reset input (external factor) Power-on reset (internal factor) Voltage detection reset (internal factor) Voltage detection reset (internal factor) Watchdog timer reset (internal factor) System clock reset (internal factor) Trimming data reset (internal factor) Flash standby reset (internal factor)
P10(RESET) Power-on reset signal
port
Internal factor reset detection status register, Voltage detection circuit reset signal External reset input enable reset signal
Voltage detection reset signal Voltage detection reset signal Watchdog timer reset signal System clock reset signal Trimming data reset signal Flash standby reset signal
Warm-up counter
Warm-up counter reset signal
CPU/peripheral circuits reset signal
System clock control circuit
Figure 2-14 Reset Control Circuit
2.4.2
Control
reset control circuit controlled system control register (SYSCR3), system control register (SYSCR4), system control status register (SYSSR4) internal factor reset detection status register (IRSTSR).
System control register
SYSCR3 (0x0FDE) Symbol Read/Write After reset (RVCTR) (RAREA) RSTDIS
RSTDIS
External reset input enable register
Enables external reset input. Disables external reset input.
Note enabled SYSCR3<RSTDIS> initialized power-on reset only, cannot initialized external reset input internal factor reset. value written SYSCR3 reset power-on reset, external reset input internal factor reset. Note value SYSCR3<RSTDIS> invalid until 0xB2 written into SYSCR4.
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Note After SYSCR3<RSTDIS> modified, SYSCR4 should written 0xB2 (Enable code SYSCR3<RSTDIS>) NORMAL1 mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> enabled unexpected timing. Note Bits SYSCR3 read "0".
System control register
SYSCR4 (0x0FDF) Symbol Read/Write After reset SYSCR4
SYSCR4
Writes SYSCR3 data control code.
0xB2 Enables contents SYSCR3<RSTDIS>. 0xD4 Enables contents SYSCR3<RAREA> SYSCR3 <RVCTR>. 0x71 Enables contents IRSTSR<FCLR> Others Invalid
Note SYSCR4 write-only register, must accessed using read-modify-write instruction, such operation. Note After SYSCR3<RSTDIS> modified, SYSCR4 should written 0xB2 (Enable code SYSCR3<RSTDIS>) NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> enabled unexpected timing. Note After IRSTSR<FCLR> modified, SYSCR4 should written 0x71 (Enable code IRSTSR<FCLR> NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> enabled unexpected timing.
System control status register
SYSSR4 (0x0FDF) Symbol Read/Write After reset (RVCTRS) (RAREAS) RSTDISS
RSTDISS
External reset input enable status
enabled SYSCR3<RSTDIS> data "0". enabled SYSCR3<RSTDIS> data "1".
Note enabled SYSCR3<RSTDIS> initialized power-on reset only, cannot initialized other reset signals. value written SYSCR3 reset power-on reset other reset signals. Note Bits SYSCR4 read "0".
Internal factor reset detection status register
IRSTSR (0x0FCC) Symbol Read/Write After reset FCLR FLSRF TRMDS TRMRF LVD2RF LVD1RF SYSRF WDTRF
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FCLR
Flag initialization control
Clears internal factor reset flag "0". Detects flash standby reset. Detect state abnormal trimming data Detects trimming data reset. Detects voltage detection reset. Detects voltage detection reset. Detects system clock reset. Detects watchdog timer reset.
FLSRF
Flash standby reset detection flag
TRMDS
Trimming data status
TRMRF
Trimming data reset detection flag
LVD2RF
Voltage detection reset detection flag
LVD1RF
Voltage detection reset detection flag
SYSRF
System clock reset detection flag
WDTRF
Watchdog timer reset detection flag
Note IRSTSR initialized external reset input power-on reset. Note Care must taken system designing since IRSTSR fulfill functions disturbing noise other effects. Note IRSTSR<FCLR> initialized power-on reset, external reset input internal reset factor. Note IRSTSR<FCLR> write 0x71 SYSCR4. This enables IRSTSR<FCLR> internal factor reset detection status register clear "0". IRSTSR<FCLR> cleared automatically after initializing internal factor reset detection status register. Note After IRSTSR<FCLR> modified, SYSCR4 should written 0x71 (Enable code IRSTSR<FCLR> NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> enabled unexpected timing. Note IRSTSR read "0".
2.4.3
Functions
power-on reset, external reset input internal factor reset signals input warm-up circuit clock generator. During reset, warm-up counter circuit reset, peripheral circuits reset. After reset released, warm-up counter starts counting high frequency clock (fc), executes warm-up operation that follows reset release. During warm-up operation that follows reset release, trimming data loaded from non-volatile exclusive memory adjustment ladder resistor that generates comparison voltage power-on reset voltage detection circuits. When warm-up operation that follows reset release finished, starts execution program from reset vector address stored addresses 0xFFFE 0xFFFF. When reset signal input during warm-up operation that follows reset release, warm-up counter circuit reset. reset operation common power-on reset, external reset input internal factor resets, except initialization some special function registers initialization voltage detection circuits. When reset applied, peripheral circuits become states shown Table 2-5.
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Table Initialization Built-in Hardware Reset Operation Status after Release
Built-in hardware During reset During warm-up operation that follows reset release mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Oscillation enabled Oscillation disabled Start Disabled Disabled enabled Refer map. Immediately after warm-up operation that follows reset release mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Oscillation enabled Oscillation disabled Stop Enabled Disabled enabled Refer map.
Program counter (PC)
mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Oscillation enabled Oscillation disabled Reset Disabled Disabled enabled Refer map.
Stack pointer (SP) General-purpose registers Register bank selector (RBS) Jump status flag (JF) Zero flag (ZF) Carry flag (CF) Half carry flag (HF) Sign flag (SF) Overflow flag (VF) Interrupt master enable flag (IMF) Individual interrupt enable flag (EF) Interrupt latch (IL) High-frequency clock oscillation circuit Low-frequency clock oscillation circuit Warm-up counter Timing generator prescaler divider Watchdog timer Voltage detection circuit port status Special function register
Note: voltage detection circuits disabled external reset input power-on reset only.
2.4.4
Reset Signal Generating Factors
Reset signals generated each factor follows:
2.4.4.1
External reset input (RESET input)
Port also used RESET pin, serves RESET after power turned supply voltage lower than recommended operating voltage range, example, when power turned supply voltage raised operating voltage range with RESET kept level, reset applied after oscillation stabilized. supply voltage within recommended operating voltage range, RESET kept level with stabilized oscillation, then reset applied. each case, after reset applied, released turning RESET warm-up operation that follows reset release gets started.
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Note: When supply voltage equal lower than detection voltage power-on reset circuit, power-on reset remains active, even RESET turned "H".
Operating voltage
Reset time RESET CPU/peripheral circuits reset During reset Warm-up operation peripheral circuits start operation
Figure 2-15 External Reset Input (when power turned
Operating voltage
Reset time RESET During reset Reset signal Warm-up operation peripheral circuits start operation
Figure 2-16 External Reset Input (when power stabilized)
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2.4.4.2
Power-on reset
power-on reset internal factor reset that occurs when power turned When power supply voltage goes supply voltage equal lower than releasing voltage power-on reset circuit, reset signal generated higher than releasing voltage power-on reset circuit, reset signal released. When power supply voltage goes down, supply voltage equal lower than detecting voltage power-on reset circuit, reset signal generated. Refer "Power-on Reset circuit".
2.4.4.3
Voltage detection reset
voltage detection reset internal factor reset that occurs when detected that supply voltage reached predetermined detection voltage. Refer "Voltage Detection Circuit".
2.4.4.4
Watchdog timer reset
watchdog timer reset internal factor reset that occurs when overflow watchdog timer detected. Refer "Watchdog Timer".
2.4.4.5
System clock reset
system clock reset internal factor reset that occurs when detected that oscillation enable register combination that puts into deadlock. Refer "Clock Control Circuit".
2.4.4.6
Trimming data reset
trimming data reset internal factor reset that occurs when trimming data latched internal circuit broken down during operation noise other factors. trimming data data provided adjustment ladder resistor that generates comparison voltage power-on reset voltage detection circuits. This loaded from non-volatile exclusive memory during warm-up time that follows reset release (tPWUP) latched into internal circuit. trimming data loaded from non-volatile exclusive memory during warm-up operation that follows reset release abnormal, IRSTSR<TRMDS> "1". When IRSTSR<TRMDS> read initialize routine immediately after reset release, trimming data need reloaded generating internal factor reset, such system clock reset, activating warm-up operation again. IRSTSR<TRMDS> still after repeated reading, detection voltage voltage detection circuit power-on reset circuit does satisfy characteristic specified electric characteristics. Design system that system will damaged such case.
2.4.4.7
Flash standby reset
flash standby reset internal factor reset generated reading writing data flash memory while standby. Refer "Flash Memory".
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2.4.4.8
Internal factor reset detection status register
reading internal factor reset detection status register IRSTSR after release internal factor reset, except power-on reset, factor which causes reset detected. internal factor reset detection status register initialized external reset input power-on reset. IRSTSR<FCLR> write 0x71 SYSCR4. This enables IRSTSR<FCLR> internal factor reset detection status register clear "0". IRSTSR<FCLR> cleared automatically after initializing internal factor reset detection status register.
Note Care must taken system designing since IRSTSR fulfill functions disturbing noise other effects. Note After IRSTSR<FCLR> modified, SYSCR4 should written 0x71 (Enable code IRSTSR<FCLR> NORMAL mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> enabled unexpected timing.
2.4.4.9
external reset input port
external reset input port, keep external reset input level until power turned warm-up operation that follows reset release finished. After warm-up operation that follows reset release finished, P1PU0 P1CR0 "0", connect pull-up resistor port. Then SYSCR3<RSTDIS> write 0xB2 SYSCR4. This disables external reset function makes external reset input usable normal port. external reset when used port, P1PU0 P1CR0 connect pull-up resistor input mode. Then clear SYSCR3<RSTDIS> write 0xB2 SYSCR4. This enables external reset function makes usable external reset input pin.
Note switch external reset input port switch used port external reset input pin, when stabilized level. Switching function when level input cause reset. Note external reset input used port, statement which clears SYSCR3<RSTDIS> written program. abnormal execution program, external reset input port changed external reset input unexpected timing. Note After SYSCR3<RSTDIS> modified, SYSCR4 should written 0xB2 (Enable code SYSCR3<RSTDIS>) NORMAL1 mode when fcgck fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> enabled unexpected timing.
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Revision History
Description "2.3.4.1 Warm-up counter operation when oscillation enabled hardware" Fixed specification from T.B.D. 0x66.
RA001 "Figure 2-15 External Reset Input (when power turned on)" "Figure 2-16 External Reset Input (when power stabilized)" Deleted "Recommended".
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Revision History TMP89FS60
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Interrupt Control Circuit
TMP89FS60 total interrupt sources excluding reset. Interrupts nested with priorities. Three internal interrupt sources non-maskable while rest maskable. Interrupt sources provided with interrupt latches (IL), which hold interrupt requests, have independent vector addresses. When request interrupt generated, interrupt latch "1", which requests accept interrupt. Acceptance interrupts enabled disabled software using interrupt master enable flag (IMF) individual enable flag (EF) each interrupt source. multiple maskable interrupts generated simultaneously, interrupts accepted order descending priority. priorities determined interrupt priority change control register (ILPRS1-ILPRS6) Levels determined hardware basic priorities. However, there prioritized interrupt sources among non-maskable interrupts.
Interrupt sources
Enable condition
Interrupt latch
Vector Address (MCU mode) RVCTR=0 enabled 0xFFFE 0xFFFC 0xFFFC 0xFFF8 0xFFF6 0xFFF4 0xFFF2 0xFFF0 0xFFEE 0xFFEC 0xFFEA 0xFFE8 0xFFE6 0xFFE4 0xFFE2 0xFFE0 0xFFDE 0xFFDC 0xFFDA 0xFFD8 0xFFD6 0xFFD4 0xFFD2 0xFFD0 0xFFCE 0xFFCC 0xFFCA 0xFFC8 RVCTR=1 enabled 0x01FC 0x01FC 0x01F8 0x01F6 0x01F4 0x01F2 0x01F0 0x01EE 0x01EC 0x01EA 0x01E8 0x01E6 0x01E4 0x01E2 0x01E0 0x01DE 0x01DC 0x01DA 0x01D8 0x01D6 0x01D4 0x01D2 0x01D0 0x01CE 0x01CC 0x01CA 0x01C8
Basic priority
Internal/ External Internal Internal Internal Internal Internal Internal Internal External Internal Internal Internal Internal Internal Internal Internal External External External External External Internal Internal Internal Internal Internal Internal Internal
(Reset) INTSWI INTUNDEF INTWDT INTWUC INTTBT INTRXD0 INTSIO0 INTTXD0 INT5 INTVLTD INTADC INTRTC INTTC00 INTTC01 INTTCA0 INTSBI0/INTSIO0 INT0 INT1 INT2 INT3 INT4 INTTCA1 INTRXD1/INTSIO1 INTTXD1 INTTC02 INTTC03 INTRXD2 INTTXD2
Non-maskable Non-maskable Non-maskable Non-maskable EIRL<EF4> EIRL<EF5> EIRL<EF6> EIRL<EF7> EIRH<EF8> EIRH<EF9> EIRH<EF10> EIRH<EF11> EIRH<EF12> EIRH<EF13> EIRH<EF14> EIRH<EF15> EIRE<EF16> EIRE<EF17> EIRE<EF18> EIRE<EF19> EIRE<EF20> EIRE<EF21> EIRE<EF22> EIRE<EF23> EIRD<EF24> EIRD<EF25> EIRD<EF26> EIRD<EF27>
ILL<IL3> ILL<IL4> ILL<IL5> ILL<IL6> ILL<IL7> ILH<IL8> ILH<IL9> ILH<IL10> ILH<IL11> ILH<IL12> ILH<IL13> ILH<IL14> ILH<IL15> ILE<IL16> ILE<IL17> ILE<IL18> ILE<IL19> ILE<IL20> ILE<IL21> ILE<IL22> ILE<IL23> ILD<IL24> ILD<IL25> ILD<IL26> ILD<IL27>
Note watchdog timer interrupt (INTWDT), clear WDCTR<WDTOUT> "Reset request" after reset released). details, "Watchdog Timer". Note 0xFFFA 0xFFFB function interrupt vectors option codes serial PROM mode. details, "Serial PROM Mode". Note Vector address areas changed SYSCR3<RVCTR> setting. assign vector address areas RAM, SYSCR3<RVCTR> SYSCR3<RAREA> "1".
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Interrupt Control Circuit
TMP89FS60
Note SYSCR3<RVCTR> serial PROM mode. interrupt generated with SYSCR3<RVCTR> ="0", software refers vector area BOOTROM user cannot
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Non-maskable interrupts
Interrupt source
IL17 IL18 IL19 IL20 IL21
Maskable interrupt priority change circuit
Interrupt source
Maskable interrupts
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Priority encoder
Decoder IDLE1/2,SLEEP1/2 Mode clear request Interrupt request
INTSWI INTUNDEF
Internal factor reset
INTWDT
Configuration
vector read signal
Interrupt source IL10 IL11 IL12 IL13 IL14 IL15 IL16
clear signal vector read signal
Interrupt source
Interrupt source
Interrupt source
Interrupt source
Interrupt source
Interrupt source
(Interrupt master enable flag)
Interrupt source
Figure Interrupt Control Circuit
IL27
Page
ILPRS6
Interrupt source
Interrupt source
Interrupt accept instruction Internal factor reset Instruction write [RET1]1 instruction (only when before interrupt acceptance) Instruction write [EI] instruction [RETN] instruction (only when before interrupt acceptance)
Interrupt source
Interrupt source
Interrupt source
Interrupt source
Interrupt source
Interrupt source27
ILPRS1
ILPRS2
ILPRS3
ILPRS4
EF27 IL27 reading
Data Address
Vector address generation
TMP89FS60
Interrupt Control Circuit
Interrupt Latches (IL27 IL3) TMP89FS60
Interrupt Latches (IL27 IL3)
interrupt latch provided each interrupt source, except software interrupt undefined instruction execution interrupt. When interrupt request generated, latch "1", requested accept interrupt acceptance enabled. interrupt latch cleared immediately after interrupt accepted. interrupt latches initialized during reset. interrupt latches located addresses 0x0FE0, 0x0FE1, 0x0FE2, 0x0FE3 area. Each latch cleared individually instruction. However, interrupt latches cannot cleared instructions. read-modify-write instruction, such manipulation operation instruction, because clear interrupt requests generated while instruction executed. Interrupt latches cannot using instruction. Writing interrupt latch equivalent denying clearing interrupt latch, setting interrupt latch. Since interrupt latches read instructions, status interrupt requests monitored software.
Note: main program, before manipulating interrupt latch (IL), sure clear master enable flag (IMF) (Disable interrupt instruction). Then required after operating (Enable interrupt instruction). interrupt service routine, becomes automatically need cleared normally. However, using multiple interrupt interrupt service routine, manipulate before setting "1".
Example Clears interrupt latches
(ILL), 0y00111111 (ILH), 0y11101000 IL12, IL10
Example Reads interrupt latches
(ILL) ILH,
Example Tests interrupt latches
TEST (ILL). SSET IL7=1 then jump
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TMP89FS60
Interrupt Enable Register (EIR)
interrupt enable register (EIR) enables disables acceptance interrupts, except non-maskable interrupts (software interrupt, undefined instruction interrupt watchdog interrupt). Non-maskable interrupts accepted regardless contents EIR. consists interrupt master enable flag (IMF) individual interrupt enable flags (EF). These registers located addresses 0x003A, 0x003B, 0x003C, 0x003D area, they read written instructions (including read-modify-write instructions such manipulation operation instructions).
3.3.1
Interrupt master enable flag (IMF)
interrupt master enable flag (IMF) enables disables acceptance maskable interrupts. Clearing disables acceptance maskable interrupts. Setting enables acceptance interrupts that specified individual interrupt enable flags. When interrupt accepted, stacked then cleared "0", which temporarily disables subsequent maskable interrupts. After interrupt service routine executed, stacked data, which status before interrupt acceptance, reloaded return interrupt instruction [RETI]/[RETN]. located EIRL (Address: 0x03A SFR), read written instructions. normally cleared [EI] [DI] instructions respectively. During reset, initialized "0".
3.3.2
Individual interrupt enable flags (EF27 EF4)
Each these flags enables disables acceptance maskable interrupt. Setting corresponding individual interrupt enable flag enables acceptance interrupt, setting disables acceptance. During reset, individual interrupt enable flags initialized maskable interrupts accepted until flags "1".
Note:In main program, before manipulating interrupt enable flag (EF), sure clear master enable flag (IMF) (Disable interrupt instruction). Then required after operating (Enable interrupt instruction). interrupt service routine, becomes automatically need cleared normally. However, using multiple interrupt interrupt service routine, manipulate before setting "1".
Example: Enables interrupts individually sets
(EIRL), 0y1110100010100000 EF15 EF13, EF11, EF7, Note: should set.
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Interrupt Control Circuit
Interrupt Enable Register (EIR) TMP89FS60
Interrupt latch (ILL)
(0x0FE0) Symbol Read/Write After reset Function INTTXD0 INTRXD0 INTSIO0 INTTBT INTWUC INTWDT
Interrupt latch (ILH)
(0x0FE1) Symbol Read/Write After reset Function IL15 INTSBI0/ INTSIO0 IL14 INTTCA0 IL13 INTTC01 IL12 INTTC00 IL11 INTRTC IL10 INTADC INTVLTD INT5
Interrupt latch (ILE)
(0x0FE2) Symbol Read/Write After reset Function IL23 INTTXD1 IL22 INTRXD1/ INTSIO1 IL21 INTTCA1 IL20 INT4 IL19 INT3 IL18 INT2 IL17 INT1 IL16 INT0
Interrupt latch (ILD)
(0x0FE3) Symbol Read/Write After reset Function IL27 INTTXD2 IL26 INTRXD2 IL25 INTTC03 IL24 INTTC02
Read Interrupt latch interrupt request Interrupt request
Write Clears interrupt request (Notes Does clear interrupt request (Interrupt writing "1".)
IL27
interrupt request Interrupt request
Note read-only register. Writing register does affect interrupt latch. Note main program, before manipulating interrupt latch (IL), sure clear interrupt master enable flag (IMF) (Disable interrupt instruction). Then required after operating (Enable interrupt instruction). interrupt service routine, becomes automatically need cleared normally. However, using multiple interrupt interrupt service routine, manipulate before setting "1". Note clear with read-modify-write instructions such operations. Note When read instruction executed ILL, bits read "0". Other unused bits read "0".
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TMP89FS60
Interrupt enable register (EIRL)
EIRL (0x003A) Symbol Read/Write After reset INTTXD0 Function INTRXD0 INTSIO0 INTTBT INTWUC Interrupt master enable flag
Interrupt enable register (EIRH)
EIRH (0x003B) Symbol Read/Write After reset Function EF15 INTSBI0/ INTSIO0 EF14 INTTCA0 EF13 INTTC01 EF12 INTTC00 EF11 INTRTC EF10 INTADC INTVLTD INT5
Interrupt enable register (EIRE)
EIRE (0x003C) Symbol Read/Write After reset Function EF23 INTTXD1 EF22 INTRXD1/ INTSIO1 EF21 INTTCA1 EF20 INT4 EF19 INT3 EF18 INT2 EF17 INT1 EF16 INT0
Interrupt enable register (EIRD)
EIRD (0x003D) Symbol Read/Write After reset Function EF27 INTTXD2 EF26 INTRXD2 EF25 INTTC03 EF24 INTTC02
EF27
Individual interrupt enable flag (Specified each bit) Interrupt master enable flag
Disables acceptance each maskable interrupt. Enables acceptance each maskable interrupt. Disables acceptance maskable interrupts. Enables acceptance maskable interrupts.
Note interrupt enable flag (EF15 EF4) same time. Note main program, before manipulating interrupt enable flag (EF), sure clear master enable flag (IMF) (Disable interrupt instruction). Then required after operating (Enable interrupt instruction) interrupt service routine, becomes automatically need cleared normally. However, using multiple interrupt interrupt service routine, manipulate before setting "1". Note When read instruction executed EIRL, bits read "0". Other unused bits read "0".
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Interrupt Control Circuit
Maskable Interrupt Priority Change Function TMP89FS60
Maskable Interrupt Priority Change Function
priority maskable interrupts (IL4 IL27) changed four levels, Levels regardless basic priorities Interrupt priorities changed interrupt priority change control register (ILPRS1 ILPRS6). raise interrupt priority, Level larger number. lower interrupt priority, Level smaller number. When different maskable interrupts generated simultaneously same level, interrupt with higher basic priority processed preferentially. example, when ILPRS1 register 0xC0 interrupts generated same time, preferentially processed (provided that have been enabled). After reset released, maskable interrupts priority level (the lowest priority).
Note: main program, before manipulating interrupt priority change control register (ILPRS1 sure clear master enable flag (IMF) (Disable interrupt instruction). required after operating ILPRS1 (Enable interrupt instruction). interrupt service routine, becomes automatically need cleared normally. However, using multiple interrupt interrupt service routine, manipulate ILPRS1 before setting "1".
Interrupt priority change control register
ILPRS1 (0x0FF0) Symbol Read/Write After reset IL07P IL06P IL05P IL04P
IL07P IL06P IL05P IL04P
Sets interrupt priority IL7. Sets interrupt priority IL6. Sets interrupt priority IL5. Sets interrupt priority IL4.
Level (lower priority) Level Level Level (higher priority)
Interrupt priority change control register
ILPRS2 (0x0FF1) Symbol Read/Write After reset IL11P IL10P IL09P IL08P
IL11P IL10P IL09P IL08P
Sets interrupt priority IL11. Sets interrupt priority IL10. Sets interrupt priority IL9. Sets interrupt priority IL8.
Level (lower priority) Level Level Level (higher priority)
Interrupt priority change control register
ILPRS3 (0x0FF2) Symbol Read/Write After reset IL15P IL14P IL13P IL12P
IL15P IL14P IL13P IL12P
Sets interrupt priority IL15. Sets interrupt priority IL14. Sets interrupt priority IL13. Sets interrupt priority IL12.
Level (lower priority) Level Level Level (higher priority)
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TMP89FS60
Interrupt priority change control register
ILPRS4 (0x0FF3) Symbol Read/Write After reset IL19P IL18P IL17P IL16P
IL19P IL18P IL17P IL16P
Sets interrupt priority IL19. Sets interrupt priority IL18. Sets interrupt priority IL17. Sets interrupt priority IL16.
Level (lower priority) Level Level Level (higher priority)
Interrupt priority change control register
ILPRS5 (0x0FF4) Symbol Read/Write After reset IL23P IL22P IL21P IL20P
IL23P IL22P IL21P IL20P
Sets interrupt priority IL23. Sets interrupt priority IL22. Sets interrupt priority IL21. Sets interrupt priority IL20.
Level (lower priority) Level Level Level (higher priority)
Interrupt priority change control register
ILPRS6 (0x0FF5) Symbol Read/Write After reset IL27P IL26P IL25P IL24P
IL27P IL26P IL25P IL24P
Sets interrupt priority IL27. Sets interrupt priority IL26. Sets interrupt priority IL25. Sets interrupt priority IL24.
Level (lower priority) Level Level Level (higher priority)
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Interrupt Control Circuit
Interrupt Sequence TMP89FS60
Interrupt Sequence
interrupt request, which raised interrupt latch, held, until interrupt accepted interrupt latch cleared resetting instruction. Interrupt acceptance sequence requires 8-machine cycles after completion current instruction. interrupt service task terminates upon execution interrupt return instruction [RETI] (for maskable interrupts) [RETN] (for non-maskable interrupts).
3.5.1
Initial Setting
Using interrupt requires specifying (stack pointer) advance. 16-bit register pointing start address stack. post-decremented when subroutine call push instruction executed when interrupt request accepted. pre-incremented when return instruction executed. Therefore, stack becomes deeper toward lower stack location addresses. sure reserve stack area having appropriate size based setting. initialized 00FFH after reset. need change right after reset when interrupt master enable flag (IMF) "0".
Example setting
023FH SP+04H 0010H 023FH 0010H
3.5.2
Interrupt acceptance processing
Interrupt acceptance processing packaged follows. interrupt master enable flag (IMF) cleared order disable acceptance following interrupt. interrupt latch (IL) interrupt source accepted cleared "0". contents program counter (PC) program status word, including interrupt master enable flag (IMF), saved (Pushed) stack sequence IMF, PCH, PCL. Meanwhile, stack pointer (SP) decremented entry address (Interrupt vector) corresponding interrupt service program, loaded vector table, transferred program counter. instruction stored entry address interrupt service program executed.
Note:When contents saved stack, contents register bank also saved.
Example: Correspondence between vector table address INTTBT entry address interrupt service program
Vector table address Vector table address
0xFFF4 0xFFF5
0x03 0xD2
0xD203 0xD204
0x0F 0x06
Figure Vector table address Entry address
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TMP89FS60
maskable interrupt accepted until even maskable interrupt requested interrupt service routine. order utilize nested interrupt service, must interrupt service program. this case, acceptable interrupt sources selectively enabled individual interrupt enable flags. avoid overloaded nesting, clear individual interrupt enable flag whose interrupt currently serviced, before setting "1". non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests.
3.5.3
Saving/restoring general-purpose registers
During interrupt acceptance processing, program counter (PC) program status word (PSW, includes IMF) automatically saved stack, general purpose registers not. These registers must saved software necessary. When multiple interrupt services nested, also necessary avoid using same data memory area saving registers. following methods used save/restore general-purpose registers.
3.5.3.1
Using PUSH instructions
save only specific register, PUSH instructions available.
Example :Using PUSH instructions
PINTxx PUSH Interrupt processing RETI Restore register RETURN Save register
Acceptance Interrupt execution PUSH instruction execution instruction
Address (Example) execution RETI instruction
Figure Saving/restoring general-purpose registers
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Interrupt Control Circuit
Interrupt Sequence TMP89FS60
3.5.3.2
Using data transfer instructions
save only specific register without nested interrupts, data transfer instructions available.
Example :Save/store register using data transfer instructions
PINTxx: Interrupt processing RETI (GSAVA) Restore register RETURN (GSAVA), Save register
Main task Interrupt acceptance Interrupt service task Saving registers
Interrupt return
Restoring registers
Figure Saving/Restoring General-purpose Registers under Interrupt Processing
3.5.3.3
Using register bank save/restore general-purpose registers
non-multiple interrupt handling, register bank function used save/restore generalpurpose registers time. register bank function saves (switches) general-purpose registers executing register bank manipulation instruction (such RBS,1) beginning interrupt service task. unnecessary re-execute register bank manipulation instruction interrupt service task because executing RETI instruction makes return automatically register bank that being used main task according content PSW.
Note: register banks (BANK0 BANK1) available. Each bank consists 8-bit general-purpose registers 16-bit general-purpose registers IY).
Example :Saving/restoring registers, using instruction transfer with data memory (with main task using register bank BANK0)
PINTxx: Interrupt processing RETI RETURN (Makes return automatically BANK0 that being used main task when restored) RBS, Switches register bank BANK1
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TMP89FS60
Main task Interrupt acceptance Interrupt service task
register bank BANK0 use. (RBS),1 Switching occurs register bank BANK1.
Interrupt return
return made automatically register bank BANK0.
Figure Saving/Restoring General-purpose Registers under Interrupt Processing
3.5.4
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform follows.
[RETI]/[RETN] Interrupt Return Program counter (PC) program status word (register bank) restored from stack. Stack pointer (SP) incremented
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Interrupt Control Circuit
Software Interrupt (INTSW) TMP89FS60
Software Interrupt (INTSW)
Executing instruction generates software interrupt immediately starts interrupt processing (INTSW top-priority interrupt). instruction only address error detection debugging described below.
3.6.1
Address error detection
0xFF read some cause such noise attempts fetch instruction from non-existent memory address. Code 0xFF instruction, software interrupt generated address error detected. address error detection range further expanded writing 0xFF unused areas program memory.
3.6.2
Debugging
Debugging efficiency increased placing instruction software break point setting address.
Undefined Instruction Interrupt (INTUNDEF)
When tries fetch execute instruction that defined, INTUNDEF generated starts interrupt processing. INTUNDEF accepted even a
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